CN105513943B - A kind of production method of semiconductor devices - Google Patents
A kind of production method of semiconductor devices Download PDFInfo
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- CN105513943B CN105513943B CN201410486976.4A CN201410486976A CN105513943B CN 105513943 B CN105513943 B CN 105513943B CN 201410486976 A CN201410486976 A CN 201410486976A CN 105513943 B CN105513943 B CN 105513943B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 51
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000005516 engineering process Methods 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 238000005520 cutting process Methods 0.000 claims abstract description 11
- 239000013078 crystal Substances 0.000 claims description 12
- 230000008018 melting Effects 0.000 claims description 8
- 238000002844 melting Methods 0.000 claims description 8
- 230000005496 eutectics Effects 0.000 claims description 4
- 239000003292 glue Substances 0.000 abstract description 6
- 235000012431 wafers Nutrition 0.000 description 108
- 239000002390 adhesive tape Substances 0.000 description 6
- 239000000126 substance Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 230000011218 segmentation Effects 0.000 description 4
- 238000003698 laser cutting Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- KRSIOWCOUNWLJY-UHFFFAOYSA-N [Si+4].[O-2].[O-2].[Ti+4].[Si+4] Chemical compound [Si+4].[O-2].[O-2].[Ti+4].[Si+4] KRSIOWCOUNWLJY-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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Abstract
The present invention provides a kind of production method of semiconductor devices, including：First wafer and the second wafer are provided, carry out the first bonding technology, by the front of first wafer and the positive engagement of second wafer；First is carried out to the back side of second wafer to be thinned；Third wafer is provided, silicon hole is formed in the third wafer；The second bonding technology is carried out, by the back side of second wafer and the positive engagement of the third wafer；Deep deburring is carried out to first wafer, second wafer and the third wafer that stack gradually since the back side of first wafer；Second is carried out to the back side of first wafer to be thinned；Third is carried out to the back side of the third wafer to be thinned, so that the bottom of the silicon hole is exposed from the back side of the third wafer；Carry out cutting technique.The present invention method, edge caused by gap caused by greatly reducing glue burst apart problem appearance risk, simplify technological process, reduce production cost.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of production method of semiconductor devices.
Background technology
In multiple-level stack wafer-level packaging, often it is required for that place is thinned to each layer crystal circle (wafer) progress backgrind
Reason finally carries out crystal grain (die) and cuts.And edge is easily caused during multilayer wafer is thinned and is burst apart (edge
chipping).When crystal grain cutting is carried out to multilayer wafer, it is also necessary to which point multistep carries out.
As shown in Fig. 2, the process flow chart for existing multiple-level stack wafer-level packaging, as can be seen from Fig., current
Technological process is：Step 1: melting bonding is carried out to CMOS wafer and MEMS wafer；Step 2: deburring is carried out to MEMS wafer
Processing；Step 3: backgrind is carried out to MEMS wafer；Step 4: the subsequent technique processing procedure at the back side is performed to MEMS wafer；Step
Rapid five, as shown in Figure 1A, the front of through-hole (TSV) wafer 103 and the back side of MEMS wafer 102 are subjected to eutectic bonding；Step
6th, as shown in Figure 1B, glue 104 is carried out to the edge for stacking wafer to fill the cavity of crystal round fringes；Step 7: to CMOS crystalline substances
Circle is ground thinned；Step 8: as shown in Figure 1B, CMOS wafer 101 and MEMS wafer 102 are cut.Step 9: such as
Shown in Fig. 1 C, backgrind adhesive tape 105 is pasted at the back side of CMOS wafer；Step 10: as shown in Figure 1 C, TSV wafer is carried out
Backgrind is to expose through-hole；Step 11: carry out the subsequent technique of TSV；Step 12: as shown in figure iD, cut TSV wafer
103。
Prior art method, CMOS wafer is ground be thinned before, need first to the edge of wafer carry out glue
To fill the cavity of crystal round fringes, and since glue easily generates the risk that gap causes edge to burst apart, first to CMOS after grinding
Wafer and MEMS wafer carry out first step cutting.Later, due to the presence of Cutting Road, it is right after backgrind adhesive tape to need to paste
TSV wafer carries out backgrind to expose through-hole, and second step cutting is carried out to TSV wafer again after completing subsequent TSV techniques.Therefore
The method of the prior art needs to paste backgrind adhesive tape, and cut processing procedure including two steps, and technological process is complicated, of high cost.
Presence in view of the above problems, the present invention propose a kind of new production method.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problems, such as presently, there are, the present invention provides a kind of production method of semiconductor devices, including：
First wafer and the second wafer are provided, carry out the first bonding technology, by the positive and described of first wafer
The positive engagement of second wafer；
First is carried out to the back side of second wafer to be thinned；
Third wafer is provided, silicon hole is formed in the third wafer；
The second bonding technology is carried out, by the back side of second wafer and the positive engagement of the third wafer；
First wafer, second wafer and described since the back side of first wafer to stacking gradually
Three wafers carry out deep deburring；
Second is carried out to the back side of first wafer to be thinned；
Third is carried out to the back side of the third wafer to be thinned, so that the bottom of the silicon hole is from the third wafer
Expose at the back side；
Carry out cutting technique.
Further, first bonding technology is bonded for melting.
Further, second bonding technology is eutectic bonding technique.
Further, the width of the deep deburring is 2.5~3.5mm, and depth is 1000~1300 μm.
Further, it before the back side to second wafer carries out thinned step, further includes to second wafer
The step of carrying out the first deburring.
Further, the width of first deburring is 2~2.5mm.
Further, the described first thickness that rear second wafer is thinned is 20~60 μm.
Further, the described second thickness that rear first wafer is thinned is 100~300 μm.
Further, the thickness that the rear third wafer is thinned in the third is 100~200 μm.
Further, cmos device is formed on first wafer, MEMS device is formed on second wafer.
In conclusion production method according to the present invention, is carried out using deep edge-neatening craftwork para-linkage wafer at substep deburring
Reason so that can be continuously thinned with wafer frontside after para-linkage and the back side, the segmentation for realizing crystal grain, this hair are cut finally by a step
It is bright to has the following advantages：
1st, substep deburring processing is carried out using wafer after deep edge-neatening craftwork para-linkage, greatly reduces glue in the prior art
Caused by edge caused by gap burst apart problem appearance risk, for realize be bonded after wafer twin grinding advantage is provided；
2nd, by double side grinding process, without using backgrind adhesive tape, and the segmentation of crystal grain can be realized with a step, simplified
Technological process, reduces production cost.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
The section that the correlation step that Figure 1A -1D are thinned and are cut by the multiple-level stack wafer of the prior art obtains device shows
It is intended to；
The process flow chart that the step of Fig. 2 is the multiple-level stack wafer-level packaging of the prior art is implemented successively；
The correlation step institute acquisition device that Fig. 3 A-3E are thinned and cut for the multiple-level stack wafer of exemplary embodiment of the present
The diagrammatic cross-section of part；
The technological process that the step of Fig. 4 is the multiple-level stack wafer-level packaging of exemplary embodiment of the present is implemented successively
Figure.
Specific embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.Disclosure will be made thoroughly and complete, and will fully convey the scope of the invention on the contrary, providing these embodiments
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or during layer, then there is no elements or layer between two parties.It should be understood that although it can make
Various elements, component, area, floor and/or part are described with term first, second, third, etc., these elements, component, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another
One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and be used so as to describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention, which further includes, to be made
With the different orientation with the device in operation.For example, if the device overturning in attached drawing, then, is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented to other elements or features " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with
With other embodiment.
[exemplary embodiment]
Below with reference to the accompanying drawings the method for exemplary embodiment of the present is described in detail in 3A-3E and Fig. 4.
First, step S401 is performed, the first wafer and the second wafer be provided, carries out the first bonding technology, by described the
The front of one wafer and the positive engagement of second wafer.
Cmos device is formed on first wafer, including such as field-effect containing metal oxide layer semiconductor (MOSFET)
Integrated circuit (IC) semiconductor devices, can also include complementary MOSFET (CMOS), cmos image sensor and/or its
His suitable active and/or passive device.In embodiment, the first wafer includes by technological design based on CMOS and is formed
IC (or part thereof).
Second wafer is MEMS wafer, and MEMS device is formed in the MEMS wafer, can include accelerometer, return
Turn instrument, loudspeaker and sensor.Although not exclusively, sensor can be any group of following kind of sensor
It closes：Magnetic sensor, pressure sensor, humidity sensor, temperature sensor, chemical sensor, biosensor or inertia pass
Sensor.These MEMS device may also comprise one or more deposition materials, one or more jointing materials or for this MEMS
Device is unique or for the common other materials of other MEMS device.
The first bonding technology is carried out, by the front of first wafer and the positive engagement of second wafer.One
In a example, first bonding technology is bonded for melting, and the melting bonding can be silicon-silicon melting bonding, silicon-titanium dioxide
Silicon melting bonding or silica-silica melting bonding.But the above method is not limited to, art technology also can be used
Any applicable bonding method known to personnel.
Step S402 is performed, the first deburring is carried out to second wafer.Specifically, can be used any suitable method into
Row first deburring, such as laser cutting or machine cuts etc..Optionally, the width of the first deburring is 2~2.5mm.
Step S403 is performed, carrying out first to the back side of second wafer is thinned.In this step, it described first is thinned
Method can select method commonly used in the art, for example, may be used mechanical lapping, chemically mechanical polishing (CMP), chemical attack,
The methods of plasma etching.In one example, the described first thickness that rear second wafer is thinned is 20~60 μm.
Later, it can also include performing step S404, back technique is performed, such as in institute at the back side of second wafer
The back side for stating the second wafer forms the processing steps such as mask layer and etching, to form various components or interconnection structure, example
Such as silicon hole.
Further, the first bonding interface layer can also be formed at the back side of the second wafer.In an example, the first bonding
Boundary layer includes aluminium.The example compositions of first bonding interface layer can also include albronze, copper silmin.It can pass through
CVD, physical vapour deposition (PVD), plating, and/or other suitable techniques are formed.In embodiment, the first bonding interface layer or its portion
Divide a part for the multilayer interconnection structure for being semiconductor devices.Further, the first bonding interface layer can include titanium, nickel, copper,
Gold, silver, indium, tin, its alloy or its combination.
Step S405 is performed, third wafer is provided, the second bonding technology is carried out, by the back side of second wafer and institute
State the positive engagement of third wafer.
Specifically, silicon hole is included in the third wafer.Illustratively, the silicon hole is vertical through hole.Further
Ground, the third wafer can also be the Silicon Wafer or glass material for including silicon hole.
The second bonding interface layer is formed in the front of the third wafer, in an example, the second bonding interface layer
Including aluminium.The example compositions of second bonding interface layer can also include albronze, copper silmin.CVD, object can be passed through
Physical vapor deposition, plating, and/or other suitable techniques are formed.In embodiment, second bonding interface layer or part thereof is half
A part for the multilayer interconnection structure of conductor device, such as a part for silicon hole.Further, the second bonding interface layer can be with
Including titanium, nickel, copper, gold, silver, indium, tin, its alloy or its combination.
As shown in Figure 3A, the front of the third wafer 303 is bonded with the back side of second wafer 302.
In one example, by eutectic bonding, by 303 positive second bonding interface layer of third wafer and second wafer
The first bonding interface layer engagement at 302 back sides, and then realize the heap of the first wafer 301, the second wafer 302 and third wafer 303
Stack structure.
Perform step S406, as shown in Figure 3B, since the back side of first wafer 301 to stack gradually described the
One wafer 301, second wafer 302 and the third wafer 303 carry out deep deburring.
Specifically, any suitable method can be used and carry out the deep deburring processing, such as laser cutting or machine cuts
Or the methods of anisotropic dry etch.In the present embodiment, the width of deep deburring is 2.5~3.5mm, depth for 1000~
1300μm。
Step S407 is performed, as shown in Figure 3 C, second is carried out to the back side of first wafer 301 and is thinned.
In this step, the thining method can select method commonly used in the art, for example, may be used mechanical lapping,
The methods of chemically-mechanicapolish polishing (CMP), chemical attack, plasma etching.Optionally, described second rear first wafer is thinned
301 thickness is 100~300 μm.
Step S408 is performed, as shown in Figure 3D, third is carried out to the back side of the third wafer 303 and is thinned, so that silicon leads to
Expose from the back side of third wafer 303 bottom of hole (not shown).Due to the integral thickness of encapsulating structure to be controlled, silicon hole
Depth is usually smaller than the thickness of wafer, to realize the purpose of interconnection, it is necessary to expose the bottom of silicon hole.And due to before
In step, the first wafer and the second wafer are not cut, therefore in the step, it can completely dispense with using adhesive tape is ground, i.e.,
Being thinned to third wafer 303 can be achieved.In this step, the third thining method can select side commonly used in the art
Method, such as mechanical lapping may be used, chemically-mechanicapolish polish the methods of (CMP), chemical attack, plasma etching.Optionally, institute
State third be thinned the rear third wafer thickness be 100~200 μm.
Step S409 is performed, performs the subsequent technique of silicon hole (TSV).Such as pass through thermal oxide at the back side of third wafer
The methods of metallization medium layer.In the damaging layer for removing certain wafer rear using wet method or dry etch process, after then carrying out
Continuous interconnection process such as redistribution lines (RDL), metal coupling (bump) etc..
Step S410 is performed, as shown in FIGURE 3 E, carries out cutting technique, wafer will be stacked and be divided into single crystal grain.Cutting
It is the process that wafer is divided into the complete chip of circuit system or crystal grain unit.This field may be used in the cutting method
Any method known to technical staff, such as physics cutting or laser cutting.
So far the encapsulation process to multiple-level stack wafer is completed.
In conclusion production method according to the present invention, is carried out using deep edge-neatening craftwork para-linkage wafer at substep deburring
Reason so that can be continuously thinned with wafer frontside after para-linkage and the back side, the segmentation for realizing crystal grain, this hair are cut finally by a step
It is bright to has the following advantages：
1st, substep deburring processing is carried out using wafer after deep edge-neatening craftwork para-linkage, greatly reduces glue in the prior art
Caused by edge caused by gap burst apart problem appearance risk, for realize be bonded after wafer twin grinding advantage is provided；
2nd, by double side grinding process, without using backgrind adhesive tape, and the segmentation of crystal grain can be realized with a step, simplified
Technological process, reduces production cost.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of production method of semiconductor devices, including：
First wafer and the second wafer are provided, carry out the first bonding technology, by the front of first wafer and described second
The positive engagement of wafer；
First is carried out to the back side of second wafer to be thinned；
Third wafer is provided, silicon hole is formed in the third wafer；
The second bonding technology is carried out, by the back side of second wafer and the positive engagement of the third wafer；
It is brilliant to first wafer, second wafer and the third that stack gradually since the back side of first wafer
Circle carries out deep deburring；
Second is carried out to the back side of first wafer to be thinned；
Third is carried out to the back side of the third wafer to be thinned, so that the bottom of the silicon hole is from the back side of the third wafer
Expose；
Cutting technique is carried out, to form single crystal grain.
2. production method according to claim 1, which is characterized in that first bonding technology is bonded for melting.
3. production method according to claim 1, which is characterized in that second bonding technology is eutectic bonding technique.
4. production method according to claim 1, which is characterized in that the width of the depth deburring is 2.5~3.5mm, deep
Spend is 1000~1300 μm.
5. production method according to claim 1, which is characterized in that carried out at the back side to second wafer thinned
Before step, the step of the first deburring is carried out to second wafer is further included.
6. production method according to claim 5, which is characterized in that the width of first deburring is 2~2.5mm.
7. production method according to claim 1, which is characterized in that described first is thinned the thickness of rear second wafer
It is 20~60 μm.
8. production method according to claim 1, which is characterized in that described second is thinned the thickness of rear first wafer
It is 100~300 μm.
9. production method according to claim 1, which is characterized in that the thickness of the rear third wafer is thinned in the third
It is 100~200 μm.
10. production method according to claim 1, which is characterized in that be formed with cmos device on first wafer, institute
It states and is formed with MEMS device on the second wafer.
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| CN108022836B (en) * | 2016-10-31 | 2021-04-06 | 中芯国际集成电路制造(上海)有限公司 | Grinding method of multilayer stacked wafer |
| CN109786234B (en) * | 2017-11-13 | 2021-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN110137096A (en) * | 2019-05-17 | 2019-08-16 | 武汉新芯集成电路制造有限公司 | A kind of bonding structure and its manufacturing method |
| CN114455536B (en) * | 2022-02-08 | 2025-06-20 | 季优科技（上海）有限公司 | Wafer-level three-dimensional packaging method and structure of MEMS gas sensor |
| CN114883187B (en) * | 2022-07-12 | 2022-09-06 | 成都功成半导体有限公司 | Processing technology for back surface of silicon carbide wafer |
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| FR2950734B1 (en) * | 2009-09-28 | 2011-12-09 | Soitec Silicon On Insulator | METHOD FOR BONDING AND TRANSFERRING A LAYER |
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| CN101399195A (en) * | 2007-09-26 | 2009-04-01 | 中芯国际集成电路制造(上海)有限公司 | Thinning method for backing side of wafer |
| CN101179038A (en) * | 2007-12-14 | 2008-05-14 | 清华大学 | Implementation method of three-dimensional integrated circuit without transfer wafer |
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