CN105512365B - The circuit emulation method of grid edge roughness effect in fin FET - Google Patents

Abstract

The invention discloses a circuit simulation method for gate edge roughness in a fin field effect transistor, which belongs to the field of microelectronic devices. The circuit simulation method is based on the predictability intensive model. Firstly, the rough gate edge is extracted from the electron microscope photo of the fin line, and its autocorrelation function is calculated, and then the calculation formula is used to obtain the fluctuation of the groove length under the influence of the fin edge roughness. The mean and variance are embedded in the simulation netlist of the circuit simulation software for circuit simulation, and the circuit performance parameters caused by the roughness of the fin edge can be obtained. The device characteristic fluctuation influence can be obtained very accurately by adopting the present invention, and all parameters can be adjusted with reference to the result obtained by TCAD Monte Carlo simulation. Compared with the traditional method, the subthreshold slope SS fluctuation of the device can be predicted, and the correlation between the subthreshold slope SS fluctuation and the threshold voltage V _th can be predicted.

Description

Circuit Simulation Method for Gate Edge Roughness Effect in FinFET

technical field

The invention belongs to the field of microelectronic devices and relates to a circuit simulation method for gate edge roughness in fin field effect transistors.

Background technique

With the gradual reduction of the scale of semiconductor devices, the influence of random fluctuations in the devices is becoming more and more difficult to ignore. The random fluctuation of the device is caused by the inevitable process uncertainty in the device manufacturing process, which will lead to the fluctuation of the electrical characteristics of the device, such as the threshold voltage, and further, it will inevitably cause the fluctuation of the circuit performance parameters. Fluctuations in circuit performance parameters will eventually lead to yield loss during chip fabrication. Therefore, circuit designers need to take into account the impact of random fluctuations in devices on circuit characteristics in advance when designing circuits, which requires a corresponding intensive model of random fluctuations that can be used for circuit simulation.

On the other hand, Fin Field Effect Transistors (FinFETs) are gradually replacing traditional planar devices and becoming the main force in the semiconductor industry. In fin field effect transistors, the sources of random fluctuations mainly include metal work function fluctuations, fin edge roughness (FER), and gate edge roughness (GER). The gate edge roughness can be extracted from the electron micrograph of the device. Gate edge roughness is generally characterized by a method based on autocorrelation function theory, and there are two main characterization parameters: mean square error Δ _GER and autocorrelation length Λ _GER . The mean square error Δ _GER characterizes the magnitude of the gate edge roughness, while the autocorrelation length Δ _GER characterizes the spatial variation period of the gate edge roughness. The values of these two characterization parameters are determined by the process.

Currently, there are no predictable intensive models for both fin edge roughness and gate edge roughness for use in circuit simulations. The traditional circuit simulation method simplifies the impact of random fluctuations on devices into the fluctuations in the threshold voltage of devices, which are directly added to the circuit simulation. However, this method has many limitations. First of all, this method is not predictive at all, that is, it cannot take into account fluctuations caused by device design parameters or process changes. Secondly, this method completely regards the influence of fluctuations on the device as the influence on the threshold voltage, ignoring the influence on other parameters of the device, such as the sub-threshold slope, which will lead to miscalculation of circuit fluctuations. Therefore, it is very necessary to propose an accurate and predictable circuit simulation method for the gate edge roughness of the fin field effect transistor.

Contents of the invention

The object of the present invention is to provide a circuit simulation method for the effect of gate edge roughness in a fin field effect transistor based on a predictable intensive model.

The circuit simulation method of the gate edge roughness effect in the fin field effect transistor provided by the present invention comprises the following steps:

1) Extract the rough gate edge from the electron microscope photo of the fin line, and calculate its autocorrelation function;

2) Using the formula μ(L _{g, eff} )=L _g

Obtain the mean and variance of L _{g, eff} fluctuation under the influence of fin edge roughness;

3) Embedding the mean and variance of the fluctuations of L _{g and eff} above into the simulation netlist of the circuit simulation software, and performing circuit simulation with the circuit simulation software, the circuit performance of the gate edge roughness effect can be obtained.

Among them, the rough grid edge is extracted from the electron microscope photo of the grid line, its autocorrelation function is calculated, and it is fitted with an appropriate function form, such as a Gaussian function, to obtain two characterization parameters of the grid edge roughness: root mean square Δ _GER and correlation length Λ _GER .

From the perspective of physical mechanism, the influence of gate edge roughness mainly lies in changing the effective length L _g,eff of the channel. Therefore, from the characterization parameters of the gate edge roughness obtained in 1 and the fin width W _Fin and fin height H _Fin of the fin field effect transistor used in the circuit simulation, and then calculate the resulting L _{g, eff} according to the following formula Mean and variance of fluctuations:

Mean value: μ(L _{g, eff} )=L _g

variance: (Applicable to dual-gate field effect transistors)

(Applicable to Tri-Gate Field Effect Transistor)

Here, R _GER (*) is the autocorrelation function of the fitted gate edge roughness in 1.

According to the above calculation formula, the groove length L _{g under the influence of gate edge roughness, the mean value and variance of eff} fluctuation are obtained, and added to the circuit simulation netlist, and the circuit simulation is performed with circuit simulation software, and the gate edge roughness can be obtained The resulting circuit fluctuations, and then get the fluctuations of circuit performance parameters.

The device characteristic fluctuation influence can be obtained very accurately by adopting the present invention, and all parameters can be adjusted with reference to the result obtained by TCAD Monte Carlo simulation. Compared with the traditional method, the fluctuation of the subthreshold slope SS of the device can be predicted, and the correlation between the subthreshold slope SS and the threshold voltage _Vth can be predicted.

Description of drawings

FIG. 1 is a schematic flow chart of the circuit simulation method of the present invention.

Fig. 2 is a schematic diagram of a fin field effect transistor of the present invention, wherein (a) a schematic side view of a fin field effect transistor; (b) a schematic top view of a fin field effect transistor with an ideal channel and a rough gate edge;

The extraction and characterization flow diagram of Fig. 3 grid edge roughness of the present invention, wherein (a) is the electron micrograph of grid edge roughness; (b) is the result that obtains from electron microscope extraction; (c) is the grid edge roughness Autocorrelation function is fitted with a Gaussian function, thereby obtaining a schematic diagram of the characteristic parameter mean square error _ΔGER and autocorrelation length _ΔGER ;

The schematic circuit diagram of Fig. 4 static random access memory SRAM;

The butterfly diagram of the SRAM obtained by the circuit simulation of Fig. 5;

Fig. 6 is a distribution diagram of the static noise margin SNM, which is the circuit performance parameter of the SRAM extracted from the SRAM butterfly diagram.

Specific implementation method

The circuit simulation method of the present invention will be described in detail below through examples and in conjunction with the accompanying drawings.

This example considers the influence of the gate edge roughness on the performance parameter of the static random access memory (SRAM) circuit in the dual-gate fin field effect transistor based on the SOI substrate - the static noise margin (SNM). The overall process is shown in Figure 1 Show. The basic structure and parameter definitions of the dual-gate FinFET are shown in Figure 2.

Specific steps:

1) As shown in Figure 3, according to the electron microscope photo of the grid, extract the rough grid edge, calculate its autocorrelation function, and use the Gaussian function Fitting is performed to obtain fitting parameters Δ _GER =2/3nm, Δ _GER =30nm.

2) Using the calculation formula of σL _g,eff in the double-gate fin field effect transistor, R _GER (*) adopts Gaussian form, and the mean value and variance of L _g are obtained as follows:

Mean value: μ(L _{g, eff} )=L _g

variance:

3) The L _g of the fin field effect transistor adopted in this example is 20nm, and the W _Fin is 10nm, therefore, the calculated

Mean value: μ(L _{g, eff} )=20nm

Standard deviation: σ(L _{g, eff} )=0.45nm

4) The schematic circuit diagram of the static random access memory (SRAM) is shown in FIG. 4 . Change the groove length in the SRAM simulation netlist to a Gaussian random variable with a mean value of 20nm and a standard deviation of 0.45nm, and select the Monte Carlo mode in the circuit simulation software HSPICE for circuit simulation.

5) According to the butterfly curve (as shown in FIG. 5 ) obtained by circuit simulation, the distribution of static noise margin (SNM) of the SRAM is extracted as shown in FIG. 6 .

The descriptions of the embodiments of the present invention have been given above for the understanding of the present invention. It should be understood that the present invention is not limited to the particular embodiments described herein, but is capable of various modifications, adaptations and substitutions, as now apparent to those skilled in the art, without departing from the scope of the present invention. Accordingly, the following claims are intended to cover such modifications and changes as fall within the true spirit and scope of this invention.

Claims (4)

1. A circuit simulation method of gate edge roughness effect in a fin field effect transistor, comprising the steps: 1) Extract the rough gate edge from the electron microscope photo of the fin line, and calculate its autocorrelation function; 2) Using the formula μ(L _{g, eff} )=L _g <mrow><msup><mi>&amp;sigma;</mi><mn>2</mn></msup><mrow><mo>(</mo><msub><mi>L</mi><mrow><mi>g</mi><mo>,</mo><mi>e</mi><mi>f</mi><mi>f</mi></mrow></msub><mo>)</mo></mrow><mo>=</mo><mfrac><mn>1</mn><mn>2</mn></mfrac><mo>&amp;CenterDot;</mo><mo>&amp;lsqb;</mo><msubsup><mi>&amp;Delta;</mi><mrow><mi>G</mi><mi>E</mi><mi>R</mi></mrow><mn>2</mn></msubsup><mo>+</mo><msub><mi>R</mi><mrow><mi>G</mi><mi>E</mi><mi>R</mi></mrow></msub><mrow><mo>(</mo><msub><mi>W</mi><mrow><mi>F</mi><mi>i</mi><mi>n</mi></mrow></msub><mo>)</mo></mrow><mo>&amp;rsqb;</mo></mrow> <mrow><msup><mi>&amp;sigma;</mi><mn>2</mn></msup><mrow><mo>(</mo><msub><mi>L</mi><mrow><mi>g</mi><mo>,</mo><mi>e</mi><mi>f</mi><mi>f</mi></mrow></msub><mo>)</mo></mrow><mo>&amp;ap;</mo><mfrac><mrow><mn>2</mn><mo>&amp;CenterDot;</mo><msubsup><mi>H</mi><mrow><mi>F</mi><mi>i</mi><mi>n</mi></mrow><mn>2</mn></msubsup></mrow><msup><mrow><mo>(</mo><mn>2</mn><mo>&amp;CenterDot;</mo><msub><mi>H</mi><mrow><mi>F</mi><mi>i</mi><mi>n</mi></mrow></msub><mo>+</mo><msub><mi>W</mi><mrow><mi>F</mi><mi>i</mi><mi>n</mi></mrow></msub><mo>)</mo></mrow><mn>2</mn></msup></mfrac><mo>&amp;CenterDot;</mo><mo>&amp;lsqb;</mo><msubsup><mi>&amp;Delta;</mi><mrow><mi>G</mi><mi>E</mi><mi>R</mi></mrow><mn>2</mn></msubsup><mo>+</mo><msub><mi>R</mi><mrow><mi>G</mi><mi>E</mi><mi>R</mi></mrow></msub><mrow><mo>(</mo><msub><mi>W</mi><mrow><mi>F</mi><mi>i</mi><mi>n</mi></mrow></msub><mo>)</mo></mrow><mo>&amp;rsqb;</mo></mrow> Obtain the average value and the variance of L _{g under the influence of fin edge roughness, eff} fluctuation, wherein L _g is the groove length of the fin field effect transistor in the formula, W _Fin is the fin width of the fin field effect transistor; H _Fin is the fin field effect transistor The fin height of the field effect transistor; _ΔGER is the root mean square of the gate edge roughness of the fin field effect transistor; _ΛGER is the correlation length of the gate edge roughness of the fin field effect transistor; L _{g, eff} is the fin field effect transistor The effective length of the effect transistor channel; μ(L _{g, eff} ) is the mean value of L _{g, eff} fluctuation; σ ² (L _{g, eff} ) is the variance of L _{g, eff} fluctuation; 3) Embed the mean and variance of the fluctuations of Lg _{and eff} above into the simulation netlist of the circuit simulation software, and use the circuit simulation software to perform circuit simulation to obtain the circuit performance of the gate edge roughness effect. 2. the circuit simulation method of gate edge roughness effect in the fin field effect transistor as claimed in claim 1, is characterized in that, adopts Gaussian function fitting in step 1), obtains two characterizing parameters of fin edge roughness: Root mean square Δ _FER and correlation length Δ _FER . 3. the circuit simulation method of gate edge roughness effect in the fin field effect transistor as claimed in claim 1, is characterized in that, step 3) adopts HSPICE circuit simulation software. 4. the circuit simulation method of gate edge roughness effect in the fin field effect transistor as claimed in claim 3 is characterized in that, adopts the Monte Carlo mode in the HSPICE circuit simulation software to carry out circuit simulation.