CN105517327A - Method for realizing via impedance matching through blind buried hole process - Google Patents
Method for realizing via impedance matching through blind buried hole process Download PDFInfo
- Publication number
- CN105517327A CN105517327A CN201510949447.8A CN201510949447A CN105517327A CN 105517327 A CN105517327 A CN 105517327A CN 201510949447 A CN201510949447 A CN 201510949447A CN 105517327 A CN105517327 A CN 105517327A
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- China
- Prior art keywords
- impedance
- via hole
- inductance
- blind
- design
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0776—Resistance and impedance
- H05K2201/0792—Means against parasitic impedance; Means against eddy currents
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention provides a method for realizing via impedance matching through a blind buried hole process, and relates to the field of electronics and PCB LAYOUT signal integrity design and simulation. According to the invention, the existing blind buried hole process is used, and via inductance is added artificially in design to offset the parasitic capacitance effect arising from a multilayer board. Therefore, matching between single-line impedance and differential impedance is realized.
Description
Technical field
The present invention relates to electronics and PCBLAYOUT Signal Integrity Design and emulation field, particularly relate to a kind of method that blind buried via hole technique realizes through hole impedance coupling.
Background technology
Along with the raising of Bus Speed, through hole impedance has become the problem that present high speed design generally will be considered.The impedance design conventional method of via hole is by designing the object to reaching through hole impedance coupling to the anti-pad of via hole and pad now.This method can alleviate the parasitic capacitance effect that via hole brings to a certain extent, alleviates the impact of the impedance mismatching that parasitic capacitance is brought.But the method is subject to technique and method for designing restriction, parasitic capacitance can only be reduced to a certain extent, and the coupling requirement of differential impedance can only be met, and the coupling requirement of single line impedance can not be met, thus can not perfect resolved impedance spectroscopy matching problem in multiple sliding cover.
Summary of the invention
In order to solve this problem, the present invention proposes a kind of method that blind buried via hole technique realizes through hole impedance coupling, making high-speed communication physical channel optimization, realizing the demand of higher rate communication.
The impedance of via hole is relevant with inductance with the parasitic capacitance of itself, and the larger impedance of inductance is larger, and the larger impedance of electric capacity is less.In multi-layer sheet situation, general capacity effect is greater than inductive effect, therefore general through hole impedance is less than normal.
The present invention utilizes existing buried blind via technique, increase via hole inductance artificial in design, is used for offsetting the parasitic capacitance effect brought of multi-layer sheet, realizes the coupling of single line impedance and differential impedance.
The inductance of via hole mainly comes from L1, and electric capacity mainly comes from C1, and C2 utilizes the mode of adding high-impedance transmission line between two blind holes to increase via hole inductance (L2).
Concrete operation step is:
1), three-dimensional modeling is carried out to this via hole result;
2) 3 D electromagnetic field simulation software, is utilized to emulate; Scanned pore structure and add the length of high-impedance transmission line;
3), to scanning result carry out analysis optimization, obtain the value of the structural parameters meeting differential impedance and single impedance.
The invention has the beneficial effects as follows
The present invention uses existing buried blind via technology, through hole impedance just can be made in design to reach optimization, meet the requirement of differential impedance and single line impedance simultaneously, adapt to the bus growth requirement of higher rate.
Accompanying drawing explanation
Fig. 1 is conventional via hole schematic diagram;
Fig. 2 is high impedance Via Design figure.
Embodiment
With reference to the accompanying drawings more detailed elaboration is carried out to content of the present invention below:
As shown in Figure 1, the impedance design of via hole becomes the indispensable part in high speed design, but existing difference through hole design is because technique well can not realize impedance matching with the reason in design, therefore can not make high-speed communication physical channel optimization, the demand of higher rate communication can not be realized.
As shown in Figure 2, a kind of method realizing through hole impedance coupling by blind buried via hole technique of the present invention, utilizes existing buried blind via technique, increase via hole inductance artificial in design, be used for offsetting the parasitic capacitance effect brought of multi-layer sheet, realize the coupling of single line impedance and differential impedance.
The inductance of via hole mainly comes from L1, and electric capacity mainly comes from C1, and C2 utilizes the mode of adding high-impedance transmission line between two blind holes to increase via hole inductance (L2).
Concrete operation step is:
1, three-dimensional modeling is carried out to this via hole result;
2,3 D electromagnetic field simulation software is utilized to emulate.Scanned pore structure and add the length of high-impedance transmission line;
3, analysis optimization is carried out to scanning result, obtain the value of the structural parameters meeting differential impedance and single impedance.
Claims (3)
1. one kind realizes the method for through hole impedance coupling by blind buried via hole technique, it is characterized in that, utilize existing buried blind via technique, increase via hole inductance artificial in design, be used for offsetting the parasitic capacitance effect brought of multi-layer sheet, realize the coupling of single line impedance and differential impedance.
2. method according to claim 1, is characterized in that, the inductance of via hole mainly comes from L1, and electric capacity mainly comes from C1, and C2 utilizes the mode of adding high-impedance transmission line between two blind holes to increase via hole inductance (L2).
3. method according to claim 2, is characterized in that, operating procedure is:
1), three-dimensional modeling is carried out to this via hole result;
2) 3 D electromagnetic field simulation software, is utilized to emulate; Scanned pore structure and add the length of high-impedance transmission line;
3), to scanning result carry out analysis optimization, obtain the value of the structural parameters meeting differential impedance and single impedance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510949447.8A CN105517327A (en) | 2015-12-18 | 2015-12-18 | Method for realizing via impedance matching through blind buried hole process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510949447.8A CN105517327A (en) | 2015-12-18 | 2015-12-18 | Method for realizing via impedance matching through blind buried hole process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105517327A true CN105517327A (en) | 2016-04-20 |
Family
ID=55724850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510949447.8A Pending CN105517327A (en) | 2015-12-18 | 2015-12-18 | Method for realizing via impedance matching through blind buried hole process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105517327A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110265761A (en) * | 2019-06-30 | 2019-09-20 | 瑞声精密制造科技(常州)有限公司 | A kind of transmission line |
| CN112867243A (en) * | 2021-01-06 | 2021-05-28 | 英韧科技(上海)有限公司 | Multilayer circuit board |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1916915A (en) * | 2005-08-19 | 2007-02-21 | 鸿富锦精密工业（深圳）有限公司 | Method for improving resistance of via hole |
| JP2007288180A (en) * | 2006-03-24 | 2007-11-01 | Kyocera Corp | Wiring structure, multilayered wiring board, and electronic device |
| US20130106528A1 (en) * | 2011-10-31 | 2013-05-02 | Samsung Electro-Mechanics Co., Ltd. | Asymmetrical multilayer substrate, rf module, and method for manufacturing asymmetrical multilayer substrate |
| CN105007682A (en) * | 2015-06-26 | 2015-10-28 | 浪潮电子信息产业股份有限公司 | PCB and circuit board |
-
2015
- 2015-12-18 CN CN201510949447.8A patent/CN105517327A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1916915A (en) * | 2005-08-19 | 2007-02-21 | 鸿富锦精密工业（深圳）有限公司 | Method for improving resistance of via hole |
| JP2007288180A (en) * | 2006-03-24 | 2007-11-01 | Kyocera Corp | Wiring structure, multilayered wiring board, and electronic device |
| US20130106528A1 (en) * | 2011-10-31 | 2013-05-02 | Samsung Electro-Mechanics Co., Ltd. | Asymmetrical multilayer substrate, rf module, and method for manufacturing asymmetrical multilayer substrate |
| CN105007682A (en) * | 2015-06-26 | 2015-10-28 | 浪潮电子信息产业股份有限公司 | PCB and circuit board |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110265761A (en) * | 2019-06-30 | 2019-09-20 | 瑞声精密制造科技(常州)有限公司 | A kind of transmission line |
| CN112867243A (en) * | 2021-01-06 | 2021-05-28 | 英韧科技(上海)有限公司 | Multilayer circuit board |
| US11706878B2 (en) | 2021-01-06 | 2023-07-18 | Innogrit Technologies Co., Ltd. | Multilayer circuit board |
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| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160420 |