CN105489241B - Static RAM - Google Patents
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- CN105489241B CN105489241B CN201410539431.5A CN201410539431A CN105489241B CN 105489241 B CN105489241 B CN 105489241B CN 201410539431 A CN201410539431 A CN 201410539431A CN 105489241 B CN105489241 B CN 105489241B
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Abstract
This application discloses a kind of Static RAM.Wherein, which includes：First bit line；The first transistor is connected to by source electrode and drain electrode between the first bit line and power supply or ground；N number of storage unit, for each in N number of storage unit for memory level state, level state includes high level and low level, and N is more than or equal to 1；N number of second transistor is corresponded with N number of storage unit, each in N number of second transistor is connected to by source electrode and drain electrode between corresponding storage unit and the grid of the first transistor；N number of first wordline is corresponded with N number of second transistor；Second bit line；Third transistor is connected to by source electrode and drain electrode between the second bit line and power supply or ground；N number of 4th transistor is corresponded with N number of storage unit；N number of second wordline is corresponded with N number of 4th transistor.Present application addresses Static RAM read data operation stability it is low the problem of.
Description
Technical Field
The application relates to the field of memories, in particular to a static random access memory.
Background
Static Random Access Memory (SRAM) can achieve fast read/write operations. Fig. 1 is a schematic diagram of a 6T sram according to the prior art, and each memory block of the 6T sram includes 6 transistors, i.e., a transistor PG-1, a transistor PG-2, a transistor PU-1, a transistor PD-1, a transistor PU-2, and a transistor PD-2, as shown in fig. 1. Transistor PU-1, transistor PD-1, transistor PU-2, transistor PD-2, power supply VDD, and ground VSS collectively form a memory cell for storing level states, i.e., a high state and a low state, the memory cell including two storage nodes, storage node Q and storage node QN, respectively, which store a pair of opposite level states. Word line WL is connected to the gates of transistors PG-1 and PG-2 for controlling the reading and writing of level states from and to the memory cells. Transistor PG-1 is coupled between a storage node Q of the memory cell and a bit line BL through a source and a drain, and transistor PG-2 is coupled between a storage node QN of the memory cell and a bit line BLB through a source and a drain.
When the word line WL is at a high level, the transistors PG-1 and PG-2 are simultaneously turned on, the bit line BL can read the level state of the storage node Q, and the bit line BLB can read the level state of the storage node QN, thereby reading data from the memory cell. Similarly, for example, writing a high level "1" to the memory cell, first, the bit line BL is added to a high level, the corresponding bit line BLB is added to a low level, when the word line WL is at a high level, the transistor PG-1 and the transistor PG-2 are simultaneously turned on, and the level states of the bit line BL and the bit line BLB are respectively transmitted to the storage node Q and the storage node QN, so that the storage node Q is at a high level state "1", and the corresponding storage node QN is at a low level state "0", thereby implementing writing data to the memory cell.
The 6T static random access memory can only realize single-port reading/writing, the reading and writing efficiency is low, the voltage of a storage node of the T static random access memory is influenced by reading operation, the static noise tolerance value is small, and the stability of the memory is too low.
Fig. 2 is a schematic diagram of a dual-port sram according to the prior art, and as shown in fig. 2, the dual-port sram is based on the 6T sram shown in fig. 1, and has added transistors PGA2 and PGB2, and bit lines BL2, BL1B and word line WLB, where transistor PGA2 is connected to bit line BL2 through a source or a drain, transistor PGB2 is connected to bit line BL1B through a source or a drain, and transistors PGA2 and PGB2 are connected to word line WLB through gates. The other elements in the figure correspond to those in FIG. 1, respectively, bit line BL1 corresponds to bit line BL, bit line BL2B corresponds to bit line BLB, transistor PGA1 corresponds to transistor PG-1, transistor PGB1 corresponds to transistor PG-2, and word line WLA corresponds to word line WL.
The dual-port static random access memory can realize simultaneous reading/writing from two ports, namely data can be written in from the two ports or data can be read out from the two ports, the reading and writing efficiency is improved, but the reading and writing operations of the two ports of the dual-port static random access memory can affect each other, and the stability of the dual-port static random access memory is lower than that of a traditional 6T static random access memory.
In order to improve the static noise margin and stability of the sram, 8T sram and 10T sram were manufactured, fig. 3 is a schematic diagram of an 8T sram according to the related art, and fig. 4 is a schematic diagram of a 10T sram according to the related art.
As shown in fig. 3, an 8T sram is formed by adding a transistor RPD and a transistor RPG to the 6T sram shown in fig. 1, a bit line RBL is connected to a storage node QN via the transistor RPD and the transistor RPG, a gate of the transistor RPG is connected to a word line RWL for controlling reading of data from the sram, the transistor PG-1 and the transistor PG-2 are connected to a word line WWL for controlling writing of data into the sram, and the rest of the 8T sram is the same as the 6T sram shown in fig. 1. Due to the existence of the transistor RPD and the transistor RPG, the voltage of the read port does not affect the voltage of the storage node QN, so that the stability of the static random access memory is improved, the static noise tolerance value is increased, but the 8T static random access memory can only execute single-port read operation, and the read efficiency is low.
As shown in fig. 4, the 10T sram is improved from the 8T sram by adding two transistors at symmetrical positions of the transistor RPD and the transistor RPG, and the two transistors are connected to the word line RWL and the bit line RBL, and the bit line RBLB corresponds to the bit line RBL in fig. 3. The rest of the 10T SRAM is the same as the 8T SRAM shown in FIG. 3. The 10T static random access memory can realize differential reading, improves the access speed of the memory and has higher stability, but each memory cell of the 10T static random access memory comprises 10 transistors, has larger area and is not beneficial to integrated manufacturing.
In summary, static memories (SRAMs) can achieve fast read/write operations, but Read Static Noise Margin (RSNM) becomes worse and less stable. The read static noise margin of a dual-port (2RW, 2 read-write ports) static memory is worse than that of a conventional 6T static memory, although the dual-port (2RW) static memory has a faster access speed. In order to realize high read static noise tolerance, 8T static memory and 10T static memory are invented, but the access speed and the unit area of the static memory are difficult to meet the requirements.
Aiming at the problem of low stability of data reading operation of the static random access memory in the prior art, an effective solution is not provided at present.
Disclosure of Invention
The embodiment of the application provides a static random access memory, which aims to solve the problem of low stability of data reading operation of the static random access memory.
According to an aspect of an embodiment of the present application, there is provided a static random access memory including: a first bit line; a first transistor connected between the first bit line and a power source or ground through a source and a drain; n memory cells, each of the N memory cells is used for storing a level state, the level state comprises a high level and a low level, and N is greater than or equal to 1; the N second transistors correspond to the N storage units one by one, and each of the N second transistors is connected between the corresponding storage unit and the grid electrode of the first transistor through a source electrode and a drain electrode; the N first word lines correspond to the N second transistors one by one, and each of the N first word lines is connected to the grid electrode of the corresponding second transistor and used for controlling the level state read out from the corresponding storage unit; a second bit line; a third transistor connected between the second bit line and a power source or ground through a source and a drain; the N fourth transistors are in one-to-one correspondence with the N storage units, wherein each of the N fourth transistors is connected between the corresponding storage unit and the grid electrode of the third transistor through a source electrode and a drain electrode; and N second word lines corresponding to the N fourth transistors one-to-one, each of the N second word lines being connected to a gate of the corresponding fourth transistor for controlling a level state read out from the corresponding memory cell.
Further, each of the N memory cells includes: a first storage node for storing a level state in phase with a level state of each memory cell; a second storage node for storing a level state inverted from the level state of each memory cell; wherein each of the N second transistors is connected between the first storage node in the corresponding memory cell and the gate of the first transistor through the source and the drain, or each of the N second transistors is connected between the second storage node in the corresponding memory cell and the gate of the first transistor through the source and the drain.
Further, each of the N memory cells includes: a first inverter connected between the first storage node and the second storage node; and a second inverter inversely connected between the first storage node and the second storage node with respect to the first inverter.
Further, each of the N memory cells includes: the first PMOS is connected between a power supply and a first storage node through a source electrode and a drain electrode, and the grid electrode of the first PMOS is connected to a second storage node; a first NMOS connected between the first storage node and ground through a source and a drain, a gate of the first NMOS being connected to the second storage node; a second PMOS connected between a power supply and a second storage node through a source and a drain, a gate of the second PMOS being connected to the first storage node; and a second NMOS connected between the second storage node and ground through a source and a drain, and having a gate connected to the first storage node.
Further, the static random access memory further comprises: a third bit line; the N fifth transistors correspond to the N storage units one by one, and each of the N fourth transistors is connected between the corresponding storage unit and the third bit line through a source electrode and a drain electrode; a fourth bit line; the N sixth transistors correspond to the N storage units one by one, and each of the N sixth transistors is connected between the corresponding storage unit and the fourth bit line through a source electrode and a drain electrode; and the N third word lines are in one-to-one correspondence with the N fifth transistors and the N sixth transistors, and each of the N third word lines is connected to the gates of the corresponding fifth transistors and the corresponding sixth transistors and is used for controlling the level state read out from the corresponding memory cells and/or controlling the level state written into the corresponding memory cells.
Further, the static random access memory further comprises: and the processor is connected with the first bit lines and the N first word lines and used for outputting control signals to any one of the N first word lines and reading the level state of the storage unit corresponding to any one of the N first word lines from the first bit lines, and the control signals are used for controlling the conduction between the source and the drain of the second transistor corresponding to any one of the N first word lines.
Further, the first transistor and the second transistor are NMOS.
According to the static random access memory, the first transistor and the second transistor are controlled through the first word line, so that the level state of the storage unit is kept unchanged when the static random access memory reads data, the purpose of improving the stability of the operation of reading the data of the static random access memory is achieved, and the technical problem of low stability of the operation of reading the data of the static random access memory is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic diagram of a 6T SRAM according to the prior art;
FIG. 2 is a schematic diagram of a dual port static random access memory according to the prior art;
FIG. 3 is a schematic diagram of an 8T SRAM according to the prior art;
FIG. 4 is a schematic diagram of a 10T SRAM according to the prior art;
FIG. 5 is a schematic diagram of a static random access memory according to an embodiment of the present application; and
FIG. 6 is a schematic diagram of a memory module according to an embodiment of the present application.
Detailed Description
The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
According to an embodiment of the present application, a static random access memory is provided, and fig. 5 is a schematic diagram of a static random access memory according to an embodiment of the present application.
As shown in fig. 5, the static random access memory includes: a first bit line 20, a first transistor 10, N memory cells, N second transistors, N first word lines, a second bit line 40, a third transistor 30, N fourth transistors, and N second word lines.
A first transistor 10 connected between a first bit line 20 and a power supply or ground through a source and a drain;
each of the N storage units is used for storing a level state, the level state comprises a high level and a low level, and N is greater than or equal to 1;
n second transistors corresponding to the N memory cells one to one, each of the N second transistors being connected between the corresponding memory cell and the gate of the first transistor 10 through a source and a drain;
and the N first word lines correspond to the N second transistors one by one, and each of the N first word lines is connected to the grid electrode of the corresponding second transistor and used for controlling the level state read out from the corresponding memory cell.
A third transistor 30 connected between the second bit line and a power source or ground through a source and a drain;
and the N fourth transistors are in one-to-one correspondence with the N storage units, wherein each of the N fourth transistors is connected between the corresponding storage unit and the grid electrode of the third transistor through a source electrode and a drain electrode.
And the N second word lines are in one-to-one correspondence with the N fourth transistors, and each of the N second word lines is connected to the grid electrode of the corresponding fourth transistor and used for controlling the level state read out from the corresponding memory cell.
As shown in fig. 5, the random access memory comprises N memory blocks, each memory block 50 of the N memory blocks comprises a memory cell 501, a second transistor 502, a first word line 507, a fourth transistor 504 and a second word line 508. The present embodiment will be described below by taking one memory module 50 of N memory cells as an example.
The source of the first transistor 10 is grounded, the gate of the first transistor 10 is connected to the source of the second transistor 502 via an internal connection ILB, the drain of the first transistor 10 is connected to a first bit line 20, the first bit line 20 is used as an output line, and is connected to an external circuit (not shown in the figure), and data stored in the memory is output through the first bit line 20 or data input from the outside is written into the memory. The drain of the second transistor 502 is connected to the first end of the memory cell 501, the gate is connected to the first word line 507, the second transistor 502 serves as a read operation transmission channel of the memory, when the first word line 507 is at a high level, the second transistor 502 is turned on, and the data stored in the memory cell 501 is transmitted to the first bit line 20 through the second transistor 502, so that the read operation of the memory data is realized. The source of third transistor 30 is connected to ground, the drain of third transistor 30 is connected to second bit line 40, and the gate of third transistor 30 is connected to the source of fourth transistor 504 via internal connection ILA. The gate of the fourth transistor 504 is connected to the second word line 508, and the drain of the fourth transistor 504 is connected to the second terminal of the memory cell 501.
In reading data of the sram, when the first word line 507 is at a high level, the second transistor 502 is turned on, and the level state of the memory cell 501 can be read from the first bit line 20, and since the gate and the source of the first transistor 10 are in an off state, no current flows through the gate of the first transistor 10, and thus the level state of the memory cell 501 can be maintained by the read operation performed by the second transistor 502 and the first transistor 10. Similarly, when the second word line 508 is at a high level, the fourth transistor 504 is turned on, and the level state stored in the memory cell can be read through the second bit line 40, while the gate of the third transistor 30 is turned off, so that the voltage value at the second end of the memory cell 501 of the sram is not affected by the operation of reading the memory. The static memory reads data from the static memory by using the first bit line 20, the first transistor 10 and the second transistor 502 as a first read port and using the third transistor 30, the fourth transistor 504 and the second bit line 40 as a second read port, so that the two read ports can simultaneously execute data reading operation, the efficiency of reading data from the memory is improved, the voltage values at two ends of a storage unit can be kept unchanged in the data reading process, the stability of reading data from the static random memory is improved, the problem of low stability of the data reading operation of the static random memory is solved, and in addition, the static random memory has a simple structure and a small area and is convenient for integrated manufacturing.
Optionally, each of the N memory cells 501 includes: a first storage node 5013 and a second storage node 5014.
The first storage node 5013 stores a level state that is in phase with the level state of each of the memory cells 501.
A second storage node 5014 for storing a level state inverted to the level state of each of the memory cells 501; each of the N second transistors 502 is connected between the first storage node 5013 of the corresponding memory cell 501 and the gate of the first transistor 10 via a source and a drain.
As can be seen in fig. 5, the second transistor 502 is connected to the memory cell by a drain connection to the second storage node 5014. The memory cell 501 stores the same level state as the memory cell 501 through the first storage node 5013, and the second storage node 5014 stores a level state opposite to the memory cell 501, for example, when the level state stored in the memory cell 501 is "1", the level state stored in the first storage node 5013 is "1", and the level state stored in the second storage node 5014 is "0".
Preferably, for the convenience of implementing the level states of the first storage node 5013 and the second storage node 5014 of the memory cell 501 as opposite level states, each memory cell 501 of the N memory cells includes: a first inverter 5011 and a second inverter 5012.
The first inverter 5011 is connected between the first storage node 5013 and the second storage node 5014.
The second inverter 5012 is connected between the first storage node 5013 and the second storage node 5014 in an inverted orientation relative to the first inverter 5011.
A first terminal of the first inverter 5011 is connected to the first storage node 5013 and a second terminal of the first inverter 5011 is connected to the second storage node 5014. While a first terminal of the second inverter 5012 is connected to the second storage node 5014 and a second terminal of the second inverter 5012 is connected to the first storage node 5013, enabling an inverting connection of the first inverter 5011 with the second inverter 5012. The inverter is used to invert the input level state, for example, a level state "1" gets a level state "0" via the inverter. Two opposite level states can be conveniently obtained through the inverter, and the inversion of the level states of the first storage node 5013 and the second storage node 5014 is realized.
The specific structure of the memory module in fig. 5 is shown in fig. 6, and as shown in fig. 6, the memory module includes a memory cell 501, and preferably, in order to reduce the power consumption of the sram, each memory cell 501 in the N memory cells includes: a first PMOS transistor PU-1, a first NMOS transistor PD-1, a second PMOS transistor PU-2 and a second NMOS transistor PD-2.
The first PMOS transistor PU-1 is connected between a power supply VDD and a first storage node Q through a source and a drain, and a gate of the first PMOS transistor PU-1 is connected to a second storage node QN.
The first NMOS transistor PD-1 is connected between the first storage node Q and the ground VSS through a source and a drain, and a gate of the first NMOS transistor PD-1 is connected to the second storage node QN.
A second PMOS transistor PU-2 connected between a power supply VDD and the second storage node QN through a source and a drain, a gate of the second PMOS transistor PU-2 being connected to the first storage node Q;
a second NMOS transistor PD-2 connected between the second storage node QN and ground VSS through a source and a drain, and a gate of the second NMOS transistor PD-2 is connected to the first storage node Q.
As shown in fig. 6, the storage unit 501 includes: a first PMOS transistor PU-1, a first NMOS transistor PD-1, a second PMOS transistor PU-2, a second NMOS transistor PD-2, a power supply VDD and a ground VSS. The gates of the first PMOS transistor PU-1 and the first NMOS transistor PD-1 are commonly connected to the second storage node QN, the drain of the first PMOS transistor PU-1 is connected to the power supply VDD, the source of the first PMOS transistor PU-1 is connected to the first storage node Q, the drain of the first NMOS transistor PD-1 is connected to the first storage node Q, and the source of the first NMOS transistor PD-1 is connected to the ground VSS. Similarly, the gates of the second PMOS transistor PU-2 and the second NMOS transistor PD-2 are connected to the first storage node Q, the drain of the second PMOS transistor PU-2 is connected to the power supply VDD, the source of the second PMOS transistor PU-2 and the drain of the second NMOS transistor PD-2 are connected to the second storage node QN, and the source of the second NMOS transistor PD-2 is connected to the ground VSS.
A CMOS inverter is formed by interconnecting the first PMOS transistor PU-1, the first NMOS transistor PD-1, the power supply VDD and the ground VSS, so that the level state of the first storage node Q is inverted to obtain the level state of the second storage node QN. Similarly, the second PMOS transistor PU-2, the second NMOS transistor PD-2, the power source VDD, and the ground VSS are connected to each other to form a CMOS inverter, so that the level state of the second storage node QN is inverted to obtain the level state of the first storage node Q. The CMOS phase inverter has low static power consumption and strong anti-interference capability, and the power consumption and the anti-interference capability of the whole static random access memory can be reduced by adopting the CMOS phase inverter as the storage unit.
Preferably, in order to further improve the efficiency of the data writing operation into the static random access memory, the static random access memory further comprises: a third bitline 509, N fifth transistors and, a fourth bitline 510 and N third wordlines.
N fifth transistors corresponding to the N memory cells one to one, each of the N fifth transistors being connected between the corresponding memory cell and the third bit line 509 through a source and a drain;
n sixth transistors corresponding to the N memory cells one to one, each of the N sixth transistors being connected between the corresponding memory cell and the fourth bit line 510 through a source and a drain;
and the N third word lines are in one-to-one correspondence with the N fifth transistors and the N sixth transistors, and each of the N third word lines is connected to the gates of the corresponding fifth transistors and the corresponding sixth transistors and is used for controlling the level state read out from the corresponding memory cells and/or controlling the level state written into the corresponding memory cells.
As shown in fig. 5, the gate of the fifth transistor 505 is connected to the third word line 511, the fifth transistor 505 is connected to the third bit line 509 by the source, and the drain of the fifth transistor 505 is connected to the first storage node 5013. The third word line 511 is used to control writing of data to the memory cell 501. When the third word line 511 is at a high level, the fifth transistor 505 is turned on to form a single transmission path, and a level state can be written into the memory cell 501 through the third bit line 509. By adding the fifth transistor 505 and the third bit line 509 as a write port in the static random access memory, data can be written into the static random access memory through the write port, and the efficiency of writing data into the static random access memory is improved.
The gate of the fifth transistor 505 is connected to the third wordline 511, the fifth transistor 505 is connected to the third bitline 509 by its source, and the drain of the fifth transistor 505 is connected to the first storage node 5013 of the memory cell 501. The gate of the sixth transistor 506 is also connected to the third word line 511, the sixth transistor 506 is connected to the fourth bit line 510 through the source, and the drain of the sixth transistor 506 is connected to the second terminal of the memory cell 501. The third word line 511 controls on and off of the fifth transistor 505 and the sixth transistor 506 at the same time to control whether to read data stored in the memory cell 501 or write data to the memory cell 501. During a data reading operation of the memory, for example, a "1" stored in the memory cell 501 is read, a level of a first terminal of the memory cell 501 is "0", a level of a second terminal of the memory cell 501 is "1", the third bit line 509 and the fourth bit line 510 are charged to "1", the third word line 511 is at a high level, the fifth transistor 505 and the sixth transistor 506 are simultaneously turned on, a current flows through the fifth transistor 505 and the sixth transistor 506, a level of the third bit line 509 is pulled down, a voltage difference is generated between the third bit line 509 and the fourth bit line 510, and when a predetermined value is reached, a sense amplifier (not shown in the figure) is turned on to amplify the voltage difference, thereby reading data. In the process of writing data into the memory, data to be written is loaded on the third bit line 509 and the fourth bit line 510, for example, data "1" is written into the memory cell 501, the third bit line 509 is loaded with data "0", the fourth bit line 510 is loaded with data "1", when the third word line 511 is at a high level, the fifth transistor 505 and the sixth transistor 506 are simultaneously turned on, at this time, "0" loaded by the third bit line 509 is transmitted to the first end of the memory cell 501, and data "1" loaded by the second bit line 307 is transmitted to the second end of the memory cell 501, so that data is written into the memory cell 501.
The third word line 511 controls the fifth transistor 505 and the sixth transistor 506 to realize reading a level state from a memory cell and/or writing a level state into a corresponding memory cell, and the fifth transistor 505, the sixth transistor 506, the third bit line 509 and the fourth bit line 510 are added to the static random access memory as a memory read/write port to realize reading data from the static random access memory or writing data into the static random access memory, thereby improving the read/write speed of the static random access memory.
Optionally, the static random access memory further comprises: and a processor connected to the first bit line 20 and the N first word lines, for outputting a control signal to any one of the N first word lines 5, and reading a level state of a memory cell corresponding to any one of the N first word lines from the first bit line 20, the control signal being used to control conduction between a source and a drain of the second transistor corresponding to any one of the N first word lines.
Preferably, the first transistor 10 and the second transistor 502 are NMOS.
The power consumption of the CMOS transistor is lower than that of the TTL transistor, and the CMOS transistor has stronger interference resistance. The CMOS transistor comprises an NMOS transistor and a PMOS transistor, wherein the NMOS transistor is conducted only when the voltage difference between the grid electrode and the source electrode is larger than a certain value, and is suitable for the condition that the source electrode is grounded, and the PMOS transistor is conducted only when the voltage difference between the grid electrode and the source electrode is smaller than a certain value, and is suitable for the source electrode to be connected with a power supply. In addition, the on-resistance of the NMOS transistor is smaller than that of the PMOS transistor, so that the on-loss of the NMOS transistor is correspondingly lower than that of the PMOS transistor, and the loss of the static random access memory can be reduced by adopting the NMOS transistor.
This application provides a preferred embodiment to further explain this application, but it should be noted that this preferred embodiment is only for better describing this application and should not be construed as unduly limiting this application.
From the above description, it can be seen that the following technical effects are achieved by the present application:
1) the gate of the first transistor is connected to the source of the second transistor through the internal connection ILB, so that the voltage of the second storage node of the memory cell can be kept unchanged when data is read from the static random access memory, and the gate of the third transistor is connected to the source of the fourth transistor through the internal connection ILA, so that the voltage of the first storage node of the memory cell can be kept unchanged when data is read from the static random access memory, thereby improving the stability of data reading from the static random access memory and solving the problem of low stability of data reading from the static random access memory. And the static random access memory has fewer transistors and smaller area, and is convenient for integrated manufacturing.
2) The static random access memory can execute 2 ports to read data and 1 port to write data simultaneously, or execute 3 ports to read data simultaneously, and the data reading efficiency of the static random access memory is greatly improved.
3) The transistor of the static random access memory is composed of MOS transistors, so that the power consumption is low, and the power consumption of the static random access memory is reduced.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (7)
1. A static random access memory, comprising:
a first bit line;
a first transistor connected between the first bit line and a power source or ground through a source and a drain;
n memory cells, each of the N memory cells is used for storing a level state, the level state comprises a high level and a low level, and N is larger than or equal to 1;
n second transistors corresponding to the N memory cells one to one, each of the N second transistors being connected between the corresponding memory cell and a gate of the first transistor through a source and a drain;
the N first word lines correspond to the N second transistors one by one, and each of the N first word lines is connected to the grid electrode of the corresponding second transistor and used for controlling the level state read out from the corresponding storage unit;
a second bit line;
a third transistor connected between the second bit line and a power source or ground through a source and a drain;
n fourth transistors in one-to-one correspondence with the N memory cells, wherein each of the N fourth transistors is connected between the corresponding memory cell and the gate of the third transistor through a source and a drain; and
and the N second word lines correspond to the N fourth transistors one by one, and each of the N second word lines is connected to the grid electrode of the corresponding fourth transistor and used for controlling the level state read out from the corresponding storage unit.
2. The SRAM of claim 1 wherein each of the N memory cells comprises:
a first storage node for storing a level state in phase with a level state of each of the memory cells;
a second storage node for storing a level state inverted from the level state of each of the memory cells; wherein,
each of the N second transistors is connected between the first storage node in the corresponding memory cell and the gate of the first transistor through a source and a drain, or each of the N second transistors is connected between the second storage node in the corresponding memory cell and the gate of the first transistor through a source and a drain.
3. The SRAM of claim 2 wherein each of the N memory cells comprises:
a first inverter connected between the first storage node and the second storage node;
a second inverter connected between the first storage node and the second storage node in an inverted manner with respect to the first inverter.
4. The SRAM of claim 2 wherein each of the N memory cells comprises:
a first PMOS connected between a power supply and the first storage node through a source and a drain, a gate of the first PMOS being connected to the second storage node;
a first NMOS connected between the first storage node and ground through a source and a drain, a gate of the first NMOS being connected to the second storage node;
a second PMOS connected between a power supply and the second storage node through a source and a drain, a gate of the second PMOS being connected to the first storage node;
and the second NMOS is connected between the second storage node and the ground through a source electrode and a drain electrode, and the grid electrode of the second NMOS is connected to the first storage node.
5. The static random access memory of claim 1, further comprising:
a third bit line;
n fifth transistors corresponding to the N memory cells one to one, each of the N fourth transistors being connected between the corresponding memory cell and the third bit line through a source and a drain;
a fourth bit line;
n sixth transistors corresponding to the N memory cells one to one, each of the N sixth transistors being connected between the corresponding memory cell and the fourth bit line through a source and a drain;
and each of the N third word lines is connected to the grid electrodes of the corresponding fifth transistor and the corresponding sixth transistor and is used for controlling the level state read out from the corresponding storage unit and/or controlling the level state written into the corresponding storage unit.
6. The static random access memory according to any of claims 1 to 5, further comprising:
and the processor is connected with the first bit line and the N first word lines and is used for outputting a control signal to any one of the N first word lines and reading the level state of the storage unit corresponding to the any one of the N first word lines from the first bit line, wherein the control signal is used for controlling the conduction between the source and the drain of the second transistor corresponding to the any one of the N first word lines.
7. The static random access memory according to any of claims 1 to 5, wherein the first transistor and the second transistor are NMOS.
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| CN113096702B (en) * | 2020-01-09 | 2024-05-14 | 中芯国际集成电路制造(上海)有限公司 | Memory circuit, reading method and recovery method thereof |
| CN116230053B (en) * | 2023-03-01 | 2023-12-22 | 芯立嘉集成电路(杭州)有限公司 | Four-transistor static random access memory and access method |
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| CN1808621A (en) * | 2004-12-30 | 2006-07-26 | 国际商业机器公司 | Memory cell having improved read stability, memory array and integrate circuit |
| CN102047339A (en) * | 2008-06-19 | 2011-05-04 | 德克萨斯仪器股份有限公司 | Memory cell employing reduced voltage |
| CN102157195A (en) * | 2011-05-05 | 2011-08-17 | 北京大学 | Low-voltage static random access memory unit, memory and writing operation method |
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| CN1808621A (en) * | 2004-12-30 | 2006-07-26 | 国际商业机器公司 | Memory cell having improved read stability, memory array and integrate circuit |
| CN102047339A (en) * | 2008-06-19 | 2011-05-04 | 德克萨斯仪器股份有限公司 | Memory cell employing reduced voltage |
| CN102157195A (en) * | 2011-05-05 | 2011-08-17 | 北京大学 | Low-voltage static random access memory unit, memory and writing operation method |
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