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CN105470293B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN105470293B
CN105470293B CN201410430805.XA CN201410430805A CN105470293B CN 105470293 B CN105470293 B CN 105470293B CN 201410430805 A CN201410430805 A CN 201410430805A CN 105470293 B CN105470293 B CN 105470293B
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layer
patterned
interlayer dielectric
hard mask
metal
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CN105470293A (zh
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林静龄
黄志森
洪庆文
吴家荣
张宗宏
李怡慧
陈意维
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US15/257,921 priority patent/US9899322B2/en
Priority to US15/863,986 priority patent/US9984974B1/en
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Abstract

本发明公开一种半导体元件及其制作方法，该半导体元件包含一基底、一第一金属栅极设于基底上、一第一硬掩模设于第一金属栅极上、一层间介电层设于第一金属栅极上并环绕该第一金属栅极以及一图案化的金属层镶嵌于层间介电层中，其中图案化的金属层的上表面低于第一硬掩模的上表面。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种半导体元件，尤其是涉及一种于层间介电层中镶嵌高阻值金属层的半导体元件。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而，在现有的鳍状场效晶体管元件制作工艺中，结合金属栅极与薄膜电阻的制作仍遇到一些瓶颈，例如形成接触插塞时常因薄膜电阻所设置的位置不佳而直接贯穿薄膜电阻，影响电阻的整体电性表现。因此如何改良现有鳍状场效晶体管制作工艺与架构即为现今一重要课题。
发明内容
为解决上述问题，本发明优选实施例是公开一种制作半导体元件的方法。首先提供一基底，该基底包含一第一金属栅极与一第二金属栅极设于其上，一第一硬掩模设于第一金属栅极上与一第二硬掩模设于第二金属栅极上，以及一第一层间介电层环绕第一金属栅极与第二金属栅极。接着利用第一硬掩模及第二硬掩模去除部分第一层间介电层以形成一凹槽，然后再形成一图案化的金属层于凹槽内，其中图案化的金属层的上表面低于第一硬掩模及第二硬掩模的上表面。
本发明另一实施例是公开一种半导体元件，包含一基底、一第一金属栅极设于基底上、一第一硬掩模设于第一金属栅极上、一层间介电层设于第一金属栅极上并环绕该第一金属栅极以及一图案化的金属层镶嵌于层间介电层中，其中图案化的金属层的上表面低于第一硬掩模的上表面。
附图说明
图1至图6为本发明优选实施例制作一半导体元件的方法示意图；
图7为本发明另一实施例的一半导体元件的结构示意图。
主要元件符号说明
12 基底 14 鳍状结构
16 绝缘层 18 金属栅极
20 金属栅极 22 金属栅极
24 间隙壁 26 源极/漏极区域
28 外延层 30 接触洞蚀刻停止层
32 层间介电层 34 功函数金属层
36 低阻抗金属层 38 硬掩模
40 凹槽 42 高阻值金属层
44 介电堆叠层 46 氮化硅层
48 二氧化硅层 50 层间介电层
52 接触插塞 54 接触插塞
56 接触插塞 58 氧化层
具体实施方式
请参照图1至图6，图1至图6为本发明优选实施例制作一半导体元件的方法示意图，其可实施于平面型或非平面型晶体管元件制作工艺，现以应用于非平面型晶体管元件制作工艺为例。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，其上定义有一晶体管区，例如一PMOS晶体管区或一NMOS晶体管区。基底12上具有至少一鳍状结构14及一绝缘层16，其中鳍状结构14的底部被绝缘层16，例如氧化硅所包覆而形成浅沟隔离，且部分的鳍状结构14上还分别设有多个金属栅极18、20、22。
鳍状结构14的形成方式可以包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中。接着，对应三栅极晶体管元件及双栅极鳍状晶体管元件结构特性的不同，而可选择性去除或留下图案化掩模，并利用沉积、化学机械研磨(chemical mechanical polishing,CMP)及回蚀刻制作工艺而形成一环绕鳍状结构14底部的绝缘层16。除此之外，鳍状结构14的形成方式另也可以是先制作一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出半导体层，此半导体层即可作为相对应的鳍状结构14。同样的，还可以选择性去除或留下图案化硬掩模层，并通过沉积、CMP及回蚀刻制作工艺形成一绝缘层16以包覆住鳍状结构14的底部。另外，当基底12为硅覆绝缘(SOI)基板时，则可利用图案化掩模来蚀刻基底上的一半导体层，并停止于此半导体层下方的一底氧化层以形成鳍状结构，故可省略前述制作绝缘层16的步骤。
金属栅极18、20、22的制作方式可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先栅极介电层(high-k first)制作工艺以及后栅极制作工艺的后栅极介电层(high-k last)制作工艺等方式制作完成。以本实施例的先栅极介电层制作工艺为例，可先于鳍状结构14与绝缘层16上形成一优选包含高介电常数介电层与多晶硅材料所构成的虚置栅极(图未示)，然后于虚置栅极侧壁形成间隙壁24。接着于间隙壁24两侧的鳍状结构14以及/或基底12中形成一源极/漏极区域26与外延层28、形成一接触洞蚀刻停止层30覆盖虚置栅极，并形成一由四乙氧基硅烷(Tetraethyl orthosilicate,TEOS)所组成的层间介电层32于接触洞蚀刻停止层30上。
之后可进行一金属栅极置换(replacement metal gate)制作工艺，先平坦化部分的层间介电层32及接触洞蚀刻停止层30，并再将虚置栅极转换为一金属栅极。金属栅极置换制作工艺可包括先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammoniumhydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除虚置栅极中的多晶硅材料以于层间介电层32中形成一凹槽。之后形成一至少包含U型功函数金属层34与低阻抗金属层36的导电层于该凹槽内，并再搭配进行一平坦化制作工艺使U型功函数金属层34与低阻抗金属层36的表面与层间介电层32表面齐平。
在本实施例中，功函数金属层34优选用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层34可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层34可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层34与低阻抗金属层36之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层36则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极是此领域者所熟知技术，在此不另加赘述。
随后可先去除层间介电层32上部分的功函数金属层34与低阻抗金属层36形成金属栅极18、20、22，然后回蚀刻凹槽内部分的金属栅极18、20、22，再填入一硬掩模38于金属栅极18、20、22上并平坦化之。其中硬掩模38可为单一材料层或复合材料层，例如一包含氧化硅与氮化硅的复合层，且硬掩模38的上表面优选与层间介电层32的上表面齐平。
接着如图2所示，先利用层间介电层32的蚀刻选择比与硬掩模38、间隙壁24、接触洞蚀刻停止层30都不同的特性，去除金属栅极18、20、22间的部分层间介电层32以形成一凹槽40，然后可选择性沉积一氧化层58于硬掩模38及层间介电层32上，用来当作一蚀刻停止层，再依序形成一高阻值金属层42与一介电堆叠层44于氧化层58上。依据本发明的优选实施例，高阻值金属层42包含氮化钛，介电堆叠层44用来当作一掩模层，其可包含一氮化硅层46及一二氧化硅层48，但不局限于此。另外在本实施例中，凹槽40的深度虽低于硬掩模38的上表面(原层间介电层32表面)且略高于硬掩模38的底部，但并不局限于此，本发明可依据制作工艺需求调整凹槽40的深度，例如使其深度低于硬掩模38的上表面(原层间介电层32表面)且又同时齐平或低于硬掩模38底部，此变化型也属本发明所涵盖的范围。
如图3所示，然后图案化介电堆叠层44与高阻值金属层42以形成一图案化的介电堆叠层44与一图案化的高阻值金属层42于凹槽40内。依据本发明的一实施例，图案化介电堆叠层44与高阻值金属层42的步骤可先形成一图案化光致抗蚀剂层(图未示)于介电堆叠层44上，然后以该图案化光致抗蚀剂层为掩模进行一干蚀刻制作工艺去除部分介电堆叠层44以形成图案化的介电堆叠层44于凹槽40内的层间介电层32上。接着如图4所示，可选择性去除该图案化光致抗蚀剂层以图案化的介电堆叠层44为蚀刻掩模，或再以该图案化光致抗蚀剂层进行一湿蚀刻制作工艺去除部分高阻值金属层42形成图案化的高阻值金属层42，使图案化的介电堆叠层44与图案化的高阻值金属层42同时设于凹槽40内的层间介电层32上，且图案化的介电堆叠层44与图案化的高阻值金属层42的上表面均低于硬掩模38的上表面。
随后如图5所示，形成另一层间介电层50于氧化层58、硬掩模38、层间介电层32、图案化的介电堆叠层44及图案化的高阻值金属层42上。在本实施例中，层间介电层50的材料优选采用与层间介电层32相同的材料，例如均由四乙氧基硅烷(TEOS)所组成。
接着如图6所示，先形成一接触插塞52于层间介电层50与层间介电层32中以电连接邻近于金属栅极18的源极/漏极区域26与外延层28，然后再形成接触插塞54于层间介电层50中以电连接图案化的高阻值金属层42以及接触插塞56于层间介电层50中以电连接金属栅极22。形成接触插塞52、54、56的方法可先于层间介电层32、50中形成多个接触洞(图未示)，之后可选择性于接触洞底部曝露的源极/漏极区域26与外延层28表面形成金属硅化物，然后依序形成一阻障/黏着层(图未示)、一晶种层(图未示)以及一导电层(图未示)覆盖并填入接触洞，其中阻障/黏着层共形地(conformally)填入接触洞中而导电层则完全填满接触洞。阻障/黏着层的材料例如是钽(Ta)、钛(Ti)、氮化钛(TiN)、钽化钛(TaN)、氮化钨(WN)或是其任意组合例如钛/氮化钛所构成，但并不以此为限。晶种层的材料优选与导电层的材料相同，导电层的材料包含各种低电阻金属材料，例如是铝(Al)、钛(Ti)、钽(Ta)、钨(W)、铌(Nb)、钼(Mo)、铜(Cu)等材料，优选是钨或铜，最佳是钨。最后进行一平坦化制作工艺例如化学机械研磨(CMP)制作工艺、蚀刻制作工艺或是两者的结合，去除部分阻障/黏着层、晶种层与导电层，使剩余的导电层上表面与层间介电层上表面齐平以形成接触插塞52、54、56，至此完成本发明优选实施例的半导体元件的制作。
值得注意的是，在层间介电层32、50中形成多个接触洞(图未示)以形成接触插塞52、54、56的方法可以整合双重曝光(Double Patterning)等技术实施之。亦即，电连接源极/漏极区域26的接触插塞52、电连接图案化的高阻值金属层42的接触插塞54、电连接金属栅极22的接触插塞56，此三种接触插塞可依蚀刻深度、图案密度、深宽比(aspect ratio)等制作工艺条件相互搭配实施。例如，以考虑相同的蚀刻深度为例，调整凹槽40的深度，使其深度齐平或略低于硬掩模38底部，即可同时于层间介电层50中蚀刻出接触插塞54、56的接触洞(图未示)，而不蚀穿高阻值金属层42；反之，调整凹槽40的深度，使其深度远低于硬掩模38底部或略齐平于外延层28，即可同时蚀刻出接触插塞52、54的接触洞(图未示)。
如图6所示，本发明还公开一种半导体元件结构，其主要包含一基底12、多个金属栅极18、20、22设于基底上12、多个硬掩模38分别设于金属栅极18、20、22上、一层间介电层包括层间介电层32及层间介电层50设于金属栅极18、20、22上并环绕各金属栅极18、20、22以及一图案化的高阻值金属层42镶嵌于层间介电层32、50中。图案化的高阻值金属层42上另设有一图案化的介电堆叠层44，其中图案化的介电堆叠层44包含氮化硅及二氧化硅，图案化的高阻值金属层42包含氮化钛，但不局限于此。在本实施例中，图案化的高阻值金属层42的上表面优选低于该各硬掩模38的上表面，且设于其上的图案化的介电堆叠层44的上表面也同样低于各硬掩模38的上表面。但不局限于此深度，高阻值金属层42与介电堆叠层44所设置的位置又可依据前述制作工艺中形成凹槽40时调整，例如可使两者的上表面均低于硬掩模38的下表面，此变化型也属本发明所涵盖的范围。
此外，半导体元件结构又包含多个接触插塞52、54、56分别电连接金属栅极与高阻值金属层42，其中接触插塞52设于层间介电层32、50中并电连接邻近于金属栅极18的源极/漏极区域26，接触插塞54设于层间介电层32、50中并电连接图案化的高阻值金属层42以及接触插塞56设于层间介电层50中并电连接金属栅极22。另外本实施例虽于图案化的高阻值金属层42正下方设置一如绝缘层16所构成的浅沟隔离，但绝缘层16所设置的位置并不局限于此，又可视制成需求调整绝缘层16的位置，例如不于图案化的高阻值金属层42正下方设置任何绝缘层16，此变化型也属本发明所涵盖的范围。
然而，不局限于上述图3-图4的实施例，依据本发明的另一实施例，如图7所示，图案化介电堆叠层44与高阻值金属层42的步骤又可同样先形成一宽度略大于上述实施例的图案化光致抗蚀剂层(图未示)于介电堆叠层44上，然后以该图案化光致抗蚀剂层为掩模进行一干蚀刻制作工艺去除部分介电堆叠层44以形成图案化的介电堆叠层44于凹槽40内的层间介电层32以及至少一侧的接触洞蚀刻停止层30、间隙壁24或部分的硬掩模38上。接着可选择性去除该图案化光致抗蚀剂层或再次以该图案化光致抗蚀剂层为掩模进行一湿蚀刻制作工艺去除部分高阻值金属层42，使图案化的介电堆叠层44与图案化的高阻值金属层42同时设于层间介电层32及两侧的接触洞蚀刻停止层30、间隙壁24或部分硬掩模38上。之后可比照图5-图6的制作工艺形成另一层间介电层50于氧化层58、硬掩模38、层间介电层32、图案化的介电堆叠层44及图案化的高阻值金属层42上，然后形成多个接触插塞52、54、56分别连接源极/漏极区域26与外延层28、图案化的高阻值金属层42及金属栅极22。以结构来看，图案化的高阻值金属层42优选镶嵌于层间介电层32、50中，且图案化的高阻值金属层42包含一阶梯部设于接触洞蚀刻停止层30、间隙壁24或部分的硬掩模38上。
综上所述，本发明优选于金属栅极上形成硬掩模后先利用硬掩模为蚀刻掩模去除部分的层间介电层，以于金属栅极之间形成一凹槽，然后于凹槽中形成一由高阻值金属层所构成的薄膜电阻。由于一部分的层间介电层已先被去除，因此所形成的高阻值金属层将低于旁边的硬掩模，例如其上表面将优选低于硬掩模的上表面，而此高低差便可避免后续制作接触插塞时使接触插塞直接贯穿高阻值金属层而影响到薄膜电阻的电性表现。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种制作半导体元件的方法，包含：
提供一基底，该基底包含第一金属栅极与第二金属栅极设于其上，一第一硬掩模设于该第一金属栅极上与一第二硬掩模设于该第二金属栅极上，以及一第一层间介电层环绕该第一金属栅极与该第二金属栅极；
利用该第一硬掩模及该第二硬掩模去除部分该第一层间介电层以形成一凹槽；以及
形成一图案化的高阻值金属层于该凹槽内，其中该图案化的高阻值金属层的上表面低于该第一硬掩模及该第二硬掩模的上表面，该第一层间介电层位于该图案化的高阻值金属层之下。
2.如权利要求1所述的方法，还包含：
形成一金属层于该第一硬掩模、该第二硬掩模以及该第一层间介电层上；
形成一介电堆叠层于该金属层上；
图案化该介电堆叠层与该金属层以形成一图案化的介电堆叠层及该图案化的高阻值金属层于该凹槽内；
形成一第二层间介电层于该第一硬掩模、该第二硬掩模、该第一层间介电层、该图案化的介电堆叠层及该图案化的高阻值金属层上；
形成一第一接触插塞于该第二层间介电层与该第一层间介电层中以电连接邻近于该第一金属栅极的一源极/漏极区域；
形成一第二接触插塞于该第二层间介电层中以电连接该图案化的高阻值金属层以及形成一第三接触插塞于该第二层间介电层中以电连接该第二金属栅极。
3.如权利要求2所述的方法，其中图案化该介电堆叠层与该金属层的步骤还包含：
进行一第一蚀刻制作工艺去除部分该介电堆叠层以形成该图案化的介电堆叠层于该凹槽内及该第一层间介电层上；以及
进行一第二蚀刻制作工艺去除部分该金属层。
4.如权利要求2所述的方法，其中图案化该介电堆叠层与该金属层的步骤还包含：
进行一第一蚀刻制作工艺去除部分该介电堆叠层以形成该图案化的介电堆叠层于该第一层间介电层、该第一硬掩模及该第二硬掩模上；以及
进行一第二蚀刻制作工艺去除部分该金属层。
5.如权利要求2所述的方法，其中该介电堆叠层包含氮化硅及二氧化硅。
6.如权利要求1所述的方法，其中该图案化的高阻值金属层包含氮化钛。
7.一种半导体元件，包含：
基底；
第一金属栅极，设于该基底上；
第一硬掩模，设于该第一金属栅极上；
层间介电层，设于该第一金属栅极上并环绕该第一金属栅极；以及
图案化的高阻值金属层，镶嵌于该层间介电层中，其中该图案化的高阻值金属层的上表面低于该第一硬掩模的上表面，该层间介电层位于该图案化的高阻值金属层之下。
8.如权利要求7所述的半导体元件，还包含图案化的介电堆叠层，设于该图案化的高阻值金属层上。
9.如权利要求8所述的半导体元件，其中该图案化的介电堆叠层包含氮化硅及二氧化硅。
10.如权利要求8所述的半导体元件，其中该图案化的介电堆叠层的上表面低于该第一硬掩模的上表面。
11.如权利要求7所述的半导体元件，其中该图案化的高阻值金属层包含氮化钛。
12.如权利要求7所述的半导体元件，还包含第一接触插塞，设于该层间介电层中并电连接邻近该第一金属栅极的一源极/漏极区域。
13.如权利要求7所述的半导体元件，还包含第二接触插塞，设于该层间介电层中并电连接该图案化的高阻值金属层。
14.如权利要求7所述的半导体元件，还包含：
第二金属栅极，设于该基底上并邻近该第一金属栅极；以及
第二硬掩模，设于该第二金属栅极上。
15.如权利要求14所述的半导体元件，还包含第三接触插塞，设于该层间介电层中并电连接该第二金属栅极。
16.如权利要求7所述的半导体元件，还包含浅沟隔离，设于该基底中以及该图案化的高阻值金属层正下方。
17.一种半导体元件，包含：
基底；
金属栅极，设于该基底上；
硬掩模，设于该金属栅极上；
层间介电层，环绕该金属栅极；以及
图案化的高阻值金属层，镶嵌于该层间介电层中，其中该图案化的高阻值金属层包含阶梯部，该层间介电层位于该图案化的高阻值金属层之下。
18.如权利要求17所述的半导体元件，还包含图案化的介电堆叠层，设于该图案化的高阻值金属层上，且该图案化的介电堆叠层包含氮化硅及二氧化硅。
19.如权利要求17所述的半导体元件，其中该阶梯部设于部分该硬掩模上。
20.如权利要求17所述的半导体元件，其中该图案化的高阻值金属层包含氮化钛。
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