CN105470253A - FinFET structure and manufacturing method thereof - Google Patents
FinFET structure and manufacturing method thereof Download PDFInfo
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- CN105470253A CN105470253A CN201410459357.6A CN201410459357A CN105470253A CN 105470253 A CN105470253 A CN 105470253A CN 201410459357 A CN201410459357 A CN 201410459357A CN 105470253 A CN105470253 A CN 105470253A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000000463 material Substances 0.000 claims description 36
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 8
- 230000008569 process Effects 0.000 abstract description 7
- 238000005516 engineering process Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000001105 regulatory effect Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000011065 in-situ storage Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 229910021478 group 5 element Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910004143 HfON Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a FinFET structure and a manufacturing method thereof, comprising the following steps: a substrate; the first fin and the second fin are positioned above the substrate and are parallel to each other; the grid laminated layer covers the substrate and the side walls of partial first fins and partial second fins; a source region in a region of the first fin not covered by the gate stack; a drain region located in a region of the second fin not covered by the gate stack; the side walls are positioned on two sides of the first fin, two sides of the second fin and above the grid laminated layer and used for isolating the source region, the drain region and the grid laminated layer; a substrate channel region in a region of the substrate proximate the upper surface. The invention provides a new device structure on the basis of the prior FinFET process, so that the gate length of the device is not limited by the dimensions of the Footprint, and the problem caused by the short channel effect is effectively solved.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, particularly, relate to a kind of FinFET manufacture method.
Technical background
Moore's Law is pointed out: on integrated circuit, open ended transistor size doubled every 18 months, and performance also promotes one times simultaneously.At present, along with the development of integrated circuit technology and technology, successively occurred the device such as diode, MOSFET, FinFET, node size constantly reduces.But, since 2011, silicon transistor is close to atomic level, reach physics limit, due to the natural quality of this material, except short-channel effect, the quantum effect of device also creates very large impact to the performance of device, and the speed of service and the performance difficulty of silicon transistor have breakthrough development.Therefore, how when when reducing characteristic size, the performance significantly promoting silicon transistor has become current technological difficulties urgently to be resolved hurrily.
Summary of the invention
The invention provides a kind of U-shaped FinFET structure and manufacture method thereof, the basis of existing FinFET technique proposes a kind of new device architecture, make the grid of device long not by footprint size restrictions, efficiently solve the problem that short-channel effect brings.Concrete, this structure comprises:
Substrate;
First fin and the second fin, first, second fin described is positioned at described types of flexure, parallel to each other;
Gate stack, described gate stack covers the sidewall of described substrate and first, second fin of part;
Source region, described source region be positioned at described first fin not the region that covers by gate stack;
Drain region, described drain region be positioned at described second fin not the region that covers by gate stack;
Side wall, described side wall is positioned at first, second fin both sides described, for isolating source region, drain region and gate stack;
Substrate channel region, described substrate channel region is arranged in the region of described substrate near upper surface.
Wherein, first, second fin described has identical height, thickness and width.
Wherein, the doping type of described substrate channel region is identical with source-drain area with doping content.
Wherein, the height of described gate stack is 1/2 ~ 3/4 of first, second fin height described.
Accordingly, present invention also offers a kind of U-shaped FinFET manufacture method, comprising:
A., substrate (100) is provided, forms channel doping district (150) at described substrate surface
B. at upper formation first fin (210) of described substrate (100) and the second fin (220);
C. gate stack is formed in described substrate (100), described first fin (210) and the second fin (220) top;
D. remove the gate stack of described first fin (210) and the second fin (220) top, form source-drain area;
E. side wall (230) is formed at the first fin (210) do not covered by described gate stack and the second fin (220) both sides.
Wherein, the doping type of described substrate channel region (150) is identical with source-drain area with doping content.
Wherein, in stepb, the method forming described first fin (210) and the second fin (220) is:
1) on described substrate (100), layer of channel material (110) and source and drain material layer (120) is formed successively;
2) described layer of channel material (110) and source and drain material layer (120) are etched, form the first fin (210) and the second fin (220).
Wherein, the method forming described first fin (210) and the second fin (220) is anisotropic etching.
Wherein, described first fin (210) and the second fin (220) have identical height, thickness and width.
Wherein, the distance between described first fin (210) and the second fin (220) is 5 ~ 50nm.
Wherein, the doping type of described substrate channel region (150) is identical with source-drain area with doping content.
Wherein, the height of described gate stack (300) is 1/2 ~ 3/4 of first, second fin described (210,220) height.
Wherein, the method forming described gate stack is atomic layer deposition.
Wherein, the method removing part gate stack is anisotropic selective etching.
Wherein, the method forming described source-drain area is the ion implantation tilted.
Wherein, the method forming described source-drain area is lateral scattering.
The present invention proposes a kind of U-shaped device architecture newly on the basis of existing FinFET technique, compared with prior art, this structure makes device have vertical raceway groove, thus when footprint size constancy, device can regulate grid long by the height changing Fin, improves short-channel effect.First, because device has U-shaped vertical channel structure, device source and drain is suspended from types of flexure, is separated with substrate is natural, and what thus make this device Punchthrough cannot occur, thus has lower subthreshold state slope and leakage current.Secondly, because device has U-shaped vertical channel structure, device source and drain is parallel to each other and is suspended from types of flexure, has effectively isolated device drain terminal electric field to the impact of source, has thus further improved the short-channel effect of device, made device have less DIBL.Again, because device has U-shaped vertical channel structure, device source and drain is suspended from types of flexure and is positioned at same plane, is thus convenient to make source and drain contact.Finally, because in the present invention, substrate channel region is heavily doped, be in the state of unlatching completely, do not control by grid voltage, therefore device has higher operating current.The device architecture that the present invention proposes is completely compatible with existing FinFET technique in manufacture craft, drastically increases device performance.
Accompanying drawing explanation
Fig. 1 ~ Figure 10 schematically shows the profile forming U-shaped FinFET each stage according to the method in embodiment in the present invention 1;
Figure 11 shows the final structure of the device that the method according to the embodiment 2 in the present invention is formed.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiments of the invention are described in detail.
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
The invention provides a kind of FinFET structure, comprising: substrate; First fin and the second fin, first, second fin described is positioned at described types of flexure, parallel to each other; Gate stack, described gate stack covers the sidewall of described substrate and first, second fin of part; Source region, described source region be positioned at described first fin not the region that covers by gate stack; Drain region, described drain region be positioned at described second fin not the region that covers by gate stack; Side wall, described side wall is positioned at first, second fin both sides described, for isolating source region, drain region and gate stack; Substrate channel region, described substrate channel region is arranged in the region of described substrate near upper surface.
Wherein, first, second fin described has identical height, thickness and width.
Wherein, the doping type of described substrate channel region is identical with source-drain area with doping content.
Wherein, the height of described gate stack is 1/2 ~ 3/4 of first, second fin height described.
The present invention proposes a kind of U-shaped device architecture newly on the basis of existing FinFET technique, compared with prior art, this structure makes device have vertical raceway groove, thus when footprint size constancy, device can regulate grid long by the height changing Fin, improves short-channel effect.First, because device has U-shaped vertical channel structure, device source and drain is suspended from types of flexure, is separated with substrate is natural, and what thus make this device Punchthrough cannot occur, thus has lower subthreshold state slope and leakage current.Secondly, because device has U-shaped vertical channel structure, device source and drain is parallel to each other and is suspended from types of flexure, has effectively isolated device drain terminal electric field to the impact of source, has thus further improved the short-channel effect of device, made device have less DIBL.Again, because device has U-shaped vertical channel structure, device source and drain is suspended from types of flexure and is positioned at same plane, is thus convenient to make source and drain contact.Finally, because in the present invention, substrate channel region is heavily doped, be in the state of unlatching completely, do not control by grid voltage, therefore device has higher operating current.The device architecture that the present invention proposes is completely compatible with existing FinFET technique in manufacture craft, drastically increases device performance.
Hereinafter with reference to accompanying drawing, the invention of this reality is described in more detail.In various figures, identical element adopts similar Reference numeral to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.
Be to be understood that, when the structure of outlines device, when one deck, region are called be positioned at another layer, another region " above " or " top " time, can refer to be located immediately at another layer, another over, or itself and another layer, also comprise other layer or region between another region.Further, if overturn by device, this one deck, a region will be positioned at another layer, another region " below " or " below ".
If in order to describe the situation being located immediately at another layer, another over, will adopt herein " directly exist ... above " or " ... above and adjoin with it " form of presentation.
Describe hereinafter many specific details of the present invention, the structure of such as device, material, size, treatment process and technology, more clearly to understand the present invention.But just as the skilled person will understand like that, the present invention can be realized not in accordance with these specific details.Such as, the semi-conducting material of substrate and fin can be selected from IV race semiconductor, as Si or Ge, or Group III-V semiconductor, as GaAs, InP, GaN, SiC, or the lamination of above-mentioned semi-conducting material.
First by reference to the accompanying drawings embodiments of the invention 1 are described in detail.
See Fig. 1, show the first substrate 100 in the present invention.Described first backing material is semi-conducting material, can be silicon, germanium, GaAs etc., and preferably, in the present embodiment, substrate used is silicon substrate.
As shown in Figure 2, then at substrate surface deposit mask layer 101, as the substrate protective film in following ion implantation process, the material of mask layer 101 can be silicon nitride and/or silica;
Next, ion implantation is carried out to substrate 100, form channel doping district 150.The dopant type injected is identical with source-drain area, in the 5 ~ 10nm degree of depth of substrate 100 surface, form certain dopant profiles; Ion implantation technology is one of fundamental technology in this area, and concrete injection process does not repeat them here, and forms device architecture after channel doping district 150 as shown in Figure 3.In addition, can also adopt and carry out epitaxial growth on substrate, use in-situ doped method to form described substrate doped region 150; In-situ doped method is the common technology means in this area, and concrete technology step does not repeat them here.
Next, as shown in Figure 4, epitaxial growth layer of channel material 110 and source and drain material layer 120 successively on described substrate 100.Described layer of channel material 110, can light dope or undope in the major part being device channel region after the process of subsequent technique; Doping type is determined according to the type of device.For N-type device, the doping type of layer of channel material is P type, and adoptable impurity is the group iii elements such as boron; For P type device, the doping type of layer of channel material is N-type, and adoptable impurity is the group-v element such as phosphorus, arsenic.In the present embodiment, the channel region formed in subsequent technique has 1e15cm
-3doping content, the doped chemical adopted is boron, and this doping is by the in-situ doped formation of outer time delay, and concrete processing step is identical with existing technique, does not repeat them here.
Described source and drain material layer 120 is after the process of subsequent technique, and will become the major part in device source drain region, its doping content is equal with source-drain area desired concn; Doping type is determined according to the type of device.For N-type device, the doping type of layer of channel material is N-type, and adoptable impurity is the group-v element such as phosphorus, arsenic; For P type device, the doping type of layer of channel material is P type, and adoptable impurity is the group iii elements such as boron.In the present embodiment, the source-drain area formed in subsequent technique has 1e19cm
-3doping content, the doped chemical adopted is arsenic, and this doping is by the in-situ doped formation of outer time delay, and concrete processing step is identical with existing technique, does not repeat them here.
As shown in Figure 4, the thickness of layer of channel material 110 shown in figure is H2 to structure after formation source and drain material layer 120, equals gate stack heights after device is formed.The thickness of source and drain material layer 120 is H1.
Next, through projection, exposure, development, the common process such as etching etch described layer of channel material 110 and source and drain material layer 120, form the first fin 210 and the second fin 220, and described lithographic method can be dry etching or dry/wet etching.As shown in Figure 5, height after described first fin 210 and the second fin 220 have etched equals the thickness H2+H1 of described layer of channel material 110 and source and drain material layer 120, wherein, the thickness H2 of described layer of channel material 110 is the height of the gate stack formed in subsequent technique, and the thickness H1 of described source and drain material layer 120 is the height of the source-drain area formed in subsequent technique.
Next, as shown in figs 6-8, gate stack 300 is formed above described substrate 100 and described first fin 210 and the second fin 220, identical with existing FinFET technique, described gate stack 300 comprises boundary layer 310, high-K dielectric layer 320, metal gate work function regulating course 330 and polysilicon 340 successively.
Wherein, the material of described boundary layer 310 is silicon dioxide, and for eliminating defect and the interfacial state on first, second fin surface, consider grid-control ability and other performances of device, the thickness of described boundary layer 310 is generally 0.5 ~ 1nm; Described high-K dielectric layer 320 is generally high K dielectric, as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al
2o
3, La
2o
3, ZrO
2, one in LaAlO or its combination, the thickness of gate dielectric layer can be 1nm-10nm, such as 3nm, 5nm or 8nm, and the device architecture after formation high-K dielectric layer is as shown in Figure 6; Described metal gate work function regulating course 330 can adopt the materials such as TiN, TaN to make, and its thickness range is 3nm ~ 15nm, and the device architecture after formation metal gate work function regulating course 330 as shown in Figure 7.
In order to make gate stack 300 have good step coverage characteristics, obtain superior in quality film, the technique of above-mentioned formation gate stack all adopts the method for atomic layer deposition to be formed.
Next, polysilicon 340 is formed on described metal gate work function regulating course 330 surface.First, adopt the method for chemical vapor deposition at described device surface deposit one deck polysilicon, make it cover whole device 10 ~ 50nm; Next, planarization is carried out to described polysilicon layer, described flattening method can be chemico-mechanical polishing (CMP), make described polysilicon surface height consistent, using described metal gate work function regulating course 330 as the stop-layer of chemico-mechanical polishing, make the polysilicon in all the other regions concordant with described metal gate work function regulating course 330; Next, use anisotropic selective etching to carry out orientation etching to described polysilicon layer, make its surface concordant with described source and drain material layer 120, as shown in Figure 8.
Next, isotropism selective etch is carried out to the gate stack covering described first fin 210 and the second fin 220, remove it and be positioned at part above polysilicon layer 340, expose described fin, as shown in Figure 9.The ion implantation tilt to the fin exposed or lateral scattering form described source-drain area.
Next, as shown in Figure 10, the described fin sidewall of the part exposed forms side wall 230, for gate stack and source-drain area being separated.Side wall 230 can by silicon nitride, silica, silicon oxynitride, carborundum and combination thereof, and/or other suitable materials are formed.Side wall 230 can have sandwich construction.Side wall can be formed by comprising deposition-etch technique, and its thickness range can be 10nm-100nm, as 30nm, 50nm or 80nm.
In embodiments of the invention 2, as shown in figure 11, with the silicon on the surface do not covered by side wall 230 for seed crystal carries out epitaxial growth, form source and drain epitaxial region 240, i.e. raised-SD, as shown in figure 11.Carry out in-situ doped epitaxially grown simultaneously, make epitaxial region have the doping content identical with source-drain area.
Next, same as the prior art, above described source-drain area and grid, form silicide and metal electrode, concrete technology step does not repeat them here.
For the U-shaped FinFET structure in the present invention, its grid structure is divided into two parts, except laying respectively at the region covered by gate stack on first, second fin, between fin on substrate 100 by a part that the region that gate stack 300 covers also is device channel.Because substrate thickness is much larger than the thickness of fin, therefore grid is relatively weak for the control ability of the channel region be positioned on substrate, forms certain restriction to the operating current of device.In order to improve this situation, our channel region on substrate has carried out the doping of type identical with source-drain area, ensures no matter grid voltage is for what scope, and the raceway groove at substrate place is all in opening, effectively compensate for the shortcoming that substrate grid-control is more weak, increase the ON state current of device.
Although describe in detail about example embodiment and advantage thereof, being to be understood that when not departing from the protection range of spirit of the present invention and claims restriction, various change, substitutions and modifications can being carried out to these embodiments.For other examples, those of ordinary skill in the art should easy understand maintenance scope in while, the order of processing step can change.
In addition, range of application of the present invention is not limited to the technique of the specific embodiment described in specification, mechanism, manufacture, material composition, means, method and step.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technique existed at present or be about to develop, mechanism, manufacture, material composition, means, method or step later, wherein their perform the identical function of the corresponding embodiment cardinal principle that describes with the present invention or obtain the identical result of cardinal principle, can apply according to the present invention to them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.
Claims (18)
1. a U-shaped FinFET structure, comprising:
Substrate (100);
First fin (210) and the second fin (220), described first fin (210) and the second fin (220) are positioned at described substrate (100) top, parallel to each other;
Gate stack (300), described gate stack covers the sidewall of described substrate and part first fin (210) and the second fin (220);
Source region (410), described source region be positioned at described first fin (210) not the region that covers by gate stack;
Drain region (420), described drain region be positioned at described second fin (220) not the region that covers by gate stack;
Side wall (230), described side wall (230) is positioned at described first fin (210) and the second fin (220) both sides, and gate stack (300) top, for isolating source region, drain region and gate stack;
Substrate channel region (150), described substrate channel region (150) are arranged in the region of described substrate (100) near upper surface.
2. FinFET structure according to claim 1, is characterized in that, described first fin (210) and the second fin (220) have identical height, thickness and width.
3. FinFET structure according to claim 1, is characterized in that, the distance between described first fin (210) and the second fin (220) is 5 ~ 50nm.
4. FinFET structure according to claim 1, is characterized in that, the height of described gate stack (300) is 1/2 ~ 3/4 of first, second fin described (210,220) height.
5. FinFET structure according to claim 1, is characterized in that, the doping type of described substrate channel region (150) is identical with source-drain area with doping content.
6. a U-shaped FinFET manufacture method, comprising:
A., substrate (100) is provided, forms channel doping district (150) at described substrate surface
B. at upper formation first fin (210) of described substrate (100) and the second fin (220);
C. gate stack is formed in described substrate (100), described first fin (210) and the second fin (220) top;
D. remove the gate stack of described first fin (210) and the second fin (220) top and partial sidewall, part first and second fin exposed forms source-drain area;
E. side wall (230) is formed at the first fin (210) do not covered by described gate stack and the second fin (220) both sides.
7. manufacture method according to claim 6, is characterized in that, the doping type of described substrate channel region (150) is identical with source-drain area with doping content.
8. manufacture method according to claim 6, is characterized in that, in stepb, the method forming described first fin (210) and the second fin (220) comprises the steps:
B1) on described substrate (100), layer of channel material (110) and source and drain material layer (120) is formed successively;
B2) described layer of channel material (110) and source and drain material layer (120) are etched, form the first fin (210) and the second fin (220).
9. manufacture method according to claim 6, is characterized in that, the method forming described first fin (210) and the second fin (220) is anisotropic etching.
10. manufacture method according to claim 6, is characterized in that, described first fin (210) and the second fin (220) have identical height, thickness and width.
11. manufacture methods according to claim 6, is characterized in that, the distance between described first fin (210) and the second fin (220) is 5 ~ 50nm.
12. manufacture methods according to claim 6, is characterized in that, the doping type of described substrate channel region (150) is identical with source-drain area with doping content.
13. manufacture methods according to claim 6, is characterized in that, the height of described gate stack (300) is 1/2 ~ 3/4 of first, second fin described (210,220) height.
14. manufacture methods according to claim 6, is characterized in that, the method forming described gate stack is atomic layer deposition.
15. manufacture methods according to claim 6, is characterized in that, the method removing part gate stack is anisotropic selective etching.
16. manufacture methods according to claim 6, is characterized in that, the method forming described source-drain area is the ion implantation tilted.
17. manufacture methods according to claim 6, is characterized in that, the method forming described source-drain area is lateral scattering.
18. manufacture methods according to claim 6, is characterized in that, with the silicon on the surface do not covered by side wall for seed crystal carries out epitaxial growth, form source and drain epitaxial region.
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| CN201410459357.6A CN105470253B (en) | 2014-09-10 | 2014-09-10 | FinFET structure and manufacturing method thereof |
| PCT/CN2014/088595 WO2016037395A1 (en) | 2014-09-10 | 2014-10-15 | Finfet structure and manufacturing method thereof |
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| CN201410459357.6A CN105470253B (en) | 2014-09-10 | 2014-09-10 | FinFET structure and manufacturing method thereof |
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| CN105470253B CN105470253B (en) | 2018-08-10 |
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Citations (5)
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|---|---|---|---|---|
| KR20060130322A (en) * | 2005-06-14 | 2006-12-19 | 주식회사 하이닉스반도체 | Field effect transistor having vertical channel and method thereof |
| US20090039420A1 (en) * | 2007-08-08 | 2009-02-12 | Trivedi Vishal P | Finfet memory cell having a floating gate and method therefor |
| CN101819975A (en) * | 2010-04-28 | 2010-09-01 | 复旦大学 | Vertical channel dual-grate tunneling transistor and preparation method thereof |
| CN102420232A (en) * | 2010-09-28 | 2012-04-18 | 中国科学院微电子研究所 | Flash memory device and forming method thereof |
| CN103956338A (en) * | 2014-04-29 | 2014-07-30 | 复旦大学 | Integrated circuit integrating U-shaped channel device and fin-shaped channel device and preparation method thereof |
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- 2014-09-10 CN CN201410459357.6A patent/CN105470253B/en active Active
- 2014-10-15 WO PCT/CN2014/088595 patent/WO2016037395A1/en active Application Filing
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060130322A (en) * | 2005-06-14 | 2006-12-19 | 주식회사 하이닉스반도체 | Field effect transistor having vertical channel and method thereof |
| US20090039420A1 (en) * | 2007-08-08 | 2009-02-12 | Trivedi Vishal P | Finfet memory cell having a floating gate and method therefor |
| CN101819975A (en) * | 2010-04-28 | 2010-09-01 | 复旦大学 | Vertical channel dual-grate tunneling transistor and preparation method thereof |
| CN102420232A (en) * | 2010-09-28 | 2012-04-18 | 中国科学院微电子研究所 | Flash memory device and forming method thereof |
| CN103956338A (en) * | 2014-04-29 | 2014-07-30 | 复旦大学 | Integrated circuit integrating U-shaped channel device and fin-shaped channel device and preparation method thereof |
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| WO2016037395A1 (en) | 2016-03-17 |
| CN105470253B (en) | 2018-08-10 |
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