CN105448981A - VDMOS device, drain electrode structure thereof, and manufacturing method - Google Patents
VDMOS device, drain electrode structure thereof, and manufacturing method Download PDFInfo
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- CN105448981A CN105448981A CN201410280381.3A CN201410280381A CN105448981A CN 105448981 A CN105448981 A CN 105448981A CN 201410280381 A CN201410280381 A CN 201410280381A CN 105448981 A CN105448981 A CN 105448981A
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Abstract
The invention discloses a VDMOS device, a drain electrode structure thereof, and a manufacturing method. The method comprises the steps: forming a trench on the back surface of a substrate layer through etching; and generating metal layers on the back surface of the substrate layer and in the trench. According to the invention, the back surface of the substrate layer is provided with the trench through etching, thereby enabling the back metal layer or metal silicide layer to be filled in the trench, increasing the contact area between the metal layer and the trench, and reducing the resistance of a substrate. Because there is no need to employ a super-low resistivity substrate and a super-thin substrate, the complex technology and equipment are avoided, thereby simplifying the technology and reducing the cost.
Description
Technical field
The present invention relates to semiconductor chip worker technology field, particularly relate to a kind of can reduce resistance substrate VDMOS device and drain electrode structure and manufacture method.
Background technology
VDMOS (verticaldouble-diffusionmetal-oxide-semiconductor, vertical bilateral diffusion field-effect tranisistor) drain-source the two poles of the earth of device are respectively in the both sides of device, electric current is vertically circulated at device inside, add current density, improve rated current, the conducting resistance of unit are is also less, is a kind of purposes power device widely.At present, (developing direction of VDMOS is: 1, reduce forward conduction resistance to reduce static power consumption; 2, switching speed is improved to reduce transient power loss.
Reduce static power consumption to realize mainly through reducing the total conducting resistance of VDMOS device.Total conducting resistance of device is formed primarily of three parts: 1. channel resistance; 2. drift zone resistance; 3. resistance substrate.The size of this three partial ohmic value is determined by the structure of device and manufacturing process, and epitaxial loayer directly affects drift zone resistance, and source electrode and grid structure directly affect channel resistance, and the drain electrode structure of device then directly affects resistance substrate.
At present, by adopting new construction and new technology, the channel resistance of VDMOS device and drift zone resistance become more and more little, reduce resistance substrate and just become extremely important.At present, the method that reduction resistance substrate is commonly used adopts the super-low resistivity substrate of high-concentration dopant and ultra-thin substrate (usual thickness is less than 100um) to manufacture VDMOS device, and then reduce resistance substrate.
But these two kinds of methods need more complicated growth technologies and back process, improve the manufacturing cost of device, process complexity must improve and also had influence on the rate of finished products of device.Super-low resistivity substrate technology requires to carry out more strict control to substrate autodoping effect, which further increases the manufacture difficulty of device.Ultra-thin substrate technology reduces resistance substrate by thinning thickness of detector, but due to device very thin, higher requirement be it is also proposed to the sealed in unit of device and technology, further increases the manufacturing cost of device.
Summary of the invention
The invention provides a kind of can reduce resistance substrate power device and drain electrode structure and manufacture method, complex manufacturing technology when reducing resistance substrate for solving in prior art, the problem that cost is higher.
A manufacture method for VDMOS device drain electrode structure, comprising:
Groove is formed at the back-etching of substrate layer;
Metal level is generated in the back side and groove of described substrate layer.
Further, the described back-etching at substrate forms groove, comprising:
Silicon oxide layer is generated at the back side of substrate layer;
Silicon oxide layer makes the mask pattern forming groove with photoresist;
Etch away not by silicon oxide layer that described mask pattern covers;
Remove photoresist;
Utilize the silicon oxide layer be not etched as mask, etch groove;
Remove silicon oxide layer.
Further, described etching adopts dry etching.
Further, described dry etching comprises RIE (ReactiveIonEtching, reactive ion etching method) or ICP (inductivelycoupledplasma, inductively coupled plasma method).
Further, the degree of depth of described groove is not less than 1/10 of substrate layer thickness.
Further, generate metal level in the back side and groove of described substrate layer after, also comprise:
Described metal level is annealed, forms ohmic contact.
A kind of VDMOS device drain electrode structure, comprising: fluted substrate layer is offered at the back side, and is arranged at the metal level in the back side of described substrate layer and groove.
Further, the degree of depth of described groove is not less than 1/10 of substrate layer thickness.
Further, described metal level and substrate layer form ohmic contact.
A kind of VDMOS device, comprises above-mentioned drain electrode structure.
The present invention by the back-etching groove at substrate layer, and makes the metal level at the back side or metal silicide layer fill described groove, adds contact area between the two, reduces resistance substrate thus.Due to without the need to using super-low resistivity substrate and ultra-thin substrate, avoiding and using complicated technology and equipment, can Simplified flowsheet, reduce costs.
Accompanying drawing explanation
The flow chart of the manufacture method of the VDMOS device drain electrode structure that Fig. 1 provides for embodiment one;
The flow chart of the manufacture method of the VDMOS device drain electrode structure that Fig. 2 provides for embodiment two;
The structural representation of Fig. 3 to Figure 10 for adopting the method that provides of embodiment two to carry out each step when drain electrode structure makes;
A kind of trench VDMOS device structural representation that Figure 11 provides for embodiment five;
A kind of plane VDMOS device structural representation that Figure 12 provides for embodiment six.
Embodiment
Below in conjunction with Figure of description and specific embodiment, technical scheme of the present invention is described in detail.
Embodiment one
Present embodiments provide a kind of manufacture method of VDMOS device drain electrode structure, the flow process of the method as shown in Figure 1, comprising:
Step 101, forms groove at the back-etching of substrate layer;
Step 102, generates metal level in the back side and groove of substrate layer.
The embodiment of the present invention by the back-etching groove at substrate layer, and makes the metal level filling groove at the back side, adds contact area between the two, reduces resistance substrate thus.Due to without the need to using super-low resistivity substrate and ultra-thin substrate, avoiding and using complicated technology and equipment, can Simplified flowsheet, reduce costs.
As a kind of optimal way of the present embodiment, after generation metal level, annealing in process can also be carried out to it, makes it form metal silicide, thus form ohmic contact.Because ohmic contact can not produce obvious additional impedance, relative to directly adopting metal level as metal back electrode, its resistance is lower.
Embodiment two
Present embodiments provide the manufacture method of another kind of VDMOS device drain electrode structure, its Making programme as shown in Figure 2, comprises following step:
Step 201, generate silicon oxide layer 2 at the back side of substrate layer 1, its structure as shown in Figure 3.
In this step, the effect of silicon oxide layer is in subsequent steps as mask during etching groove, and therefore its thickness needs to reach etching requirement, and ordinary circumstance is issued to more than 0.01um.
Step 202, silicon oxide layer 2 makes the mask pattern of 3 formation grooves with photoresist, forms structure as shown in Figure 4.
Step 203, etches away the silicon oxide layer 2 do not covered by mask pattern, forms structure as shown in Figure 5.
Step 204, removes photoresist 3, forms structure as shown in Figure 6.
Step 205, utilizes the silicon oxide layer 2 be not etched as mask, etches groove 4, form structure as shown in Figure 7.In this step and step 203, its etching all adopts the mode of dry etching, and concrete grammar includes but not limited to RIE, ICP etc.
In the etching process of groove, need to control its degree of depth.If the degree of depth of groove is less than substrate layer thickness 1/10, the contact area increased due to it is less, reduces the effect of resistance substrate and not obvious.Therefore, when actual fabrication, gash depth at least will be etched to 1/10 of substrate layer thickness, and if desired increases contact area further, adopts and is etched to 1/2,7/10 or 9/10 of substrate layer thickness etc.
In addition, the density of groove is larger in theory, and its contact area increased is also larger, and the reduction effect of resistance substrate is more obvious too.But along with the increase of groove density, the mechanical strength of substrate layer can decline thereupon, the difficulty of technique also can promote simultaneously, and therefore the density of groove also should not arrange excessive.
Step 206, removes silicon oxide layer 2, forms structure as shown in Figure 8.In this step, silicon oxide layer can use mixed acid solution to carry out erosion removal, to be specifically as follows in sulfuric acid, hydrochloric acid, nitric acid and hydrofluoric acid at least two kinds of sour mixed solutions.
Step 207, generates metal level 50 in the back side of substrate layer 1 and groove 4, forms structure as shown in Figure 9.
Step 208, anneals to metal level, and form ohmic contact, concrete structure as shown in Figure 10.By annealing in this step, the silicon on original metal level and substrate layer surface and metal are reacted, form metal silicide 5, to form ohmic contact, reduce resistance further thus.
Adopt the grid structure that said method makes, owing to not needing to adopt super-low resistivity substrate technology or ultra-thin substrate technology, can simplification of flowsheet and reduce manufacturing cost.In addition, because substrate is not thinning, therefore the thermal capacitance change of device is little, can not produce the defect that when adopting ultra-thin substrate, device thermal capacitance obviously reduces.After generating metal silicide in groove, because its thermal conductivity is better, and the setting of groove turn increases contact area, so significantly can reduce the thermal resistance of device.
Embodiment three
Present embodiments provide a kind of VDMOS device drain electrode structure, its concrete structure can step 207 is formed in reference example two device architecture, as shown in Figure 9, comprises substrate layer 1 and metal level 50.Wherein, the back side of substrate layer 1 offers groove 4, and metal level 50 fills full groove 4 and cover the back side of substrate layer 1, as metal back electrode.
Relative to the VDMOS device drain electrode structure of routine, due to substrate layer 1 having offered groove, the contact area of metal level 50 and substrate layer 1 is increased, reduces resistance substrate, when actual fabrication, gash depth preferably ensures to be etched to 1/10 of substrate layer thickness to reach effect of coming down to a lower group more as well.And relative to adopting the drain electrode structure of super-low resistivity substrate technology or ultra-thin substrate technology, due to without the need to using complicated technology and equipment, therefore, it is possible to Simplified flowsheet, reduce costs.
In addition, because substrate is not thinning, therefore the thermal capacitance change of device is little, can not produce the defect that when adopting ultra-thin substrate, device thermal capacitance obviously reduces.After generating metal level in groove, because its thermal conductivity is better, and the setting of groove turn increases contact area, so significantly can reduce the thermal resistance of device.
Embodiment four
Present embodiments provide a kind of VDMOS device drain electrode structure, its concrete structure can step 208 is formed in reference example two device architecture, as shown in Figure 10, comprises substrate layer 1 and metal silicide 5.Wherein, the back side of substrate layer 1 offers groove 4, and metal silicide 5 is filled full groove 4 and covered the back side of substrate layer 1.Metal silicide 5 is undertaken annealing formed, and makes to define ohmic contact between original metal level and substrate layer, therefore its to fall low-resistance effect more remarkable.
Embodiment five
Present embodiments provide a kind of plane VDMOS device, the drain electrode structure of this device adopts the scheme provided in embodiment three, is made up of the substrate layer 1 of with groove 4 and the metal level 50 of the surperficial also filling groove of covering substrate layer.And the structure of remainder is identical with conventional plane VDMOS device, comprise epitaxial loayer 6, be arranged on the tagma 7 of epitaxial loayer, the grid structure 10 be made up of grid polycrystalline silicon, gate oxide and dielectric layer, and the source configuration to be made up of source region 8 and source metal 9, concrete structure is as shown in figure 11.
Relative to the VDMOS device of routine, due to substrate layer 1 having offered groove, the contact area of metal level 50 and substrate layer 1 is increased, has reduced resistance substrate.And relative to adopting the drain electrode structure of super-low resistivity substrate technology or ultra-thin substrate technology, due to without the need to using complicated technology and equipment, therefore, it is possible to Simplified flowsheet, reduce costs.
In addition, because substrate is not thinning, therefore the thermal capacitance change of device is little, can not produce the defect that when adopting ultra-thin substrate, device thermal capacitance obviously reduces.After generating metal level in groove, because its thermal conductivity is better, and the setting of groove turn increases contact area, so significantly can reduce the thermal resistance of device.
Embodiment six
Present embodiments provide a kind of trench VDMOS device, the drain electrode structure of this device adopts the scheme provided in embodiment four, is made up of the substrate layer 1 of with groove 4 and the metal silicide 5 of the surperficial also filling groove of covering substrate layer.And the structure of remainder is identical with conventional trench VDMOS device, comprise epitaxial loayer 6, be arranged on the tagma 7 of epitaxial loayer, be arranged on the grid structure 10 be made up of grid polycrystalline silicon, gate oxide and dielectric layer in epitaxial loayer groove, and the source configuration to be made up of source region 8 and source metal 9, concrete structure is as shown in figure 12.
Because metal silicide 5 is undertaken annealing being formed by metal level, make to define ohmic contact between original metal level and substrate layer, therefore its to fall low-resistance effect more remarkable.
In addition, the drain electrode structure that embodiment three provides can be applied to trench VDMOS device too, and the drain electrode structure that embodiment four provides can be applied to plane VDMOS device too, all can play same beneficial effect.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a manufacture method for vertical bilateral diffusion field-effect tranisistor VDMOS device drain electrode structure, is characterized in that, comprising:
Groove is formed at the back-etching of substrate layer;
Metal level is generated in the back side and groove of described substrate layer.
2. the method for claim 1, is characterized in that, the described back-etching at substrate forms groove, comprising:
Silicon oxide layer is generated at the back side of substrate layer;
Silicon oxide layer makes the mask pattern forming groove with photoresist;
Etch away not by silicon oxide layer that described mask pattern covers;
Remove photoresist;
Utilize the silicon oxide layer be not etched as mask, etch groove;
Remove silicon oxide layer.
3. method as claimed in claim 2, is characterized in that, described etching adopts dry etching.
4. method as claimed in claim 3, it is characterized in that, described dry etching is reactive ion etching method RIE or inductively coupled plasma method ICP.
5. the method as described in as arbitrary in Claims 1 to 4, it is characterized in that, the degree of depth of described groove is not less than 1/10 of substrate layer thickness.
6. the method as described in as arbitrary in Claims 1 to 4, is characterized in that, after generating metal level, also comprise in the back side and groove of described substrate layer:
Described metal level is annealed, forms ohmic contact.
7. a vertical bilateral diffusion field-effect tranisistor VDMOS device drain electrode structure, is characterized in that, comprising: fluted substrate layer is offered at the back side, and is arranged at the metal level in the back side of described substrate layer and groove.
8. drain electrode structure as claimed in claim 7, it is characterized in that, the degree of depth of described groove is not less than 1/10 of substrate layer thickness.
9. drain electrode structure as claimed in claim 7, it is characterized in that, described metal level and substrate layer form ohmic contact.
10. a vertical bilateral diffusion field-effect tranisistor VDMOS device, is characterized in that, comprises the arbitrary described drain electrode structure of claim 7 ~ 9.
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| CN201410280381.3A CN105448981A (en) | 2014-06-20 | 2014-06-20 | VDMOS device, drain electrode structure thereof, and manufacturing method |
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| CN201410280381.3A CN105448981A (en) | 2014-06-20 | 2014-06-20 | VDMOS device, drain electrode structure thereof, and manufacturing method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106952876A (en) * | 2017-03-16 | 2017-07-14 | 浙江大学 | A kind of metal laminated silicon carbide substrates structure for filling out groove array |
| CN108682687A (en) * | 2018-04-11 | 2018-10-19 | 大连理工大学 | Half longitudinal type Ohm contact electrode and preparation method thereof |
| CN113707549A (en) * | 2021-08-18 | 2021-11-26 | 深圳市美浦森半导体有限公司 | Manufacturing method and device for reducing MOSFET substrate resistance |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6111280A (en) * | 1997-01-15 | 2000-08-29 | University Of Warwick | Gas-sensing semiconductor devices |
| CN1474459A (en) * | 2002-08-09 | 2004-02-11 | ������������ʽ���� | Semiconductor device with high structure reliability and low parasitic capacitance |
| CN103021858A (en) * | 2011-09-27 | 2013-04-03 | 万国半导体股份有限公司 | Power MOS transistor device with low on-resistance and preparation method thereof |
-
2014
- 2014-06-20 CN CN201410280381.3A patent/CN105448981A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6111280A (en) * | 1997-01-15 | 2000-08-29 | University Of Warwick | Gas-sensing semiconductor devices |
| CN1474459A (en) * | 2002-08-09 | 2004-02-11 | ������������ʽ���� | Semiconductor device with high structure reliability and low parasitic capacitance |
| CN103021858A (en) * | 2011-09-27 | 2013-04-03 | 万国半导体股份有限公司 | Power MOS transistor device with low on-resistance and preparation method thereof |
Non-Patent Citations (2)
| Title |
|---|
| PETER VAN ZANT著 韩郑生 赵树武 译: "《芯片制造-半导体工艺制程实用教程（第五版）》", 31 August 2010, 电子工业出版社 * |
| 吴德馨等: "《现代微电子技术》", 31 January 2002 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106952876A (en) * | 2017-03-16 | 2017-07-14 | 浙江大学 | A kind of metal laminated silicon carbide substrates structure for filling out groove array |
| CN108682687A (en) * | 2018-04-11 | 2018-10-19 | 大连理工大学 | Half longitudinal type Ohm contact electrode and preparation method thereof |
| CN113707549A (en) * | 2021-08-18 | 2021-11-26 | 深圳市美浦森半导体有限公司 | Manufacturing method and device for reducing MOSFET substrate resistance |
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