CN105376008A - Low density parity check code (LDPC) word interleaving mapping method and LDPC word de-interleaving demapping method - Google Patents

Abstract

The invention provides a low density parity check code (LDPC) word interleaving mapping method and an LDPC word de-interleaving demapping method. The LDPC word interleaving mapping method comprises the steps of performing first bit interleaving on a verification part in the LDPC word for obtaining a verification bit stream; splicing the information bit part in the LDPC word with the verification bit stream for obtaining the LDPC word after first-time bit interleaving; dividing the LDPC word after first-time bit interleaving into a plurality of continuous bit sub-blocks according to a preset length and changing the arrangement sequence of the bit sub-blocks according to a corresponding bit exchange pattern for forming the LDPC word after second-time bit interleaving; writing the LDPC code after second-time bit interleaving according a row sequence and reading according to a line sequence for obtaining the LDPC code after third-time bit interleaving; and performing constellation mapping on the LDPC word after third-time bit interleaving for obtaining a symbol flow. The interleaving mapping methods and the de-interleaving demapping methods are selected for different LDPC lists so that system performance is improved.

Description

The interlace map method of LDPC code word and deinterleaving de-mapping method

Technical field

The present invention relates to digital television techniques field, particularly a kind of intertexture of LDPC code word and mapping method and deinterleaving de-mapping method.

Background technology

In existing broadcast communication standard, LDPC coding, Bit Interleave and constellation mapping are code modulation modes the most common.In different emission systems, LDPC coding, Bit Interleave and constellation mapping all need independent design, and combined debugging, to obtain best channel performance.Therefore, how forming Bit Interleave targetedly for specific LDPC code word and constellation mapping mode, is a technical barrier of this area.

Summary of the invention

The problem that the present invention solves cannot form Bit Interleave targetedly for specific LDPC code word and constellation mapping mode in prior art.

For solving the problem, embodiments providing a kind of intertexture and mapping method of LDPC code word, comprising the steps: the check part in described LDPC code word to carry out first time Bit Interleave to obtain check bit stream; Information bit part in described LDPC code word and described check bit stream are spliced into the LDPC code word after first time Bit Interleave; LDPC code word after described first time Bit Interleave is divided into the multiple sub-blocks of bits of continuous print by predetermined length, and puts in order the LDPC code word after forming second time Bit Interleave according to sub-blocks of bits described in corresponding bit exchange pattern change; LDPC code word column major order write memory space after described second time Bit Interleave is also sequentially read the LDPC code word after obtaining third time Bit Interleave by row in this memory space; Constellation mapping is carried out to obtain symbol stream according to corresponding planisphere to the LDPC code word after described third time Bit Interleave.

The embodiment of the present invention additionally provides a kind of deinterleaving de-mapping method of LDPC code word, comprises the steps: to carry out soft demapping process to obtain bit soft value data to symbol stream soft value data according to corresponding planisphere; Wherein said symbol stream soft value data are the symbol stream that interlace map method that receiving terminal receives LDPC code word described above obtains; Described bit soft value data are sequentially written in memory space by row and column major order reads to obtain first time than the bit soft value data after deinterleave in this memory space; Described first time is divided into the multiple bit soft value data sub-block of continuous print than the bit soft value data after deinterleave by predetermined length, and according to bit soft value data sub-block described in corresponding bit exchange pattern change put in order form second time than the bit soft value data after deinterleave; Described second time is carried out third time than deinterleave to obtain third time than the bit soft value data after deinterleave than the bit soft value data of the check part corresponded in LDPC code word in the bit soft value data after deinterleave; Described second time is spliced into bit soft value data flow with described third time than the bit soft value data after deinterleave than in the bit soft value data after deinterleave; LDPC decoding process is carried out to obtain decoded bitstream data to described bit soft value data flow.

Compared with prior art, technical solution of the present invention has the following advantages:

Corresponding interlace map and deinterleaving de-mapping method is selected better to be promoted to make systematic function for specific LDPC code table.

Accompanying drawing explanation

Fig. 1 is the schematic flow sheet of the embodiment of the interlace map method of a kind of LDPC code word of the present invention;

Fig. 2 is the schematic flow sheet of the embodiment of the deinterleaving de-mapping method of a kind of LDPC code word of the present invention;

Fig. 3 be in the interlace map method of a kind of LDPC code word of the present invention to the check part in LDPC code word carry out first time Bit Interleave to obtain the schematic diagram of check bit stream;

Fig. 4 is the schematic diagram put in order according to sub-blocks of bits described in bit exchange pattern change in the interlace map method of a kind of LDPC code word of the present invention.

Embodiment

Inventor finds in prior art, cannot form Bit Interleave targetedly for specific LDPC code word and constellation mapping mode.

For the problems referred to above, inventor is through research, provide a kind of interlace map method and deinterleaving de-mapping method of LDPC code word, select corresponding interlace map and deinterleaving de-mapping method better to be promoted to make systematic function for different LDPC code tables.

For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.

In embodiments of the present invention, transmitter terminal is: first the bit stream after message sink coding, Bose-Chaudhuri-Hocquenghem Code is input to the coding that LDPC encoder carries out the LDPC code word of specific code check code length, input bit interleaver afterwards, interleaving treatment is carried out according to certain specific Bit Interleave patterning method, subsequently the data after Bit Interleave process are carried out the 256QAM constellation mapping of corresponding code check, modulate afterwards, launch, experience channel.Receiver end is: the data after channel are carried out demodulation, and the data input De-mapping module then after demodulation, carries out 256QAM demapping.Afterwards the bit soft value information that De-mapping module exports is input to de-interleaving block and carries out deinterleaving, output to ldpc decoder afterwards, the decoding based on specific LDPC code word is carried out to it, output bit flow of finally decoding.

As shown in Figure 1 be the schematic flow sheet of the embodiment of the interlace map method of a kind of LDPC code word of the present invention.With reference to figure 1, the interlace map method of LDPC code word comprises the steps:

Step S11: the check part in described LDPC code word is carried out first time Bit Interleave to obtain check bit stream;

Step S12: the information bit part in described LDPC code word and described check bit stream are spliced into the LDPC code word after first time Bit Interleave;

Step S13: the LDPC code word after described first time Bit Interleave is divided into the multiple sub-blocks of bits of continuous print by predetermined length, and put in order the LDPC code word after forming second time Bit Interleave according to sub-blocks of bits described in corresponding bit exchange pattern change;

Step S14: the LDPC code word column major order write memory space after described second time Bit Interleave is also sequentially read the LDPC code word after obtaining third time Bit Interleave by row in this memory space;

Step S15: constellation mapping is carried out to obtain symbol stream according to corresponding planisphere to the LDPC code word after described third time Bit Interleave.

In the present embodiment, described step S11 specifically comprises the steps: the check part column major order write memory space in described LDPC code word and sequentially reads to obtain check bit stream in this memory space by row.

Particularly, the check portion generating LDPC code word is divided and carries out Bit Interleave: check part M the bit altogether of LDPC code word, write in a memory space by row, often arrange Q bit, altogether L row, that is M=Q*L, then sequentially reads by row.Its specific implementation process is with reference to shown in figure 3.

In described step S13, the LDPC code word after described first time Bit Interleave is divided into the multiple sub-blocks of bits of continuous print by predetermined length, and wherein said predetermined length is 320.Further, according to sub-blocks of bits described in corresponding bit exchange pattern change put in order formed second time Bit Interleave after LDPC code word.Its detailed process is detailed as shown in Figure 4, in the diagram, and (m ₀, m ₁..., m _n/320-1) be the bit exchange pattern of 320 length bits sub-blocks.

Particularly, the code length of the LDPC code word in LDPC code table is 57600, and corresponding bit exchange pattern is:

1717717233165104323710813151739461114963101787944114169543211599218862265467154199971411121251173411012611933815512710045166170139914713766174901494164745616241291914310757122778583597398151526413695121750302214428012281681204016365539615213911797036891426815331150123161602061015811325812412915613013535102103173727616711614684134421288817171140118555015712410613814817517811510548715132231458616014910917611947162761485813382693

It should be noted that, in the present embodiment, each numerical value in described bit exchange pattern refers to the position without sub-blocks of bits described before bit exchange.Such as, first numerical value 17 implication in above-mentioned bit exchange pattern refers to and original after bit exchange, nowadays becomes first sub-blocks of bits without the 18th sub-blocks of bits before bit exchange.

Corresponding planisphere is:

In described step S14, such as, be the LDPC code word (the LDPC code word after second time Bit Interleave) of 57600 bits for code length, its column major order write memory space is also sequentially read by row in this memory space, wherein every row 7200 bit, totally 8 row.

Afterwards to the bitstream data (b after above-mentioned Bit Interleave ₀, b ₁..., b _n-1), according to 256QAM planisphere, the decimal number corresponding to every eight binary bit sequence is mapped to some constellation point, obtains symbol stream (the corresponding constellation point of each complex symbol).Such as, the corresponding decimal number of 8 bits ' 00001101 ' of input is 13, then correspond to the constellation point of the 0.39661-0.6648i in 256QAM planisphere, this constellation point being shown as on real number axis and axis of imaginaries, real number axis 0.39661, axis of imaginaries-0.6648.Then utilize symbol stream to carry out generation OFDM symbol at modulation module, finally launch.

In the present embodiment, described LDPC code word be to message sink coding after bit stream obtain after specific LDPC coding, wherein said specific LDPC coding can adopt prior art to realize.

Particularly, the code word of this LDPC is with L × L (L is generally 320) for sub-block size, and code table is as follows:

Table 1 code check 7/12N _ldpc=57600, L × L=320 × 320, Q=75, M=24000

Its coding method is as follows:

By the bit stream after message sink coding, be split as block of information one by one, each block of information is made up of K information bit, is expressed as S=(s ₀, s ₁..., s _k-1).By the specific LDPC coding in Fig. 1, be will according to S=(s ₀, s ₁..., s _k-1) generate M check bit P=(p ₀, p ₁..., p _m-1).Namely the code word Λ=(λ of N number of bit is obtained ₀, λ ₁..., λ _n-1), wherein N=K+M.Λ can be expressed as again, Λ=(s ₀, s ₁..., s _k-1, p ₀, p ₁..., p _m-1).

The step of coding is:

1) initialization λ _i=s _i, i=0,1 ..., K-1.p _j＝0，j＝0,1,...,M-1

2) to information bit λ ₀, add up for the check bit of address to the first row numeral in code table, lift table 1 code check 7/12, the code table of code length 57600 is example:

3) $p_{725}=p_{725}\⊕{\mathrm{\λ}}_0,p_{867}=p_{867}\⊕{\mathrm{\λ}}_0,p_{1334}=p_{1334}\⊕{\mathrm{\λ}}_0,......p_{22659}=$ $p_{22659}\⊕{\mathrm{\λ}}_0,p_{23551}=p_{23551}\⊕{\mathrm{\λ}}_0.$

4) for an ensuing L-1 information bit, (usual L=320), λ _m, m=1,2 ...., L-1, adds up with the check bit according to following y being address respectively by each information bit:

y＝{x+(mmod320)×Q}modM

Wherein, x refers to and λ ₀relevant check digit address, act table 1 is example, the numeral of the first row in x and code table:

725867133414971916504952735610803290069461985510368110291144311713121861279813208135511435914576158631640316552172301756717630180351844219321206132107321375213902265923551

And wherein m is the quantity of check bit, and be also the quantity that check matrix is capable, L is the size of sub-block in check matrix, is generally 320.

Code word for table 1 is example,

$Q=\frac{M}{L}=\frac{24000}{320}=75.$

$p_{800}=p_{800}\⊕{\mathrm{\λ}}_1,p_{942}=p_{942}\⊕{\mathrm{\λ}}_1,p_{1409}=p_{1409}\⊕{\mathrm{\λ}}_1,......,p_{22734}=p_{22734}\⊕{\mathrm{\λ}}_1,$ $p_{23626}=p_{23626}\⊕{\mathrm{\λ}}_1.$

5) for L information bit λ _l, according to the second line number word address in code table, check bit is added up.Same for L information bit λ _lan ensuing L-1 information bit, continues according to step 3) in formula check bit is added up, the at this time numeral of the second row in the x of the formula of step 3 kind and code table.

6) in like manner, for 2L, 3L, 4L ... iL ... individual information bit, according to difference the 3rd in code table, 4, 5, (i+1) add up to check bit in the address that L.... is capable, L-1 information bit after its information bit is then respectively according to step 3) in formula check bit is added up, note the x of the formula of at this time step 3 kind corresponding be row in code table corresponding to a current i-th L information bit, L-1 bit after such as the i-th L information bit, its applying step 3) in formula time corresponding x address be (i+1) in code table OK.

7) step 5 is finished) after, be done as follows:

wherein i=1,2,3 ..., M-1.

The embodiment of the present invention additionally provides a kind of deinterleaving de-mapping method of LDPC code word.As shown in Figure 2 be the schematic flow sheet of the embodiment of the deinterleaving de-mapping method of a kind of LDPC code word of the present invention.With reference to figure 2, the deinterleaving de-mapping method of LDPC code word comprises the steps:

Step S21: soft demapping process is carried out to obtain bit soft value data according to corresponding planisphere to symbol stream soft value data;

Step S22: described bit soft value data are sequentially written in memory space by row and column major order reads to obtain first time than the bit soft value data after deinterleave in this memory space;

Step S23: described first time is divided into the multiple bit soft value data sub-block of continuous print than the bit soft value data after deinterleave by predetermined length, and according to bit soft value data sub-block described in corresponding bit exchange pattern change put in order form second time than the bit soft value data after deinterleave;

Step S24: described second time is carried out third time than deinterleave to obtain third time than the bit soft value data after deinterleave than the bit soft value data of the check part corresponded in LDPC code word in the bit soft value data after deinterleave;

Step S25: described second time is spliced into bit soft value data flow with described third time than the bit soft value data after deinterleave than in the bit soft value data after deinterleave;

Step S26: LDPC decoding process is carried out to obtain decoded bitstream data to described bit soft value data flow.

In the present embodiment, described step S24 specifically comprises: described second time is sequentially written in memory space by row than the bit soft value data of the check part corresponded in LDPC code word in the bit soft value data after deinterleave and column major order reads to obtain third time than the bit soft value data after deinterleave in this memory space.

Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.

Claims (7)

1. an interlace map method for LDPC code word, is characterized in that, comprise the steps:

Check part in described LDPC code word is carried out first time Bit Interleave to obtain check bit stream;

Information bit part in described LDPC code word and described check bit stream are spliced into the LDPC code word after first time Bit Interleave;

LDPC code word after described first time Bit Interleave is divided into the multiple sub-blocks of bits of continuous print by predetermined length, and puts in order the LDPC code word after forming second time Bit Interleave according to sub-blocks of bits described in corresponding bit exchange pattern change;

LDPC code word column major order write memory space after described second time Bit Interleave is also sequentially read by row in this memory space, obtains the LDPC code word after third time Bit Interleave;

Constellation mapping is carried out to obtain symbol stream according to corresponding planisphere to the LDPC code word after described third time Bit Interleave; Wherein, described bit exchange pattern and described planisphere are all corresponding from the LDPC code table of different code check.

2. the interlace map method of LDPC code word as claimed in claim 1, is characterized in that, the check part in described LDPC code word is carried out first time Bit Interleave and comprises to obtain check bit stream:

Check part column major order write memory space in described LDPC code word also is sequentially read to obtain check bit stream by row in this memory space.

3. the interlace map method of LDPC code word as claimed in claim 1, it is characterized in that, described predetermined length is 320 bits.

4. the interlace map method of LDPC code word as claimed in claim 1, is characterized in that, in described LDPC code table, the code length of LDPC code word is 57600 bits, code check is 7/12; Code table is:

Corresponding bit exchange pattern is: 17,177,172,331,651,043,237,108,131,517,394,611,149,631,017,879,441,141,695 43,211,599,218,862,265,467,154,199,971,411,121,251,173,411,012,611,933,815 51,271,004,516,617,013,991,471,376,617,490,149,416,474,561,624,129,191,431 07,571,227,785,835,973,981,515,264,136,951,217,503,022,144,280,122,816,812 04,016,365,539,615,213,911,797,036,891,426,815,331,150,123,161,602,061,015 81,132,581,241,291,561,301,353,510,210,317,372,761,671,161,468,413,442,128 88,171,711,401,185,550,157,124,106,138,148,175,178,115,105,487,151,322,314 58616014910917611947162761485813382693

Corresponding planisphere is:

5. the interlace map method of LDPC code word as claimed in claim 1, it is characterized in that, the number of described column major order is 8 row.

6. a deinterleaving de-mapping method for LDPC code word, is characterized in that, comprise the steps:

Soft demapping process is carried out to obtain bit soft value data according to corresponding planisphere to symbol stream soft value data; Wherein said symbol stream soft value data are the symbol stream that interlace map method that receiving terminal receives LDPC code word as claimed in claim 1 obtains;

Described bit soft value data are sequentially written in memory space by row and column major order reads to obtain first time than the bit soft value data after deinterleave in this memory space;

Described first time is divided into the multiple bit soft value data sub-block of continuous print than the bit soft value data after deinterleave by predetermined length, and according to bit soft value data sub-block described in corresponding bit exchange pattern change put in order form second time than the bit soft value data after deinterleave;

Described second time is carried out third time than deinterleave to obtain third time than the bit soft value data after deinterleave than the bit soft value data of the check part corresponded in LDPC code word in the bit soft value data after deinterleave;

Described second time is spliced into bit soft value data flow with described third time than the bit soft value data after deinterleave than in the bit soft value data after deinterleave;

LDPC decoding process is carried out to obtain decoded bitstream data to described bit soft value data flow.

7. the deinterleaving de-mapping method of LDPC code word as claimed in claim 6, it is characterized in that, describedly described second time is carried out third time than the bit soft value data of the check part corresponded in LDPC code word in the bit soft value data after deinterleave comprise than the bit soft value data after deinterleave to obtain third time than deinterleave:

Described second time is sequentially written in memory space by row than the bit soft value data of the check part corresponded in LDPC code word in the bit soft value data after deinterleave and column major order reads in this memory space, the described columns that also column major order reads of write is by row 8 row, obtains third time than the bit soft value data after deinterleave.