CN105335324A - Receiver for high-speed serial bus and data receiving method - Google Patents
Receiver for high-speed serial bus and data receiving method Download PDFInfo
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- CN105335324A CN105335324A CN201510885448.0A CN201510885448A CN105335324A CN 105335324 A CN105335324 A CN 105335324A CN 201510885448 A CN201510885448 A CN 201510885448A CN 105335324 A CN105335324 A CN 105335324A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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Abstract
The invention provides a receiver for a high-speed serial bus and a data receiving method. The receiver comprises a decoder used for determining the type of control data units in received data, a counter used for counting the times of repetition of control data units of a specific type, a controller used for controlling the counter to count the times of repetition of control data units of the specific type according to the type, determined by the decoder, of the control data units, and a buffer used for storing processed received data, and when the times of repetition reaches a reference value, at least one repeated control data unit of the specific type is discarded from the received data.
Description
Technical field
The present invention relates to high-speed serial bus transmission technology, more specifically, relate to the receiver for high-speed serial bus and the method receiving data.
Background technology
Along with digital device is in the widespread use in various field, need the bandwidth of larger memory data output and Geng Gao, develop the high-speed serial bus technology of such as Serial Advanced Technology Attachment (SATA), peripheral assembly high speed interconnect (PCIe) and hypervelocity I (UHS-I) and hypervelocity II (UHS-II).For UHS-II, the transfer rate up to 156MB/s (full duplex) or 312MB/s (half-duplex) can be realized by two paths (lane) between main frame and storage card.
In physical layer transmission, the interface both sides between main frame from storage card are in different clock zones.Be between the transmission of different clock zones and the clock source receiving both sides and usually have phase differential, even frequency also has fine distinction.When in order to reduce electromagnetic interference (EMI) use spread spectrum clock (SSC) technology time, the above-mentioned difference between clock source may be more serious.
For this reason, elastic buffer is usually adopted to solve the problems referred to above.That is, by the reception data-pushing (push) from the first clock zone in elastic buffer, and eject (pop) to second clock territory.But if the clock frequency in second clock territory is for a long time lower than the clock frequency of the first clock zone, then the spill-over of elastic buffer possibility, makes to receive data further.At present, UHS-II does not specify how resolve buffer device spill-over problem.Usually, the extra hardware configuration of design is needed to deal with impact damper spill-over.In addition, when using two tunnel data in a half-duplex mode simultaneously, also can produce other problem, namely, also there are differences between the clock source of different path, cause the waterline (watermark) in the elastic buffer of individual channel different, this is called data crooked (dataskew).The merging of the crooked meeting of data to the data of each path causes difficulty.Thus, need the extra hardware configuration of such as impact damper crooked for the data eliminated between path further.Above-mentioned extra hardware configuration improves design complexities, makes manufacturing cost more high simultaneously.
Summary of the invention
Therefore, in order to solve the problem, the invention provides the method that can prevent impact damper spill-over and the crooked receiver for high-speed serial bus of data and receive data.
According to one embodiment of present invention, a kind of receiver for high-speed serial bus is provided, comprises: demoder, for determining the type of the control data unit received in data; Counter, the multiplicity for the control data unit to particular type counts; Controller, according to the type of the control data unit determined by this demoder, control the multiplicity of this counter to the control data unit of described particular type to count, when this multiplicity reaches reference value, from receiving the control data unit abandoning the described particular type that at least one repeats data; And impact damper, for storing treated reception data.
According to embodiment, when the type of control data unit belongs to idle data unit, this controller can control the multiplicity of control data unit of this counter to the above-mentioned particular type belonging to idle data unit and count.
According to embodiment, described high-speed serial bus can be hypervelocity II (UHS-II) bus, and the control data unit of described particular type can comprise at least one in following link symbol collection (LSS): synchronous (SYN), logical idle (LIDL), data transfer logic free time (DIDL) and direction switch (DIR).
According to embodiment, this receiver may further include register, for arranging described reference value.
According to embodiment, described reference value can be determined by the duration of the control data unit of described particular type.
According to embodiment, described reference value can be 16 to 256.
According to embodiment, this receiver can comprise multiple data path, and each data path can comprise independent counter and impact damper.
According to embodiment, this impact damper can be elastic buffer.
According to embodiment, this receiver can receive this reception data according to the first clock recovered from these reception data, and can export according to second clock these reception data described treated be stored in this impact damper, wherein said reference value can be determined by the difference of described first clock and described second clock.
According to another embodiment of the present invention, a kind of method of the reception data for high-speed serial bus is provided, comprises: the type determining the control data unit received in data; According to the type of control data unit, the multiplicity of the control data unit of particular type is counted, when this multiplicity reaches reference value, from receiving the control data unit abandoning the described particular type that at least one repeats data; And store treated reception data.
According to embodiment, when the type of control data unit belongs to idle data unit, can count the multiplicity of control data unit of the above-mentioned particular type belonging to idle data unit.
According to embodiment, described high-speed serial bus can be hypervelocity II (UHS-II) bus, and the control data unit of described particular type can comprise at least one in following link symbol collection (LSS): synchronous (SYN), logical idle (LIDL), data transfer logic free time (DIDL) and direction switch (DIR).
According to embodiment, the method may further include: arrange described reference value.
According to embodiment, described reference value can be determined by the duration of the control data unit of described particular type.
According to embodiment, described reference value can be 16 to 256.
According to embodiment, this reception data can be received according to the first clock recovered from these reception data, and can export according to second clock these reception data described treated be stored in this impact damper, wherein said reference value can be determined by the difference of described first clock and described second clock.
According to embodiments of the invention, when cross clock domain receives data, by to the control data unit of particular type (such as, idle data unit) multiplicity carry out counting and abandon at least one control data unit repeated, can waterline effectively in controller buffer to prevent buffer full from overflowing without the need to increasing hardware design complexity.In addition, when receiving data by multiple path, can solve further between different path, due to clock frequency difference, the crooked problem of data occurring.
Accompanying drawing explanation
Fig. 1 illustrates according to an embodiment of the invention for the block diagram of the receiver 100 of high-speed serial bus;
Fig. 2 illustrates according to an embodiment of the invention for the process flow diagram of the method for the reception data of high-speed serial bus;
Fig. 3 illustrates according to an embodiment of the invention for the block diagram of the elastic buffer 300 of high-speed serial bus; And
Fig. 4 illustrates according to an embodiment of the invention for the process flow diagram of the method for the elastic buffer of high-speed serial bus.
Embodiment
Describe in detail with reference to the accompanying drawings according to one exemplary embodiment of the present invention.In accompanying drawing, by same or similar Reference numeral imparting mechanism and the substantially identical ingredient of function, and in order to make instructions more simple and clear, the redundancy eliminated about substantially the same ingredient describes.
Hereinafter, by using hypervelocity II (UHS-II) as the example of high-speed serial bus, embodiments of the invention are described.But, the present invention is not limited thereto.The solution of the present invention also can be applied to other high-speed serial bus (such as SATA or the PCIe bus) technology using elastic buffer between different clock-domains.
Fig. 1 illustrates according to an embodiment of the invention for the block diagram of the receiver 100 of high-speed serial bus.
With reference to Fig. 1, receiver 100 can comprise demoder 101, counter 102, controller 103 and impact damper 104.In one embodiment, receiver 100 can be arranged in the Physical layer of main frame or storage card.Receiver 100 receives data from the first clock zone, and exports treated reception data to second clock territory.Such as, the side of receiver 100 produces recovered clock source via clock and data recovery (CDR) from the data received from transmitter (figure does not illustrate), and data-pushing (push) will be received in receiver 100 according to produced recovered clock source, 100 opposite sides of receiver eject (pop) treated reception data to second clock territory, and second clock territory is such as the clock source of main frame or storage card this locality.
Demoder 101 can determine the type of the control data unit in the data received.Such as, in UHS-II, control data unit can be link symbol collection (LLS), comprising: synchronous (SYN), bootstrapping synchronous (BSYN), direction switch (DIR), logical idle (LIDL), data transfer logic free time (DIDL), data burst starts (SDB), data burst terminates (EDB), grouping starts (SOP), grouping terminates (EOP) etc.Each LLS has respective signal pattern, and demoder 101 determines its type by the signal pattern of LLS.Such as, LIDL can comprise two symbols, and first symbol is comma (COM) (K28.5), and second symbol can be the symbol of Stochastic choice from LIDL0 (K28.3) and LIDL1 (D16.7).In UHS-II physical layer specification 4.0, the signal pattern of the various LLS of specified in more detail and effect, repeat no more here.
Counter 102 can count the multiplicity of the control data unit of particular type.According to embodiments of the invention, when the type of control data unit is defined as belonging to idle data unit by demoder 101, controller 103 can control counter 102 pairs of types multiplicity of being confirmed as the control data unit belonging to idle data unit count.In UHS-II, idle data unit can be in following LLS at least one or all: SYN, DIR, LIDL and DIDL.But this is only example, the present invention is not limited thereto.In addition, according to embodiment, also can count the multiplicity of other control data unit except idle data unit.
When this multiplicity reaches reference value, treated reception data from receiving the control data unit abandoning the aforementioned particular type that at least one repeats data, and can be stored in impact damper 104, to provide to second clock territory by controller 103.According to embodiment, impact damper 104 can be elastic buffer.Be dropped owing to only inputting a very little part for particular type control data unit in data, can the waterline of controller buffer 104 effectively, to prevent the spill-over of impact damper 104.In order to avoid affecting command transmitting, can only abandon idle data unit.
In UHS-II, the LLS as such as SYN, DIR, LIDL and DIDL of idle data unit is repeated to send usually in a large number, and the LLS therefore suitably abandoning repetition can not cause the follow-up decoding error to receiving data.The present invention controls to abandon the frequency of repetition LLS according to reference value, makes the waterline of elastic buffer both can not be too high to such an extent as to close to spill-over, also can not be too low to such an extent as to close to becoming empty.For this reason, according to embodiment, receiver 100 may further include register (not shown), for arranging described reference value, for the idle data unit of particular type.In one embodiment, reference value is determined by the duration of idle data unit, especially, is determined by the duration of the shortest idle data unit of duration in idle data unit.Such as, the duration of DIR is the shortest, for N_LSS_DIR*8 (such as, N_LSS_DIR can equal 8), 16 can be set as with reference to value, namely (SYN is comprised whenever receiving 16 idle data unit repeated, DIR, LIDL, with all or part of type of DIDL) time, abandon duration the shortest DIR to be just enough to the waterline of impact damper 104 be maintained reduced levels and can not spill-over, and the follow-up decoding to receiving data can not be affected, the idle data unit so then abandoning an any type just one is established a capital and is enough to the waterline of impact damper 104 is reduced to reduced levels and can not causes decoding error.On the other hand, reference value is also determined by the clock source difference (comprising phase difference and/or frequency difference) in the first clock zone and second clock territory, and the difference of clock source is larger, and described reference value is less, but the impact of clock source difference is less usually.In other embodiments, even can be set as up to 256 by described reference value, that is, every 256 idle data unit repeated just abandon one, are still enough to rapidly waterline is reduced to lower level, and can not cause decoding error.
According to embodiment, receiver 100 can comprise multiple data path, and now, each data path can comprise independent counter 102 and impact damper 104.In a half-duplex mode, idle data unit can be abandoned respectively in each impact damper 104 crooked to eliminate data, make the waterline of the impact damper 104 of individual channel concordant, so that the merging of data.
Fig. 2 illustrates according to an embodiment of the invention for the process flow diagram of the method for the reception data of high-speed serial bus.
With reference to Fig. 2, in step S201, the type of the control data unit received in data can be determined.As mentioned above, in UHS-II, control data unit can be LLS, comprising: SYN, BSYN, DIR, LIDL, DIDL, SDB, EDB, SOP, EOP etc.Its type can be determined by the signal pattern of LLS.
In step S202, if the type of control data unit belongs to the control data unit of particular type, then can count the multiplicity of the control data unit of particular type in step S203, otherwise, enter step S206.As mentioned above, for UHS-II, the control data unit of particular type can comprise at least one or whole in following LSS: SYN, LIDL, DIDL and DIR.But this is example, the present invention is not limited thereto.In addition, according to embodiment, also can count the multiplicity of the control data unit of other particular types except idle data unit.
In step S204, if multiplicity reaches reference value, then can abandon the control data unit (or other control data unit) of the particular type that at least one repeats from reception data in step S205, otherwise, step S203 can be got back to and continue counting.
In step S206, store treated reception data, to provide to second clock territory.
As mentioned above, in order to the waterline in accurately controller buffer, can according to the duration of control data unit (such as, comprising SYN, DIR, LIDL and DIDL) of particular type and the clock source difference in the first clock zone and second clock territory to determine described reference value.Described reference value can be 16 to 256.
In addition, according to embodiment, when by multiple data path transmission, counting and buffer memory can be performed separately to each data path.In a half-duplex mode, idle data unit can be abandoned respectively in each data path crooked to eliminate data, make waterline concordant, so that the merging of data.
Fig. 3 illustrates according to an embodiment of the invention for the block diagram of the elastic buffer 300 of high-speed serial bus.The elastic buffer 300 of Fig. 3 is different from the impact damper 104 of Fig. 1, himself has the function counting idle data unit and abandon.
With reference to Fig. 3, elastic buffer 300 can comprise input interface 301, controller 302, storer 303 and output interface 304.
Controller 302 can to identifying from the idle data unit in the data of the first clock zone of being received by input interface 301, and the multiplicity of the idle data unit recognized is counted, when this multiplicity reaches reference value, abandon at least one idle data unit repeated from receiving data, and treated reception data are stored in storer 303.In one embodiment, storer 303 is a first-in first-out buffer (FIFObuffer).
Output interface 304 can export the reception data processed through above-mentioned controller 302 be stored in storer 303 to second clock territory.
As mentioned above, described high-speed serial bus can be UHS-II bus, and described idle data unit can comprise at least one or whole in following LSS: SYN, LIDL, DIDL and DIR.
In addition, according to embodiment, in order to accurately controlling water level line, elastic buffer 300 may further include register (not shown), for arranging described reference value.Particularly, described reference value can be determined according to the clock source difference in the duration of idle data unit (comprising SYN, DIR, LIDL and DIDL) and/or the first clock zone and second clock territory.Described reference value can be 16 to 256.
Fig. 4 illustrates according to an embodiment of the invention for the process flow diagram of the method for the elastic buffer of high-speed serial bus.
With reference to Fig. 4, in step S401, receive the data from the first clock zone.
In step S402, the idle data unit received in data is identified, and the multiplicity of the idle data unit recognized is counted.For UHS-II bus, described idle data unit can comprise at least one or whole in following LSS: SYN, LIDL, DIDL and DIR.
In step S403, if multiplicity reaches reference value, then abandon at least one idle data unit repeated in step S404 from receiving data, otherwise, step S402 can be got back to and continue counting.
In step S405, store treated reception data.
In step S406, export the treated reception data stored to second clock territory.
According to embodiment, described reference value can be determined according to the clock source difference in the duration of idle data unit and/or the first clock zone and second clock territory.Described reference value can be 16 to 256.
As mentioned above, specifically describing each embodiment of the present invention, but the present invention is not limited thereto.It should be appreciated by those skilled in the art, various amendment, combination, sub-portfolio or replacement can be carried out according to designing requirement or other factors, and they are in the scope of appended claims and equivalent thereof.
Claims (10)
1., for a receiver for high-speed serial bus, comprising:
Demoder, for determining the type of the control data unit received in data;
Counter, the multiplicity for the control data unit to particular type counts;
Controller, according to the type of the described control data unit determined by this demoder, control the multiplicity of this counter to the control data unit of described particular type to count, when this multiplicity reaches reference value, from these reception data, abandon the control data unit of the described particular type that at least one repeats; And
Impact damper, for storing these reception data treated.
2. receiver as claimed in claim 1, wherein, when the type of described control data unit belongs to idle data unit, this controller controls the multiplicity of control data unit of this counter to the above-mentioned particular type belonging to idle data unit and counts.
3. receiver as claimed in claim 1, wherein, described high-speed serial bus is hypervelocity II (UHS-II) bus, and the control data unit of described particular type comprises at least one in following link symbol collection (LSS): synchronous (SYN), logical idle (LIDL), data transfer logic free time (DIDL) and direction switch (DIR).
4. receiver as claimed in claim 1, comprises further:
Register, for arranging described reference value.
5. receiver as claimed in claim 1, wherein, described reference value is determined by the duration of the control data unit of described particular type.
6. receiver as claimed in claim 1, wherein, described reference value is 16 to 256.
7. receiver as claimed in claim 1, comprise multiple data path, each data path comprises independent described counter and described impact damper.
8. receiver as claimed in claim 1, wherein this impact damper is elastic buffer.
9. receiver as claimed in claim 1, wherein this receiver receives this reception data according to the first clock recovered from these reception data, and these reception data described treated be stored in this impact damper are exported according to second clock, wherein said reference value is determined by the difference of described first clock and described second clock.
10., for a method for the reception data of high-speed serial bus, comprising:
Determine the type of the control data unit received in data;
According to the type of described control data unit, the multiplicity of the control data unit of particular type is counted, when this multiplicity reaches reference value, from these reception data, abandon the control data unit of the described particular type that at least one repeats; And
Store these reception data treated.
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| CN201510885448.0A CN105335324B (en) | 2015-12-04 | 2015-12-04 | The method of receiver and reception data for high-speed serial bus |
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| CN201510885448.0A CN105335324B (en) | 2015-12-04 | 2015-12-04 | The method of receiver and reception data for high-speed serial bus |
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| CN102737699A (en) * | 2011-03-31 | 2012-10-17 | 海力士半导体有限公司 | Data output circuit of semiconductor apparatus |
| CN103577373A (en) * | 2012-08-03 | 2014-02-12 | 阿尔特拉公司 | Techniques for aligning and reducing skew in serial data signals |
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2015
- 2015-12-04 CN CN201510885448.0A patent/CN105335324B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20030065987A1 (en) * | 2001-09-28 | 2003-04-03 | Koninklijke Philips Electronics N.V. | Parallel data communication realignment of data sent in multiple groups |
| CN1561619A (en) * | 2001-09-28 | 2005-01-05 | 皇家飞利浦电子股份有限公司 | Parallel data communication having skew intolerant data groups and data validity indicator |
| CN1776656A (en) * | 2005-12-13 | 2006-05-24 | 北京中星微电子有限公司 | Data transmission method between host and USB device and corres ponding USB device |
| CN102737699A (en) * | 2011-03-31 | 2012-10-17 | 海力士半导体有限公司 | Data output circuit of semiconductor apparatus |
| CN103577373A (en) * | 2012-08-03 | 2014-02-12 | 阿尔特拉公司 | Techniques for aligning and reducing skew in serial data signals |
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Address after: Room 301, 2537 Jinke Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee after: Shanghai Zhaoxin Semiconductor Co.,Ltd. Address before: Room 301, 2537 Jinke Road, Zhangjiang hi tech park, Shanghai 201203 Patentee before: VIA ALLIANCE SEMICONDUCTOR Co.,Ltd. |
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