CN105280647A - Thin film transistor array panel and manufacturing method thereof - Google Patents
Thin film transistor array panel and manufacturing method thereof Download PDFInfo
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- CN105280647A CN105280647A CN201510581159.1A CN201510581159A CN105280647A CN 105280647 A CN105280647 A CN 105280647A CN 201510581159 A CN201510581159 A CN 201510581159A CN 105280647 A CN105280647 A CN 105280647A
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Abstract
The invention discloses a thin film transistor array panel and a manufacturing method thereof. The method includes A, forming a first panel; B, performing a first photomask process on a metal layer, a first insulation layer, and a polysilicon layer in the first panel to form a grid; C, removing the part of the first insulation layer in a second area and a third area to expose the part of the polysilicon layer in the second area and the third area; D, performing a second photomask process on a first transparent electrode layer and a second insulation layer on the surfaces of the polysilicon layer and the first metal layer to form a first through hole and a second through hole; E, performing a third photomask process on the first transparent electrode layer and the second metal layer on the first transparent electrode layer to form a source electrode and a drain electrode; and F, performing a fourth photomask process on the second insulation layer, the source electrode, the drain electrode, and the second transparent electrode on the first transparent electrode layer to form a second transparent electrode layer. According to the invention, the manufacturing period of a thin film transistor array substrate is reduced, and the manufacturing procedures can be simplified.
Description
[technical field]
The present invention relates to Display Technique field, particularly a kind of thin-film transistor display panel and preparation method thereof.
[background technology]
Based on LTPS (LowTemperaturePoly-Silicon, low temperature polycrystalline silicon) thin-film transistor of technology is owing to having higher electron mobility, therefore TFT (ThinFilmTransistor can effectively be reduced, thin-film transistor) area of device, improves the aperture opening ratio of pixel cell.
Traditional thin-film transistor array base-plate based on LTPS technology generally has ten layers even structure of more than ten layers, because the manufacture craft more complicated of traditional thin-film transistor array base-plate based on LTPS technology, need more optical cover process, fabrication cycle is also longer simultaneously.
This is unfavorable for the raising of production efficiency, is also unfavorable for the reduction of production cost simultaneously.
Therefore, be necessary to propose a kind of new technical scheme, to solve the problems of the technologies described above.
[summary of the invention]
The object of the present invention is to provide a kind of thin-film transistor display panel and preparation method thereof, it can reduce the manufacturing cycle of thin-film transistor array base-plate, simplifies the manufacturing process of thin-film transistor array base-plate.
For solving the problem, technical scheme of the present invention is as follows:
A kind of manufacture method of thin-film transistor display panel, said method comprising the steps of: A, form the first panel, wherein, described first panel comprises substrate, resilient coating, polysilicon layer, the first insulating barrier and the first metal layer, described first panel comprises first area, second area and the 3rd region, wherein, described first area is between described second area and described 3rd region; B, described the first metal layer, the first insulating barrier and described polysilicon layer in described first panel implement the first optical cover process, and remove in described the first metal layer the part being arranged in described second area and described 3rd region, to form the grid in thin-film transistor; C, remove in described first insulating barrier the part being positioned at described second area and described 3rd region, to expose the part that described polysilicon layer is positioned at described second area and described 3rd region; D, be positioned at described second area and the described surface in the 3rd region and the surface of described the first metal layer at described polysilicon layer and form the second insulating barrier and the first transparent electrode layer, and the second optical cover process is implemented to described first transparent electrode layer and described second insulating barrier, to form the first through hole and the second through hole at described second area and described 3rd region respectively, wherein, described first through hole and described second through hole all make the described polysilicon layer of part appear; E, the second metal level is set on described first transparent electrode layer, and the 3rd optical cover process is implemented to described first transparent electrode layer and described second metal level, to form source electrode in described thin-film transistor and drain electrode in described second metal level, and form the first transparency electrode in described first transparent electrode layer; F, passivation layer and the second transparent electrode layer are set on described second insulating barrier, described source electrode, described drain electrode and described first transparent electrode layer, and the 4th optical cover process is implemented, to form the second transparency electrode to described second transparent electrode layer.
In the manufacture method of above-mentioned thin-film transistor display panel, after described step B, and before described step D, described method is further comprising the steps of: H, plant ion through the part being positioned at described second area and described 3rd region in described first insulating barrier to described polysilicon layer cloth.
In the manufacture method of above-mentioned thin-film transistor display panel, described second area comprises the 4th region and the 5th region, described 3rd region comprises the 6th region and SECTOR-SEVEN territory, wherein, described 4th region is between described first area and described 5th region, and described 6th region is between described first area and described SECTOR-SEVEN territory; Described step H comprises the following steps: P-ion planted by h1, the part cloth being positioned at described 4th region and described 6th region in described polysilicon layer; And P+ ion planted by h2, the part cloth that is positioned at described 5th region and described SECTOR-SEVEN territory in described polysilicon layer.
In the manufacture method of above-mentioned thin-film transistor display panel, at described first insulating barrier after the effect of described first optical cover process, 4th thickness of described first insulating barrier is more than or equal to the 5th thickness of described first insulating barrier, wherein, described 4th thickness is described first insulating barrier at the average thickness at described 4th region or described 6th region place, and described 5th thickness is described first insulating barrier at the average thickness at described 5th region or described SECTOR-SEVEN territory place.
In the manufacture method of above-mentioned thin-film transistor display panel, described first through hole is positioned at described 5th region, and described second through hole is positioned at described SECTOR-SEVEN territory; Described first through hole is through in described polysilicon layer the part being positioned at described 5th region, and described second through hole is through in described polysilicon layer the part being positioned at described SECTOR-SEVEN territory; Described step D comprises: d1, form the second insulating barrier and the first transparent electrode layer on the surface of described polysilicon layer and described the first metal layer; And d2, to described first transparent electrode layer and described second insulating barrier implement described second optical cover process, to form described first through hole and described second through hole in described 5th region and described SECTOR-SEVEN territory respectively.
A kind of thin-film transistor display panel, described thin-film transistor display panel comprises: substrate; Resilient coating; First insulating barrier; Second insulating barrier; First transparent electrode layer; Thin-film transistor, described thin-film transistor comprises: grid, and described grid on described first insulating barrier, arranges the first metal layer to passing through, and implement the first optical cover process to be formed to described the first metal layer; Polysilicon layer, described polysilicon layer is arranged between described resilient coating and described first insulating barrier; Source electrode; And drain electrode; Wherein, described source electrode and described drain electrode are by arranging the second metal level in described first transparency electrode and in the first through hole and the second through hole, and described second metal level enforcement the 3rd optical cover process is formed, described first through hole and described second through hole are by arranging the second insulating barrier and the first transparent electrode layer on the surface of described polysilicon layer and described the first metal layer, and implement the second optical cover process to be formed to described second insulating barrier and described first transparent electrode layer; Passivation layer; Second transparency electrode, described second transparency electrode is by arranging the second transparent electrode layer on described passivation layer, and described second transparent electrode layer enforcement the 4th optical cover process is formed; The first panel be made up of described substrate, described resilient coating, described polysilicon layer, described first insulating barrier and described the first metal layer comprises first area, second area and the 3rd region, wherein, described first area is between described second area and described 3rd region; Described grid is by implementing described first optical cover process to described the first metal layer, and removes described the first metal layer and be positioned at that the part in described second area and described 3rd region formed; Described first through hole and described second through hole lay respectively at described second area and described 3rd region.
In above-mentioned thin-film transistor display panel, the part cloth being positioned at described second area and described 3rd region in described polysilicon layer is implanted with ion.
In above-mentioned thin-film transistor display panel, described second area comprises the 4th region and the 5th region, described 3rd region comprises the 6th region and SECTOR-SEVEN territory, wherein, described 4th region is between described first area and described 5th region, and described 6th region is between described first area and described SECTOR-SEVEN territory; The part cloth being positioned at described 4th region and described 6th region in described polysilicon layer is implanted with P-ion; The part cloth being positioned at described 5th region and described SECTOR-SEVEN territory in described polysilicon layer is implanted with P+ ion.
In above-mentioned thin-film transistor display panel, at described first insulating barrier after the effect of described first optical cover process, 4th thickness of described first insulating barrier is more than or equal to the 5th thickness of described first insulating barrier, wherein, described 4th thickness is described first insulating barrier at the average thickness at described 4th region or described 6th region place, and described 5th thickness is described first insulating barrier at the average thickness at described 5th region or described SECTOR-SEVEN territory place.
In above-mentioned thin-film transistor display panel, described first through hole is positioned at described 5th region, and described second through hole is positioned at described SECTOR-SEVEN territory; Described first through hole is through in described polysilicon layer the part being positioned at described 5th region, and described second through hole is through in described polysilicon layer the part being positioned at described SECTOR-SEVEN territory.
Hinge structure, the present invention only utilizes four road optical cover process namely to can be made into thin-film transistor array base-plate based on LTPS technology, effectively reduce the manufacturing cycle of thin-film transistor array base-plate, simplify the manufacturing process of thin-film transistor array base-plate, reduce the production cost of thin-film transistor array base-plate.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, be described in detail below.
[accompanying drawing explanation]
Fig. 1 to Fig. 7 is the schematic diagram of the manufacture method of thin-film transistor display panel of the present invention;
Fig. 8 is the flow chart of the first embodiment of the manufacture method of thin-film transistor display panel of the present invention;
Fig. 9 is the flow chart of the second embodiment of the manufacture method of thin-film transistor display panel of the present invention;
Figure 10 is the flow chart of the 3rd embodiment of the manufacture method of thin-film transistor display panel of the present invention;
Figure 11 is the flow chart of the step forming the first panel in the manufacture method of thin-film transistor display panel of the present invention.
[embodiment]
The word " embodiment " that this specification uses means example, example or illustration.In addition, the article " " used in this specification and claims usually can be interpreted as " one or more ", can know unless otherwise or from context and determine singulative.
Thin-film transistor array base-plate of the present invention is the thin-film transistor array base-plate based on LTPS (LowTemperaturePoly-Silicon, low temperature polycrystalline silicon) technology.
Referring to figs. 1 to Fig. 8, wherein, Fig. 1 to Fig. 7 is the schematic diagram of the manufacture method of thin-film transistor display panel of the present invention, is the flow chart of the first embodiment of the manufacture method of thin-film transistor display panel of the present invention with reference to figure 8, Fig. 8.
The manufacture method of the thin-film transistor display panel of the present embodiment comprises the following steps:
A (step 801), form the first panel, wherein, described first panel comprises substrate 101, resilient coating 102, polysilicon layer 103, first insulating barrier 104 and the first metal layer 105, described first panel comprises first area 107, second area 108 and the 3rd region 109, wherein, described first area 107 is between described second area 108 and described 3rd region 109.
B (step 802), the first optical cover process is implemented to described the first metal layer 105, first insulating barrier 104 in described first panel and described polysilicon layer 103, and remove in described the first metal layer 105 part being arranged in described second area 108 and described 3rd region 109, to form the grid in thin-film transistor.Described thin-film transistor is PMOS (PositivechannelMetalOxideSemiconductor, P-channel metal-oxide-semiconductor) transistor.
C (step 803), remove the part being positioned at described second area 108 and described 3rd region 109 in described first insulating barrier 104, to expose the part that described polysilicon layer 103 is positioned at described second area 108 and described 3rd region 109.
D (step 804), be positioned at described second area 108 and the described surface in the 3rd region 109 and the surface of described the first metal layer 105 at described polysilicon layer 103 and form the second insulating barrier 401 and the first transparent electrode layer 402, and the second optical cover process is implemented to described first transparent electrode layer 402 and described second insulating barrier 401, to form the first through hole 403 and the second through hole 404 at described second area 108 and described 3rd region 109 respectively, wherein, described first through hole 403 and described second through hole 404 all make the described polysilicon layer 103 of part appear.
E (step 805), the second metal level 501 is set on described first transparent electrode layer 402, and the 3rd optical cover process is implemented to described first transparent electrode layer 402 and described second metal level 501, to form source electrode in described thin-film transistor 601 and drain electrode 602 in described second metal level 501.
F (step 806), passivation layer 701 and the second transparent electrode layer 702 are set on described second insulating barrier 401, described source electrode 601, described drain electrode 602 and described first transparent electrode layer 402, and the 4th optical cover process is implemented, to form the second transparency electrode to described second transparent electrode layer 702.
In technique scheme, comprise described substrate 101 owing to first being formed, described resilient coating 102, described polysilicon layer 103, described first panel of described first insulating barrier 104 and described first signal line layer, is then carrying out optical cover process (described first optical cover process to described first panel, described second optical cover process, described 3rd optical cover process and described 4th optical cover process), and described source electrode 601 is set on described first panel simultaneously, described drain electrode 602, described transparency electrode etc., and then form described thin-film transistor array base-plate, therefore, in relative conventional solution, form described resilient coating 102 successively, described polysilicon layer 103, described first insulating barrier 104 and described first signal line layer, described second insulating barrier 401, described secondary signal line layer, described transparent electrode layer (described first transparent electrode layer 402, described second transparent electrode layer 702) step, technique scheme can only utilize four road optical cover process namely to can be made into thin-film transistor array base-plate based on LTPS technology, effectively reduce the manufacturing cycle of thin-film transistor array base-plate, simplify the manufacturing process of thin-film transistor array base-plate, reduce the production cost of thin-film transistor array base-plate.
In the present embodiment, after described step B, and before described step D, described method is further comprising the steps of:
H, plant ion through the part being positioned at described second area 108 and described 3rd region 109 in described first insulating barrier 104 to described polysilicon layer 103 cloth.
In the present embodiment, described second area 108 comprises the 4th region 201 and the 5th region 202, described 3rd region 109 comprises the 6th region 203 and SECTOR-SEVEN territory 204, wherein, described 4th region 201 is between described first area 107 and described 5th region 202, and described 6th region 203 is between described first area 107 and described SECTOR-SEVEN territory 204.
Described step H comprises the following steps:
P-ion planted by h1, the part cloth being positioned at described 4th region 201 and described 6th region 203 in described polysilicon layer 103.
P+ ion planted by h2, the part cloth being positioned at described 5th region 202 and described SECTOR-SEVEN territory 204 in described polysilicon layer 103.
Now, the part being positioned at described 4th region 201 and described 6th region 203 in described polysilicon layer 103 forms P-structure, and the part being positioned at described 5th region 202 and described SECTOR-SEVEN territory 204 in described polysilicon layer 103 forms P+ structure.
In the present embodiment, at described first insulating barrier 104 after the effect of described first optical cover process, 4th thickness of described first insulating barrier 104 is more than or equal to the 5th thickness of described first insulating barrier 104, wherein, described 4th thickness is described first insulating barrier 104 at the average thickness at described 4th region 201 or described 6th region 203 place, and described 5th thickness is described first insulating barrier 104 at the average thickness at described 5th region 202 or described SECTOR-SEVEN territory 204 place.
In the present embodiment, corresponding described 5th region 202 of described first through hole 403, the described second corresponding described SECTOR-SEVEN territory 204 of through hole 404.
Described first through hole 403 is through in described polysilicon layer 103 part being positioned at described 5th region 202, and described second through hole 404 is through to the part being positioned at described SECTOR-SEVEN territory 204 in described polysilicon layer 103.
Described step D comprises:
D1, form the second insulating barrier 401 and the first transparent electrode layer 402 on the surface of described polysilicon layer 103 and described the first metal layer 105.
D2, described second optical cover process is implemented to described first transparent electrode layer 402 and described second insulating barrier 401, to form described first through hole 403 and described second through hole 404 in described 5th region 202 and described SECTOR-SEVEN territory 204 respectively.
It is the flow chart of the second embodiment of the manufacture method of thin-film transistor display panel of the present invention with reference to figure 9, Fig. 9.The present embodiment is similar to above-mentioned first embodiment, and difference is:
Before described first optical cover process of enforcement, described method is further comprising the steps of:
I (step 901), the first photoresist layer 106 is set on described first panel.
Wherein, in described first photoresist layer 106, the position corresponding with described first area 107 has the first thickness, have the second thickness with the position in described second area 108 and described 3rd region 109 in described first photoresist layer 106, described first thickness is greater than described second thickness.
With reference to the flow chart that Figure 10, Figure 10 are the 3rd embodiment of the manufacture method of thin-film transistor display panel of the present invention.The present embodiment is similar to above-mentioned first embodiment or the second embodiment, and difference is:
In the present embodiment, described step e comprises the following steps:
E1 (step 1001), the second metal level 501 is set on described first transparent electrode layer 402, and the second photoresist layer 502 is set on described second metal level 501;
E2 (step 1002), the 3rd optical cover process is implemented to described first transparent electrode layer 402 and described second metal level 501, to form source electrode in described thin-film transistor 601 and drain electrode 602 in described second metal level 501, and form the first transparency electrode in described first transparent electrode layer 402.
Wherein, described second photoresist layer 502 comprises the first branch 5021 and the second branch 5022, described first branch 5021 is arranged at described second area 108, described second branch 5022 is arranged at described 3rd region 109, described first branch 5021 hides the region at described first through hole 403 place, and described second branch 5022 hides the region at described second through hole 404 place.
With reference to the flow chart that Figure 11, Figure 11 are the step forming the first panel in the manufacture method of thin-film transistor display panel of the present invention.
In the present embodiment, described steps A (that is, described step 801) comprises the following steps:
A1 (step 1101), on described substrate 101, form described resilient coating 102.
A2 (step 1102), on described resilient coating 102, form described polysilicon layer 103.
A3 (step 1103), on described polysilicon layer 103, form described first insulating barrier 104.
A4 (step 1104), on described first insulating barrier 104, form described the first metal layer 105.
When described thin-film transistor array base-plate comprises described color rete, the manufacture method of described thin-film transistor display panel comprises the following steps:
Described thin-film transistor array base-plate arranges described color rete.
With reference to the schematic diagram that figure 7, Fig. 7 is thin-film transistor display panel of the present invention.
In the present embodiment, described thin-film transistor display panel comprises substrate 101, resilient coating 102, first insulating barrier 104, second insulating barrier 401, first transparent electrode layer 402, thin-film transistor, passivation layer 701 and the second transparency electrode.
Described thin-film transistor comprises grid, polysilicon layer 103, source electrode 601 and drain electrode 602.Described thin-film transistor is PMOS (PositivechannelMetalOxideSemiconductor, P-channel metal-oxide-semiconductor) transistor.
Described grid on described first insulating barrier 104, arranges described the first metal layer 105 to passing through, and implement the first optical cover process to be formed to described the first metal layer 105.
Described polysilicon layer 103 is arranged between described resilient coating 102 and described first insulating barrier 104.
Wherein, described source electrode 601 and described drain electrode 602 are by arranging the second metal level 501 in described first transparency electrode and in the first through hole 403 and the second through hole 404, and described second metal level 501 is implemented to the 3rd optical cover process formed, described first through hole 403 and described second through hole 404 are by arranging described second insulating barrier 401 and described first transparent electrode layer 402 on the surface of described polysilicon layer 103 and described the first metal layer 105, and implement the second optical cover process to be formed to described second insulating barrier 401 and described first transparent electrode layer 402.
Described second transparency electrode is by arranging described second transparent electrode layer 702 on described passivation layer 701, and described second transparent electrode layer 702 is implemented to the 4th optical cover process formed.
The first panel be made up of described substrate 101, described resilient coating 102, described polysilicon layer 103, described first insulating barrier 104 and described the first metal layer 105 comprises first area 107, second area 108 and the 3rd region 109, wherein, described first area 107 is between described second area 108 and described 3rd region 109.
Described grid is by implementing described first optical cover process to described the first metal layer 105, and removes described the first metal layer 105 and be positioned at that the part in described second area 108 and described 3rd region 109 formed.
Described first through hole 403 and described second through hole 404 lay respectively at described second area 108 and described 3rd region 109.
In the present embodiment, the part cloth being positioned at described second area 108 and described 3rd region 109 in described polysilicon layer 103 is implanted with ion.
In the present embodiment, described second area 108 comprises the 4th region 201 and the 5th region 202, described 3rd region 109 comprises the 6th region 203 and SECTOR-SEVEN territory 204, wherein, described 4th region 201 is between described first area 107 and described 5th region 202, and described 6th region 203 is between described first area 107 and described SECTOR-SEVEN territory 204.
The part cloth being positioned at described 4th region 201 and described 6th region 203 in described polysilicon layer 103 is implanted with P-ion.
The part cloth being positioned at described 5th region 202 and described SECTOR-SEVEN territory 204 in described polysilicon layer 103 is implanted with P+ ion.
Now, the part being positioned at described 4th region 201 and described 6th region 203 in described polysilicon layer 103 forms P-structure, and the part being positioned at described 5th region 202 and described SECTOR-SEVEN territory 204 in described polysilicon layer 103 forms P+ structure.
In the present embodiment, at described first insulating barrier 104 after the effect of described first optical cover process, 4th thickness of described first insulating barrier 104 is more than or equal to the 5th thickness of described first insulating barrier 104, wherein, described 4th thickness is described first insulating barrier 104 at the average thickness at described 4th region 201 or described 6th region 203 place, and described 5th thickness is described first insulating barrier 104 at the average thickness at described 5th region 202 or described SECTOR-SEVEN territory 204 place.
In the present embodiment, described first through hole 403 is positioned at described 5th region 202, and described second through hole 404 is positioned at described SECTOR-SEVEN territory 204.
Described first through hole 403 is through in described polysilicon layer 103 part being positioned at described 5th region 202, and described second through hole 404 is through to the part being positioned at described SECTOR-SEVEN territory 204 in described polysilicon layer 103.
In the present invention, described substrate 101 is comprised owing to first being formed, described resilient coating 102, described polysilicon layer 103, described first panel of described first insulating barrier 104 and described first signal line layer, is then carrying out optical cover process (described first optical cover process to described first panel, described second optical cover process, described 3rd optical cover process and described 4th optical cover process), and described source electrode 601 is set on described first panel simultaneously, described drain electrode 602, transparency electrode etc., and then form described thin-film transistor array base-plate, therefore, in relative conventional solution, form described resilient coating 102 successively, described polysilicon layer 103, described first insulating barrier 104 and described first signal line layer, described second insulating barrier 401, described secondary signal line layer, described transparent electrode layer (the first transparent electrode layer 402, second transparent electrode layer 702), above-mentioned thin-film transistor array base-plate can only utilize four road optical cover process namely to can be made into, effectively reduce the manufacturing cycle of thin-film transistor array base-plate, simplify the manufacturing process of thin-film transistor array base-plate, reduce the production cost of thin-film transistor array base-plate.
Although illustrate and describe the present invention relative to one or more implementation, those skilled in the art are based on to the reading of this specification and accompanying drawing with understand and will expect equivalent variations and amendment.The present invention includes all such amendments and modification, and only limited by the scope of claims.Especially about the various functions performed by said modules, term for describing such assembly is intended to the random component (unless otherwise instructed) corresponding to the appointed function (such as it is functionally of equal value) performing described assembly, even if be not structurally equal to the open structure of the function in the exemplary implementations performing shown in this article specification.In addition, although the special characteristic of this specification relative in some implementations only one be disclosed, this feature can with can be such as expect and other Feature Combinations one or more of other favourable implementations for given or application-specific.And, " comprise " with regard to term, " having ", " containing " or its distortion be used in embodiment or claim with regard to, such term is intended to comprise " to comprise " similar mode to term.
In sum; although the present invention discloses as above with preferred embodiment; but above preferred embodiment is also not used to limit the present invention; those of ordinary skill in the art; without departing from the spirit and scope of the present invention; all can do various change and retouching, the scope that therefore protection scope of the present invention defines with claim is as the criterion.
Claims (10)
1. a manufacture method for thin-film transistor display panel, is characterized in that, said method comprising the steps of:
A, form the first panel, wherein, described first panel comprises substrate, resilient coating, polysilicon layer, the first insulating barrier and the first metal layer, described first panel comprises first area, second area and the 3rd region, wherein, described first area is between described second area and described 3rd region;
B, described the first metal layer, the first insulating barrier and described polysilicon layer in described first panel implement the first optical cover process, and remove in described the first metal layer the part being arranged in described second area and described 3rd region, to form the grid in thin-film transistor;
C, remove in described first insulating barrier the part being positioned at described second area and described 3rd region, to expose the part that described polysilicon layer is positioned at described second area and described 3rd region;
D, be positioned at described second area and the described surface in the 3rd region and the surface of described the first metal layer at described polysilicon layer and form the second insulating barrier and the first transparent electrode layer, and the second optical cover process is implemented to described first transparent electrode layer and described second insulating barrier, to form the first through hole and the second through hole at described second area and described 3rd region respectively, wherein, described first through hole and described second through hole all make the described polysilicon layer of part appear;
E, the second metal level is set on described first transparent electrode layer, and the 3rd optical cover process is implemented to described first transparent electrode layer and described second metal level, to form source electrode in described thin-film transistor and drain electrode in described second metal level, and form the first transparency electrode in described first transparent electrode layer;
F, passivation layer and the second transparent electrode layer are set on described second insulating barrier, described source electrode, described drain electrode and described first transparent electrode layer, and the 4th optical cover process is implemented, to form the second transparency electrode to described second transparent electrode layer.
2. the manufacture method of thin-film transistor display panel according to claim 1, is characterized in that, after described step B, and before described step D, described method is further comprising the steps of:
H, plant ion through the part being positioned at described second area and described 3rd region in described first insulating barrier to described polysilicon layer cloth.
3. the manufacture method of thin-film transistor display panel according to claim 2, it is characterized in that, described second area comprises the 4th region and the 5th region, described 3rd region comprises the 6th region and SECTOR-SEVEN territory, wherein, described 4th region is between described first area and described 5th region, and described 6th region is between described first area and described SECTOR-SEVEN territory;
Described step H comprises the following steps:
P-ion planted by h1, the part cloth being positioned at described 4th region and described 6th region in described polysilicon layer; And
P+ ion planted by h2, the part cloth being positioned at described 5th region and described SECTOR-SEVEN territory in described polysilicon layer.
4. the manufacture method of thin-film transistor display panel according to claim 3, it is characterized in that, at described first insulating barrier after the effect of described first optical cover process, 4th thickness of described first insulating barrier is more than or equal to the 5th thickness of described first insulating barrier, wherein, described 4th thickness is described first insulating barrier at the average thickness at described 4th region or described 6th region place, and described 5th thickness is described first insulating barrier at the average thickness at described 5th region or described SECTOR-SEVEN territory place.
5. the manufacture method of thin-film transistor display panel according to claim 1, is characterized in that, described first through hole is positioned at described 5th region, and described second through hole is positioned at described SECTOR-SEVEN territory;
Described first through hole is through in described polysilicon layer the part being positioned at described 5th region, and described second through hole is through in described polysilicon layer the part being positioned at described SECTOR-SEVEN territory;
Described step D comprises:
D1, form the second insulating barrier and the first transparent electrode layer on the surface of described polysilicon layer and described the first metal layer; And
D2, to described first transparent electrode layer and described second insulating barrier implement described second optical cover process, to form described first through hole and described second through hole in described 5th region and described SECTOR-SEVEN territory respectively.
6. a thin-film transistor display panel, is characterized in that, described thin-film transistor display panel comprises:
Substrate;
Resilient coating;
First insulating barrier;
Second insulating barrier;
First transparent electrode layer;
Thin-film transistor, described thin-film transistor comprises:
Grid, described grid on described first insulating barrier, arranges the first metal layer to passing through, and implement the first optical cover process to be formed to described the first metal layer;
Polysilicon layer, described polysilicon layer is arranged between described resilient coating and described first insulating barrier;
Source electrode; And
Drain electrode;
Wherein, described source electrode and described drain electrode are by arranging the second metal level in described first transparency electrode and in the first through hole and the second through hole, and described second metal level enforcement the 3rd optical cover process is formed, described first through hole and described second through hole are by arranging the second insulating barrier and the first transparent electrode layer on the surface of described polysilicon layer and described the first metal layer, and implement the second optical cover process to be formed to described second insulating barrier and described first transparent electrode layer;
Passivation layer;
Second transparency electrode, described second transparency electrode is by arranging the second transparent electrode layer on described passivation layer, and described second transparent electrode layer enforcement the 4th optical cover process is formed;
The first panel be made up of described substrate, described resilient coating, described polysilicon layer, described first insulating barrier and described the first metal layer comprises first area, second area and the 3rd region, wherein, described first area is between described second area and described 3rd region;
Described grid is by implementing described first optical cover process to described the first metal layer, and removes described the first metal layer and be positioned at that the part in described second area and described 3rd region formed;
Described first through hole and described second through hole lay respectively at described second area and described 3rd region.
7. thin-film transistor display panel according to claim 6, is characterized in that, the part cloth being positioned at described second area and described 3rd region in described polysilicon layer is implanted with ion.
8. thin-film transistor display panel according to claim 7, it is characterized in that, described second area comprises the 4th region and the 5th region, described 3rd region comprises the 6th region and SECTOR-SEVEN territory, wherein, described 4th region is between described first area and described 5th region, and described 6th region is between described first area and described SECTOR-SEVEN territory;
The part cloth being positioned at described 4th region and described 6th region in described polysilicon layer is implanted with P-ion;
The part cloth being positioned at described 5th region and described SECTOR-SEVEN territory in described polysilicon layer is implanted with P+ ion.
9. thin-film transistor display panel according to claim 8, it is characterized in that, at described first insulating barrier after the effect of described first optical cover process, 4th thickness of described first insulating barrier is more than or equal to the 5th thickness of described first insulating barrier, wherein, described 4th thickness is described first insulating barrier at the average thickness at described 4th region or described 6th region place, and described 5th thickness is described first insulating barrier at the average thickness at described 5th region or described SECTOR-SEVEN territory place.
10. thin-film transistor display panel according to claim 6, is characterized in that, described first through hole is positioned at described 5th region, and described second through hole is positioned at described SECTOR-SEVEN territory;
Described first through hole is through in described polysilicon layer the part being positioned at described 5th region, and described second through hole is through in described polysilicon layer the part being positioned at described SECTOR-SEVEN territory.
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Application publication date: 20160127 |