CN105278913A - Device for realizing base-2 exponential or logarithmic computation of vector floating point - Google Patents
Device for realizing base-2 exponential or logarithmic computation of vector floating point Download PDFInfo
- Publication number
- CN105278913A CN105278913A CN201510019196.3A CN201510019196A CN105278913A CN 105278913 A CN105278913 A CN 105278913A CN 201510019196 A CN201510019196 A CN 201510019196A CN 105278913 A CN105278913 A CN 105278913A
- Authority
- CN
- China
- Prior art keywords
- floating
- point
- data
- vector
- calculating unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Complex Calculations (AREA)
Abstract
The invention provides a device for realizing base-2 exponential or logarithmic computation of a vector floating point. The device comprises a vector register group, a group of data selectors of a floating point number, a group of floating point transcendental function computing units and a control logic unit, wherein the vector register group comprises at least one vector register, wherein a plurality of floating point data can be stored in each vector register; each data selector of the floating point number is used for sending data read from each vector register to the corresponding floating point transcendental function computing unit after changing the order; each floating point transcendental function computing unit is used for carrying out single-precision floating point transcendental function computation and base-2 exponential or logarithmic computation of the floating point, wherein the number of the floating point transcendental function computing units is equal to the number of the floating point data in the vector registers; and the control logic unit is used for controlling data selection of one group of data selectors and operating function selection of the floating point transcendental function computing units. According to the device, the parallel computing property of vector data is utilized, computation of a plurality of floating point data can be simultaneously carried out, the computing speed is accelerated, and the execution cycle is reduced.
Description
Technical field
The present invention relates to micro-processor architecture technical field, particularly a kind of device of witness vector floating-point basis 2 index Logarithmic calculation.
Background technology
Along with the fast development of digital communication technology, also more and more higher to the requirement of digital signal processing capability, therefore need constantly to promote digital signal processing capability.And traditional compute mode adopts Scalar operation unit, arithmetic speed is slow, and the performance period is long, to digital signal processing inefficiency.
Summary of the invention
The present invention is intended to solve one of technical matters in above-mentioned correlation technique at least to a certain extent.
For this reason, the object of the invention is to the device proposing a kind of witness vector floating-point basis 2 index Logarithmic calculation, this device make use of the parallel computation characteristic of vector data, the calculating of multiple floating data can be carried out simultaneously, the Scalar operation unit of comparing traditional, accelerate arithmetic speed, decrease the performance period.
To achieve these goals, embodiments of the invention propose a kind of device of witness vector floating-point basis 2 index Logarithmic calculation, and comprise vector registor group, comprise at least one vector registor, wherein, multiple floating data preserved by each vector registor; The data selector of one group of floating number, the data change order for reading from described vector registor is rear sends into Floating-point transcendental function calculating unit; One group of Floating-point transcendental function calculating unit, for carrying out the Floating-point transcendental functional operation of single precision, and carrying out floating-point exponent or the logarithm operation of base 2, the number of described Floating-point transcendental function calculating unit is equal with the number of the floating data in described vector registor; And steering logic unit, for controlling the data selection of described one group of data selector, and the operating function controlling described Floating-point transcendental function calculating unit is selected.
According to the device of the witness vector floating-point basis 2 index Logarithmic calculation of the embodiment of the present invention, sense data from the vector registor preserving floating-point complex, send in data selector, the data permutation that vector is inner is delivered to Floating-point transcendental function calculating unit by data selector, Floating-point transcendental function calculating unit carries out base 2 index Logarithmic calculation according to the result of data selector, and the output of performance element preserved by last vector registor.Therefore, this device make use of the parallel computation characteristic of vector data, and can carry out the calculating of multiple floating data, the Scalar operation unit of comparing traditional, accelerates arithmetic speed, decrease the performance period simultaneously.
In addition, the device of witness vector floating-point basis 2 index Logarithmic calculation according to the above embodiment of the present invention can also have following additional technical characteristic:
In some instances, described vector registor group comprises multiple vector registor, and each vector registor can comprise the floating data of multiple single precision.
In some instances, described floating data is single-precision floating-point data.
In some instances, described steering logic unit is for the annexation of the input port of the data selection passage and Floating-point transcendental function calculating unit of determining described data selector, and Floating-point transcendental function calculating unit mode of operation.
In some instances, the structure of each Floating-point transcendental function calculating unit is identical, all adopts floating-point cordic algorithm realization to calculate.
In some instances, each described Floating-point transcendental function calculating unit completes the index Logarithmic calculation of the single precision floating datum of 1 32.
In some instances, described steering logic unit is for performing following steps: (1) reads one group of data from the described vector registor group of preserving floating number, and each register comprises multiple floating number; (2) by described data selector, each floating number is extracted respectively, different floating number is delivered to each Floating-point transcendental function calculating unit; (3) described Floating-point transcendental function calculating unit carries out single precision floating datum computing according to action type; (4) operation result of Floating-point transcendental function calculating unit described in each is saved in a vector registor.
Additional aspect of the present invention and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage will become obvious and easy understand from accompanying drawing below combining to the description of embodiment, wherein:
Fig. 1 is the structured flowchart of the device of witness vector floating-point basis 2 index Logarithmic calculation according to an embodiment of the invention;
Fig. 2 is the calculation function block diagram of the device of witness vector floating-point basis 2 index Logarithmic calculation in accordance with another embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
Below in conjunction with accompanying drawing, the device according to the witness vector floating-point basis 2 index Logarithmic calculation of the embodiment of the present invention is described.
Fig. 1 is the structured flowchart of the device of witness vector floating-point basis 2 index Logarithmic calculation according to an embodiment of the invention.As shown in Figure 1, this device 100 comprises: data selector 120, one group of Floating-point transcendental function calculating unit 130 of vector registor group 110, one group of floating number and steering logic unit 140.
Particularly, vector registor group 110 comprises at least one vector registor, and wherein, multiple floating data preserved by each vector registor.Wherein, in one embodiment of the invention, floating data is such as single-precision floating-point data or double-precision floating point data.More specifically, in this example, such as vector registor group 110 comprises multiple vector registor, and each vector registor can comprise the floating data of multiple single precision.Further, floating data is kept in same register, and their reading is carried out simultaneously, also can be successively to read.And for the write of result, can in same register, also can in different registers.
The data change order rear feeding Floating-point transcendental function calculating unit 130 of data selector 120 for reading from vector registor of one group of floating number.
One group of Floating-point transcendental function calculating unit 130 for carrying out the Floating-point transcendental functional operation of single precision, and carries out floating-point exponent or the logarithm operation of base 2, and the number of Floating-point transcendental function calculating unit 130 is equal with the number of the floating data in vector registor.In some instances, such as, the structure of each Floating-point transcendental function calculating unit 130 is identical, all adopts floating-point cordic algorithm realization, such as, shown in Fig. 2.More specifically, each Floating-point transcendental function calculating unit 130 completes the index Logarithmic calculation of the single precision floating datum of 1 32.
Steering logic unit 140 is for controlling the data selection of one group of data selector, and the operating function controlling Floating-point transcendental function calculating unit 130 is selected.More specifically, in some instances, steering logic unit 140 is for the annexation of the input port of the data selection passage and Floating-point transcendental function calculating unit 130 of determining data selector 120, and the mode of operation of Floating-point transcendental function calculating unit 130.
In one embodiment of the invention, specifically, steering logic unit 140 is mainly used in performing following steps:
Step 1: read one group of data from the vector registor group 110 of preserving floating number, each vector registor comprises multiple floating number.Also be the service data preparatory stage, such as, from a vector registor, take out one group of data.
Step 2: each floating number extracted respectively by data selector 120, delivers to each Floating-point transcendental function calculating unit 130 by different floating number.Also be the service data choice phase, such as, according to the arithmetic operation instruction received, in units of 32, composition is sent to the operand of Floating-point transcendental function calculating unit 130.
Step 3: Floating-point transcendental function calculating unit 130 carries out single precision floating datum computing according to action type (exponential function/logarithmic function).Wherein, multiple single precision floating datum is had to carry out arithmetic operation at the same time.Also namely according to the operate coding sent into, corresponding cordic calculating is carried out to 32 single precision floating datums.
Step 4: the operation result of each Floating-point transcendental function calculating unit 130 is saved in a vector registor.In other words, 32 single precision floating datums obtained by each Floating-point transcendental function calculating unit 130 are combined into vector data, write back in vector registor.
Wherein, for above-mentioned Floating-point transcendental function calculating unit 130, when vector registor group 120 is 256 bit wide, the computing of Floating-point transcendental function calculating unit 130 executed in parallel 8 single precision floating datums.
As example particularly, describe the device 100 of the witness vector floating-point basis 2 index Logarithmic calculation of the above embodiment of the present invention in detail below in conjunction with Fig. 2.
As shown in Figure 2, for the operating processes that operand is the computing of 256 detailed description floating number vector basis 2 exponential functions, specifically comprise: the vector floating-point logarithmic data obtaining 256 from vector registor, computing module is made up of the Floating-point transcendental function calculating unit of 8 32.Also namely, through the data selector of floating number the source operand of each 32 that choose delivered in corresponding Floating-point transcendental function calculating unit and go.Steering logic unit, according to the operation information sent into, provides the control signal of each Floating-point transcendental function calculating unit.Then Floating-point transcendental function calculating unit does corresponding operation according to control signal to operand, and the operation result of each Floating-point transcendental function calculating unit is combined into 256 outputs.
Following as an example particularly, 256 single-precision floating point base 2 exponential function computing computation processes are described.Assuming that the floating number will carried out in a vector registor of exponential function computing is respectively x7, x6, x5, x4, x3, x2, x1, x0.Needed single-precision floating point base 2 exponential function arithmetic operation assuming that current, its operating result is y7, y6, y5, y4, y3, y2, y1, y0, and its arithmetic operation is y [n]=2^ (x [n]), then perform following steps:
Step 10: vector index functional operation operation is sent in steering logic unit, the data selection control signal of generating data path, generates the operating control signal of Floating-point transcendental function calculating unit simultaneously.
Step 20: the data selector of floating number is delivered in corresponding Floating-point transcendental function calculating unit according to the source data that the single precision operation signal sent into chooses each 32 and gone.
Step 30: the control signal that the function operation that Floating-point transcendental function calculating unit is sent into according to steering logic unit etc. are relevant, completes the exponential function computing to operand.Particularly, such as:
The operand of first Floating-point transcendental function calculating unit is x0, and steering order signal is that exponential function calculates;
The operand of second Floating-point transcendental function calculating unit is x1, and steering order signal is that exponential function calculates;
The operand of the 3rd Floating-point transcendental function calculating unit is x2, and steering order signal is that exponential function calculates;
The operand of the 4th Floating-point transcendental function calculating unit is x3, and steering order signal is that exponential function calculates;
The operand of the 5th Floating-point transcendental function calculating unit is x4, and steering order signal is that exponential function calculates;
The operand of the 6th Floating-point transcendental function calculating unit is x5, and steering order signal is that exponential function calculates;
The operand of the 7th Floating-point transcendental function calculating unit is x6, and steering order signal is that exponential function calculates;
The operand of the 8th Floating-point transcendental function calculating unit is x7, and steering order signal is that exponential function calculates.
Step 40: finally 32 Output rusults of above-mentioned eight Floating-point transcendental function calculating unit are combined into 256 bit vector data, and write back in vector registor.
As another concrete example, 256 single-precision floating point base 2 logarithmic function computing computation processes are described.Assuming that the floating number will carried out in a vector registor of logarithmic function computing is respectively x7, x6, x5, x4, x3, x2, x1, x0.Needed single-precision floating point base 2 logarithmic function arithmetic operation assuming that current, its operating result is y7, y6, y5, y4, y3, y2, y1, y0, and its arithmetic operation is y [n]=log2 (x [n]), then perform following steps:
Step 100: be sent in steering logic unit by vectorial logarithmic function arithmetic operation, the data selection control signal of generating data path, generates the operating control signal of Floating-point transcendental function calculating unit simultaneously.
Step 200: the data selector of floating number is delivered in corresponding Floating-point transcendental function calculating unit according to the source data that the single precision operation signal sent into chooses each 32 and gone.
Step 300: the control signal that the function operation that Floating-point transcendental function calculating unit is sent into according to steering logic unit etc. are relevant, completes the logarithmic function computing to operand.Particularly, such as:
The operand of first Floating-point transcendental function calculating unit is x0, and steering order signal is that logarithmic function calculates;
The operand of second Floating-point transcendental function calculating unit is x1, and steering order signal is that logarithmic function calculates;
The operand of the 3rd Floating-point transcendental function calculating unit is x2, and steering order signal is that logarithmic function calculates;
The operand of the 4th Floating-point transcendental function calculating unit is x3, and steering order signal is that logarithmic function calculates;
The operand of the 5th Floating-point transcendental function calculating unit is x4, and steering order signal is that logarithmic function calculates;
The operand of the 6th Floating-point transcendental function calculating unit is x5, and steering order signal is that logarithmic function calculates;
The operand of the 7th Floating-point transcendental function calculating unit is x6, and steering order signal is that logarithmic function calculates;
The operand of the 8th Floating-point transcendental function calculating unit is x7, and steering order signal is that logarithmic function calculates.
Step 400: finally 32 Output rusults of above-mentioned eight Floating-point transcendental function calculating unit are combined into 256 bit vector data, and write back in vector registor.
To sum up, according to the device of the witness vector floating-point basis 2 index Logarithmic calculation of the embodiment of the present invention, sense data from the vector registor preserving floating-point complex, send in data selector, the data permutation that vector is inner is delivered to Floating-point transcendental function calculating unit by data selector, Floating-point transcendental function calculating unit carries out base 2 index Logarithmic calculation according to the result of data selector, and the output of performance element preserved by last vector registor.Therefore, this device make use of the parallel computation characteristic of vector data, and can carry out the calculating of multiple floating data, the Scalar operation unit of comparing traditional, accelerates arithmetic speed, decrease the performance period simultaneously.
In describing the invention, it will be appreciated that, term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ", " thickness ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward ", " clockwise ", " counterclockwise ", " axis ", " radial direction ", orientation or the position relationship of the instruction such as " circumference " are based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, instead of indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore limitation of the present invention can not be interpreted as.
In addition, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance or imply the quantity indicating indicated technical characteristic.Thus, be limited with " first ", the feature of " second " can express or impliedly comprise at least one this feature.In describing the invention, the implication of " multiple " is at least two, such as two, three etc., unless otherwise expressly limited specifically.
In the present invention, unless otherwise clearly defined and limited, the term such as term " installation ", " being connected ", " connection ", " fixing " should be interpreted broadly, and such as, can be fixedly connected with, also can be removably connect, or integral; Can be mechanical connection, also can be electrical connection; Can be directly be connected, also indirectly can be connected by intermediary, can be the connection of two element internals or the interaction relationship of two elements, unless otherwise clear and definite restriction.For the ordinary skill in the art, above-mentioned term concrete meaning in the present invention can be understood as the case may be.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature " on " or D score can be that the first and second features directly contact, or the first and second features are by intermediary indirect contact.And, fisrt feature second feature " on ", " top " and " above " but fisrt feature directly over second feature or oblique upper, or only represent that fisrt feature level height is higher than second feature.Fisrt feature second feature " under ", " below " and " below " can be fisrt feature immediately below second feature or tiltedly below, or only represent that fisrt feature level height is less than second feature.
In the description of this instructions, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, to the schematic representation of above-mentioned term not must for be identical embodiment or example.And the specific features of description, structure, material or feature can combine in one or more embodiment in office or example in an appropriate manner.In addition, when not conflicting, the feature of the different embodiment described in this instructions or example and different embodiment or example can carry out combining and combining by those skilled in the art.
Although illustrate and describe embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, and those of ordinary skill in the art can change above-described embodiment within the scope of the invention, revises, replace and modification.
Claims (7)
1. a device for witness vector floating-point basis 2 index Logarithmic calculation, is characterized in that, comprising:
Vector registor group, comprises at least one vector registor, and wherein, multiple floating data preserved by each vector registor;
The data selector of one group of floating number, the data change order for reading from described vector registor is rear sends into Floating-point transcendental function calculating unit;
One group of Floating-point transcendental function calculating unit, for carrying out the Floating-point transcendental functional operation of single precision, and carrying out floating-point exponent or the logarithm operation of base 2, the number of described Floating-point transcendental function calculating unit is equal with the number of the floating data in described vector registor; And
Steering logic unit, for controlling the data selection of described one group of data selector, and the operating function controlling described Floating-point transcendental function calculating unit is selected.
2. the device of witness vector floating-point basis 2 index Logarithmic calculation as claimed in claim 1, it is characterized in that, described vector registor group comprises multiple vector registor, and each vector registor can comprise the floating data of multiple single precision.
3. the device of witness vector floating-point basis 2 index Logarithmic calculation as claimed in claim 1, it is characterized in that, described floating data is single-precision floating-point data.
4. the device of witness vector floating-point basis 2 index Logarithmic calculation as claimed in claim 1, it is characterized in that, described steering logic unit is for the annexation of the input port of the data selection passage and Floating-point transcendental function calculating unit of determining described data selector, and the mode of operation of Floating-point transcendental function calculating unit.
5. according to the device of the witness vector floating-point basis 2 index Logarithmic calculation described in claim 1, it is characterized in that, the structure of each Floating-point transcendental function calculating unit is identical, all adopts floating-point cordic algorithm realization to calculate.
6., according to the device of the witness vector floating-point basis 2 index Logarithmic calculation described in claim 5, it is characterized in that, each described Floating-point transcendental function calculating unit completes the index Logarithmic calculation of the single precision floating datum of 1 32.
7. the device of witness vector floating-point basis 2 index Logarithmic calculation according to claim 1, it is characterized in that, described steering logic unit is for performing following steps:
(1) read one group of data from the described vector registor group of preserving floating number, each register comprises multiple floating number;
(2) by described data selector, each floating number is extracted respectively, different floating number is delivered to each Floating-point transcendental function calculating unit;
(3) described Floating-point transcendental function calculating unit carries out single precision floating datum computing according to action type;
(4) operation result of Floating-point transcendental function calculating unit described in each is saved in a vector registor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510019196.3A CN105278913A (en) | 2015-01-14 | 2015-01-14 | Device for realizing base-2 exponential or logarithmic computation of vector floating point |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510019196.3A CN105278913A (en) | 2015-01-14 | 2015-01-14 | Device for realizing base-2 exponential or logarithmic computation of vector floating point |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105278913A true CN105278913A (en) | 2016-01-27 |
Family
ID=55147985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510019196.3A Pending CN105278913A (en) | 2015-01-14 | 2015-01-14 | Device for realizing base-2 exponential or logarithmic computation of vector floating point |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105278913A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109960533A (en) * | 2019-03-29 | 2019-07-02 | 苏州中晟宏芯信息科技有限公司 | Floating-point operation method, apparatus, equipment and storage medium |
| CN109976706A (en) * | 2019-03-29 | 2019-07-05 | 苏州中晟宏芯信息科技有限公司 | Floating-point operation device |
| CN109977701A (en) * | 2019-04-01 | 2019-07-05 | 苏州中晟宏芯信息科技有限公司 | A kind of fixed and floating arithmetic unit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3766370A (en) * | 1971-05-14 | 1973-10-16 | Hewlett Packard Co | Elementary floating point cordic function processor and shifter |
| JPH02266468A (en) * | 1989-04-06 | 1990-10-31 | Koufu Nippon Denki Kk | Vector operation processor |
| CN101825998A (en) * | 2010-01-22 | 2010-09-08 | 北京龙芯中科技术服务中心有限公司 | Instruction execution method for vector complex multiplication operation and corresponding device |
| CN102495719A (en) * | 2011-12-15 | 2012-06-13 | 中国科学院自动化研究所 | Vector floating point operation device and method |
| CN102722469A (en) * | 2012-05-28 | 2012-10-10 | 西安交通大学 | Elementary transcendental function operation method based on floating point arithmetic unit and coprocessor for method |
-
2015
- 2015-01-14 CN CN201510019196.3A patent/CN105278913A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3766370A (en) * | 1971-05-14 | 1973-10-16 | Hewlett Packard Co | Elementary floating point cordic function processor and shifter |
| JPH02266468A (en) * | 1989-04-06 | 1990-10-31 | Koufu Nippon Denki Kk | Vector operation processor |
| CN101825998A (en) * | 2010-01-22 | 2010-09-08 | 北京龙芯中科技术服务中心有限公司 | Instruction execution method for vector complex multiplication operation and corresponding device |
| CN102495719A (en) * | 2011-12-15 | 2012-06-13 | 中国科学院自动化研究所 | Vector floating point operation device and method |
| CN102722469A (en) * | 2012-05-28 | 2012-10-10 | 西安交通大学 | Elementary transcendental function operation method based on floating point arithmetic unit and coprocessor for method |
Non-Patent Citations (3)
| Title |
|---|
| 博尔顿: "《机械电气学 机械和电气工程中的电气控制系统》", 30 June 2014, 机械工业出版社 * |
| 幸云辉: "《16位微型计算机原理与应用》", 28 February 1992, 北京邮电学院出版社 * |
| 王庆荣: "《计算机组成原理与体系结构》", 31 August 2013, 北京交通大学出版社 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109960533A (en) * | 2019-03-29 | 2019-07-02 | 苏州中晟宏芯信息科技有限公司 | Floating-point operation method, apparatus, equipment and storage medium |
| CN109976706A (en) * | 2019-03-29 | 2019-07-05 | 苏州中晟宏芯信息科技有限公司 | Floating-point operation device |
| CN109976706B (en) * | 2019-03-29 | 2023-03-31 | 合芯科技(苏州)有限公司 | Floating-point arithmetic device |
| CN109960533B (en) * | 2019-03-29 | 2023-04-25 | 合芯科技(苏州)有限公司 | Floating point operation method, device, equipment and storage medium |
| CN109977701A (en) * | 2019-04-01 | 2019-07-05 | 苏州中晟宏芯信息科技有限公司 | A kind of fixed and floating arithmetic unit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107077416B (en) | Apparatus and method for vector processing in selective rounding mode | |
| JP6487097B2 (en) | Perform rounding according to instructions | |
| CN108139885B (en) | Floating point number rounding | |
| US5946361A (en) | Viterbi decoding method and circuit with accelerated back-tracing and efficient path metric calculation | |
| CN107769791B (en) | Apparatus and method for fixed-to-floating point conversion and negative power detector of 2 | |
| KR102200913B1 (en) | High performance floating-point adder with full in-line denormal/subnormal support | |
| US11853716B2 (en) | System and method for rounding reciprocal square root results of input floating point numbers | |
| CN112540946B (en) | Reconfigurable processor and method for calculating activation functions of various neural networks on reconfigurable processor | |
| CN102087590A (en) | Execution device of resource-multiplexing floating point SIMD (single instruction multiple data) instruction | |
| CN105278913A (en) | Device for realizing base-2 exponential or logarithmic computation of vector floating point | |
| CN101650643B (en) | Rounding method for indivisible floating point division radication | |
| KR20090007478A (en) | Controlled-precision iterative arithmetic logic unit | |
| WO1999066423A1 (en) | Data calculating device | |
| CN104866461A (en) | Floating point complex number i-multiplying addition-subtraction device and floating point complex number i-multiplying addition-subtraction method | |
| RU2439667C1 (en) | Processor of higher functioning reliability | |
| CN111124361A (en) | Arithmetic processing apparatus and control method thereof | |
| US7917707B2 (en) | Semiconductor device | |
| US20110022646A1 (en) | Processor, control method of processor, and computer readable storage medium storing processing program | |
| KR100331846B1 (en) | floating addition | |
| JPH0346024A (en) | Floating point computing element | |
| US20150363170A1 (en) | Calculation of a number of iterations | |
| JPH10283340A (en) | Arithmetic processor | |
| CN105302772A (en) | Floating point complex number vector first-level FFT computing method and system | |
| CN109977701B (en) | Fixed floating point arithmetic device | |
| CN109947391A (en) | A kind of data processing method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination |