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CN105244259A - Structure and fabrication method of multiple patterning mask layer - Google Patents

Structure and fabrication method of multiple patterning mask layer Download PDF

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Publication number
CN105244259A
CN105244259A CN201510663000.4A CN201510663000A CN105244259A CN 105244259 A CN105244259 A CN 105244259A CN 201510663000 A CN201510663000 A CN 201510663000A CN 105244259 A CN105244259 A CN 105244259A
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CN
China
Prior art keywords
side wall
sacrifice layer
multiple graphical
mask
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510663000.4A
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Chinese (zh)
Inventor
鲍宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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Publication date
Application filed by Shanghai Huali Microelectronics Corp filed Critical Shanghai Huali Microelectronics Corp
Priority to CN201510663000.4A priority Critical patent/CN105244259A/en
Publication of CN105244259A publication Critical patent/CN105244259A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention relates to the field of yield improvement of semiconductors, in particular to a structure of a multiple patterning mask layer. The structure comprises a base plate and a hard mask, wherein the base plate is used for forming a substrate, and the hard mask is used for providing an operation surface for etching. The invention simultaneously provides a fabrication method of the multiple patterning mask layer, and the fabrication method comprises the following steps of depositing the hard mask and a sacrificial layer; patterning the sacrificial layer; depositing a thin film and etching to form a first side wall; depositing a thin film again and etching to form a second side wall; and finally, removing the sacrificial layer, and correcting the morphologies of the side walls by an etching method.

Description

A kind of structure of multiple graphical mask layer and manufacture method
Technical field
The present invention relates to semiconductor yields and promote field, particularly relate to a kind of structure and manufacture method of multiple graphical mask layer.
Background technology
Semicon industry manufacture is maked rapid progress, and the manufacturing process of product more and more becomes more meticulous.Various defect can produce the yield of product and kill and wound, and improve cause the various factors of defect also more and more to become the important means that can promote semiconductor yields.Find in production that the varying topography of the both sides sidewall of a lot of defect and mask layer side wall has correlation, little sidewall profile difference is passable, thus gives security for improving chip quality.
Because the value of semiconductor product depends on the technology adopted in development & production process to a great extent, and As time goes on and rapidly the value of these technology often devalue.Therefore, once there are the quality problems that yield declines, solved by the technical scheme of improvement with regard to needing.
Summary of the invention
For the problems referred to above, the present invention relates to a kind of structure and manufacture method of multiple graphical mask layer, it is characterized in that, comprise, substrate, hard mask, side wall, described hard mask is in surface, and described side wall is deposited by sacrifice layer and etched and formed, overall pointed, point is put down in inside and outside is round and smooth;
Above-mentioned mask layer, is characterized in that, the material of described hard mask preferably but be limited to silicon nitride.
Above-mentioned mask layer, is characterized in that, the material of described sacrifice layer is: silica or silicon nitride or silicon oxynitride or amorphous carbon or boron nitride or titanium nitride.
Above-mentioned mask layer, is characterized in that, the material of described side wall is: silica or silicon nitride or silicon oxynitride or amorphous carbon or boron nitride or titanium nitride.
Above-mentioned mask layer, is characterized in that, described side wall number is more than or equal to 2, and the height of the first side wall is greater than the height of the second side wall, and described first side wall flushes with bottom described second side wall.
Above-mentioned mask layer, multiple graphical mask layer according to claim 6, is characterized in that, the width of described first side wall is greater than 20A, and thickness is 1/4 to 1/2 of described first side wall and described second lateral wall width summation.
For the problems referred to above, the present invention relates to a kind of structure and manufacture method of multiple graphical mask layer, it is characterized in that, comprise, substrate, hard mask, side wall, described hard mask is in surface, and described side wall is deposited by sacrifice layer and etched and formed, overall pointed, point is put down in inside and outside is round and smooth;
Above-mentioned mask layer, is characterized in that, the material of described hard mask preferably but be limited to silicon nitride.
Above-mentioned mask layer, is characterized in that, the material of described sacrifice layer is: silica or silicon nitride or silicon oxynitride or amorphous carbon or boron nitride or titanium nitride.
Above-mentioned mask layer, is characterized in that, the material of described side wall is: silica or silicon nitride or silicon oxynitride or amorphous carbon or boron nitride or titanium nitride.
Above-mentioned mask layer, is characterized in that, described side wall number is more than or equal to 2, and the height of the first side wall is greater than the height of the second side wall, and described first side wall flushes with bottom described second side wall.
Above-mentioned mask layer, multiple graphical mask layer according to claim 6, is characterized in that, the width of described first side wall is greater than 20A, and thickness is 1/4 to 1/2 of described first side wall and described second lateral wall width summation.
Beneficial effect, the structure of a kind of multiple graphical mask layer that the present invention proposes and manufacture method, both sides inner side of outer wall sidewall profile can be changed by adopting this mask layer, this can reduce the varying topography of the both sides sidewall of side wall effectively, and then reduce the possibility of side wall as defect source, very large help can be produced to raising product yield.
Accompanying drawing explanation
Fig. 1 is the sectional view of the mask material of one embodiment of the invention.
Fig. 2 is the sectional view of the mask with graphical sacrifice layer of one embodiment of the invention.
Fig. 3 is the sectional view of the mask with the first side wall of one embodiment of the invention.
Fig. 4 is the sectional view of the mask with the second side wall of one embodiment of the invention.
Fig. 5 is the sectional view of the mask after the removal sacrifice layer of one embodiment of the invention.
Fig. 6 is the sectional view of the mask after the amendment pattern of one embodiment of the invention.
Fig. 7 is the sectional view of the mask material of another embodiment of the present invention.
Fig. 8 is the sectional view of the graphical sacrifice layer of another embodiment of the present invention.
Fig. 9 is the sectional view of many sacrifice layers of another embodiment of the present invention.
Figure 10 is the sectional view of the mask with side wall of another embodiment of the present invention.
Figure 11 is the sectional view of the mask after the removal sacrifice layer of another embodiment of the present invention.
Figure 12 is the sectional view of the mask after the amendment pattern of another embodiment of the present invention.
Figure 13 is the preparation method of a kind of multiple graphical mask layer of the present invention.
Figure 14 is the preparation method of a kind of multiple graphical mask layer of the present invention.
Embodiment
For at present in actual production, mask layer side wall is one of reason becoming defect often, so propose a kind of new mask layer to improve semiconductor yields.
The present invention relates to a kind of structure and manufacture method of multiple graphical mask layer, substrate, hard mask, side wall, described hard mask is in surface, and described side wall is deposited by sacrifice layer and etched and formed, and overall pointed, point is put down in inside and outside is round and smooth.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described.
A specific embodiment of the present invention:
As shown in Figure 6, the invention provides a kind of structure of multiple graphical mask layer, comprise substrate 1, hard mask 2, first side wall 7 and the second side wall 6.
As shown in Figure 1, first place substrate 1 as substrate, then place hard mask 2, wherein hard mask 2 material preferred nitrogen SiClx on substrate 1, but be not limited to silicon nitride.Then the sacrifice layer 3 in order to etching is positioned on hard mask 2.Wherein sacrifice layer 3 material includes but not limited to silica, silicon nitride, silicon oxynitride, amorphous carbon, boron nitride, titanium nitride.
We need first to carry out graphical treatment to the first sacrifice layer 3, obtain as shown in Figure 2 and the sacrifice layer 4 that meets of required size requirement, now the sacrifice layer 4 after graphical treatment is deposited, form the first side wall 5 as shown in Figure 3, wherein the width of the first side wall 5 is greater than 20A, preferably, the thickness of the first side wall 5 is 1/4 to 1/2 of whole side wall.
As shown in Figure 4, again deposition shape second side wall 6 is carried out in the first side wall 5 outside.Wherein, if side wall number is greater than 2, then corresponding frequency of depositing is also greater than 2.
As shown in Figure 5, be removable sacrifice layer 3 after all side walls are formed, the sidewall section of formation is revealed.Can clearly find out from figure, the height of the first side wall 5 is greater than large two side walls 6, and when wherein side wall quantity is greater than 2, height of side wall tapers off trend from inside to outside.The outboard sidewalls varying topography of whole side wall is larger, therefore the first side wall 5 is etched by the method for etching, to reduce the varying topography of the both sides sidewall of side wall, the process wherein etching the first side wall 5 can be independently, also can carry out in the process of etching hard mask 2 simultaneously, but all require that the etch rate of the first side wall 5 is greater than the second side wall 6.
As shown in Figure 6, the first side wall 7 after etching and the mask of varying topography more not without pattern process of the second side wall 6 less.
As shown in figure 13, a kind of preparation method of multiple graphical mask layer, is characterized in that, comprise,
Step S1: place substrate, hard mask and sacrifice layer
Step S2: deposition hard mask and sacrifice layer
Step S3: graphical treatment is carried out to sacrifice layer by taking a picture/etching
Step S4: deposit film also etches formation first side wall
Step S5: deposit film also etches formation second side wall
Step S6: remove sacrifice layer
Step S7: with the pattern of etching amendment side wall
A preferred scheme, in described step S4, while etching hard mask, the pattern of amendment side wall, requires that the etch rate of the first side wall is greater than the second side wall.
A preferred scheme, in described step S7, uses the pattern of independently etch step amendment side wall, requires that the etch rate of the first side wall is greater than the second side wall.
An alternative embodiment of the invention:
As shown in figure 12, the invention provides a kind of structure of multiple graphical mask layer, comprise substrate 8, hard mask 9, first side wall 16 and the second side wall 15.
As shown in Figure 7, first place substrate 8 as substrate, then place hard mask 9, wherein hard mask 9 material preferred nitrogen SiClx on the substrate 8, but be not limited to silicon nitride.Then the first sacrifice layer 10 in order to etching is positioned on hard mask 9.
As shown in Figure 8, we need to carry out graphical treatment to the first sacrifice layer 10, obtain the first sacrifice layer 11 met with required size requirement.
As shown in Figure 9, cover the second sacrifice layer 12 and the 3rd sacrifice layer 13 of hat shape above the first sacrifice layer 11 after graphical treatment, wherein the sacrifice layer number of plies can be greater than 3.
As shown in Figure 10, the second sacrifice layer 12 and the 3rd sacrifice layer 13 are etched, makes them reach desired thickness, wherein the thickness of sacrifice layer 12 is greater than 20A, preferably, thickness is 1/4 to 1/2 of side wall gross thickness, and the etch rate of sacrifice layer 12 is greater than sacrifice layer 13 simultaneously.Sacrifice layer after etching is deposited, obtain the first side wall 14 and the second side wall 15, wherein the first side wall 14 is square, the second side wall 15 by semi-surrounding in the first side wall 14, be removable sacrifice layer 11 after all side walls are formed, the sidewall section of formation is revealed.
As shown in figure 11, the outboard sidewalls varying topography removing the side wall after sacrifice layer 11 is larger, therefore the first side wall 14 is etched by the method for etching, to reduce the varying topography of the both sides sidewall of side wall, the process wherein etching the first side wall 14 can be independently, also can carry out in the process of etching hard mask 9 simultaneously.
As shown in figure 12, the first side wall 16 after etching and the varying topography of the second side wall 15 less compared with the mask without pattern process.
As shown in figure 14, a kind of preparation method of multiple graphical mask layer, is characterized in that, comprise,
Step S1: place base plate, hard mask and sacrifice layer
Step S2: deposition hard mask and the first sacrifice layer
Step S3: graphical treatment is carried out to the first sacrifice layer by taking a picture/etching
Step S4: the second sacrifice layer and the 3rd sacrifice layer are deposited
Step S5: deposit film also etches formation first side wall
Step S6: deposit film also etches formation second side wall
Step S7: remove sacrifice layer
Step S8: with the pattern of etching amendment side wall
A preferred embodiment, in described step S5, while etching hard mask, the pattern of amendment side wall, wherein requires that the etch rate of the first side wall is greater than the second side wall.
A preferred embodiment, in described step S8, uses the pattern of independently etch step amendment side wall, wherein requires that the etch rate of the first side wall is greater than the second side wall.
In sum, the structure of a kind of multiple graphical mask layer that the present invention proposes and manufacture method, both sides inner side of outer wall sidewall profile can be changed by adopting this mask layer, this can reduce the varying topography of the both sides sidewall of side wall effectively, and then reduce the possibility of side wall as defect source, very large help can be produced to raising product yield.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.

Claims (18)

1. a structure for multiple graphical mask layer, is characterized in that, described mask layer comprises,
Hard mask, is in surface;
Side wall, is deposited by sacrifice layer and is etched and formed, overall pointed, inner flat point and outside round and smooth.
2. multiple graphical mask layer according to claim 1, is characterized in that, the material of described hard mask is silicon nitride.
3. multiple graphical mask layer according to claim 1, is characterized in that, the material of described sacrifice layer is: silica or silicon nitride or silicon oxynitride or amorphous carbon or boron nitride or titanium nitride.
4. multiple graphical mask layer according to claim 1, is characterized in that, the material of described side wall is: silica or silicon nitride or silicon oxynitride or amorphous carbon or boron nitride or titanium nitride.
5. multiple graphical mask layer according to claim 1, is characterized in that, described side wall number is more than or equal to 2, and the height of the first side wall is greater than the height of the second side wall, and described first side wall flushes with bottom described second side wall.
6. multiple graphical mask layer according to claim 6, is characterized in that, the width of described first side wall is greater than 20A, and thickness is 1/4 to 1/2 of described first side wall and described second lateral wall width summation.
7. a preparation method for multiple graphical mask layer, is characterized in that, comprises,
Step S1: place substrate, hard mask and sacrifice layer
Step S2: deposition hard mask and sacrifice layer
Step S3: graphical treatment is carried out to sacrifice layer by taking a picture/etching
Step S4: deposit film also etches formation first side wall
Step S5: deposit film also etches formation second side wall
Step S6: remove sacrifice layer
Step S7: with the pattern of etching amendment side wall
8. the preparation method of multiple graphical mask layer according to claim 8, is characterized in that, in described step S4, while etching hard mask, the pattern of amendment side wall, wherein requires that the etch rate of the first side wall is greater than the second side wall.
9. the preparation method of multiple graphical mask layer according to claim 8, is characterized in that, in described step S7, uses the pattern of independently etch step amendment side wall, wherein requires that the etch rate of the first side wall is greater than the second side wall.
10. a structure for multiple graphical mask layer, is characterized in that, described mask layer comprises,
Hard mask, is in surface;
Side wall, is deposited by sacrifice layer and is etched and formed, overall pointed, inner flat point and outside round and smooth.
11. multiple graphical mask layers according to claim 10, is characterized in that, the material of described hard mask is silicon nitride.
12. multiple graphical mask layers according to claim 10, is characterized in that, the material of described sacrifice layer is: silica or silicon nitride or silicon oxynitride or amorphous carbon or boron nitride or titanium nitride.
13. multiple graphical mask layers according to claim 10, is characterized in that, the material of described side wall is: silica or silicon nitride or silicon oxynitride or amorphous carbon or boron nitride or titanium nitride.
14. multiple graphical mask layers according to claim 10, is characterized in that, the described sacrifice layer number of plies is more than or equal to 2.
15. multiple graphical mask layers according to claim 10, it is characterized in that, the thickness of the second sacrifice layer is greater than 20A, and thickness is 1/4 to 1/2 of the first side wall and the second lateral wall width summation, described second side wall is rectangular in shape, and described first side wall is surrounded by half in described second side wall.
The preparation method of 16. 1 kinds of multiple graphical mask layers, is characterized in that, comprises,
Step S1: place base plate, hard mask and sacrifice layer
Step S2: deposition hard mask and the first sacrifice layer
Step S3: graphical treatment is carried out to the first sacrifice layer by taking a picture/etching
Step S4: the second sacrifice layer and the 3rd sacrifice layer are deposited
Step S5: deposit film also etches formation first side wall
Step S6: deposit film also etches formation second side wall
Step S7: remove sacrifice layer
Step S8: with the pattern of etching amendment side wall
The preparation method of 17. multiple graphical mask layers according to claim 8, is characterized in that, in described step S5, while etching hard mask, the pattern of amendment side wall, wherein requires that the etch rate of the first side wall is greater than the second side wall.
The preparation method of 18. multiple graphical mask layers according to claim 8, is characterized in that, in described step S8, uses the pattern of independently etch step amendment side wall, wherein requires that the etch rate of the first side wall is greater than the second side wall.
CN201510663000.4A 2015-10-14 2015-10-14 Structure and fabrication method of multiple patterning mask layer Pending CN105244259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Publications (1)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107359111A (en) * 2016-05-10 2017-11-17 上海格易电子有限公司 A kind of method of self-alignment duplex pattern
CN109216165A (en) * 2017-07-06 2019-01-15 中芯国际集成电路制造(天津)有限公司 The manufacturing method of multiple graphics and semiconductor devices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103578931A (en) * 2012-07-20 2014-02-12 中芯国际集成电路制造(上海)有限公司 Multiple graphical mask layer and forming method thereof
CN103632943A (en) * 2012-08-24 2014-03-12 中国科学院微电子研究所 Semiconductor device manufacturing method
CN103715080A (en) * 2012-09-29 2014-04-09 中芯国际集成电路制造(上海)有限公司 Forming method of self-aligned double pattern
CN103794490A (en) * 2012-10-30 2014-05-14 中芯国际集成电路制造(上海)有限公司 Method for forming self-aligned double pattern
US20140256136A1 (en) * 2013-03-06 2014-09-11 United Microelectronics Corp. Method for forming fin-shaped structures

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103578931A (en) * 2012-07-20 2014-02-12 中芯国际集成电路制造(上海)有限公司 Multiple graphical mask layer and forming method thereof
CN103632943A (en) * 2012-08-24 2014-03-12 中国科学院微电子研究所 Semiconductor device manufacturing method
CN103715080A (en) * 2012-09-29 2014-04-09 中芯国际集成电路制造(上海)有限公司 Forming method of self-aligned double pattern
CN103794490A (en) * 2012-10-30 2014-05-14 中芯国际集成电路制造(上海)有限公司 Method for forming self-aligned double pattern
US20140256136A1 (en) * 2013-03-06 2014-09-11 United Microelectronics Corp. Method for forming fin-shaped structures

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107359111A (en) * 2016-05-10 2017-11-17 上海格易电子有限公司 A kind of method of self-alignment duplex pattern
CN109216165A (en) * 2017-07-06 2019-01-15 中芯国际集成电路制造(天津)有限公司 The manufacturing method of multiple graphics and semiconductor devices
CN109216165B (en) * 2017-07-06 2020-11-03 中芯国际集成电路制造(天津)有限公司 Method for manufacturing multiple patterns and semiconductor device

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