CN105227259A - A kind of M sequence walks abreast production method and device - Google Patents
A kind of M sequence walks abreast production method and device Download PDFInfo
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Abstract
The invention provides a kind of M sequence to walk abreast production method, comprising: the recurrence formula 1) obtaining M sequence, determine degree of parallelism w, input initial M sequence position; 2) the synchronous known M sequence position of w group of reading is as input data, synchronously carries out w road recurrence calculation, obtain original w unknown M sequence position according to recurrence formula; Wherein, one group of known M sequence position is corresponding to each power item on the right side of the recurrence formula of a road recurrence calculation; 3) recording step 2) w M sequence position calculating this w M sequence bit synchronization is exported, then re-execute step 2) to calculate w M sequence position of next group.Present invention also offers corresponding M sequence to walk abreast generation device.It is high that the present invention has degree of parallelism, and feedback is simple, and initialization is simple, has both been applicable to the advantage that hardware implementing is also applicable to software simulating.
Description
Technical field
The present invention relates to the communications field, more specifically, the present invention relates to a kind of M sequence and to walk abreast production method and device.
Background technology
M sequence is the abbreviation of maximum length linear shift register sequence, is a kind of pseudo random sequence, pseudo noise (PN) code or pseudo noise code.Can to pre-determine and the sequence that can repeat to realize is called and determines sequence; The sequence that can not pre-determine and can not repeat to realize claims random sequence; Can not pre-determine but can repeat produce sequence claim pseudo random sequence.M sequence is widely used in radio communication Code scrambling technique.
Code scrambling technique is technology conventional in digital communication, and its object can make the data transmitted in channel have randomness, thus effectively can avoid the interference between data.Scrambler sequence is made up of pseudo random sequence M sequence usually.Along with the development of mobile communication, transmission rate is more and more higher, and required scrambler speed is also more and more higher, and disturbing code parallel is a kind of well solution of generation speed improving scrambler.
Traditional parallel disturbance code technology mainly contains look-up table, matrix method, sampling method.Look-up table adopts memory to realize parallelization, and one-period is 2
rthe scrambler sequence of-1 (r is generator polynomial exponent number), if need degree of parallelism to be W, so W* (2
r-1) be also cycle of scrambler sequence.Adopt bit wide to be the memory of W, store (2
r-1) arrange, each row that extract carry out scrambling, after last row, be recycled to first row.Look-up table advantage is that speed is fast, and complexity is low, but storage overhead is very large, is applicable to the occasion that generator polynomial exponent number is lower.But along with Mobile Communication Development, it is more complicated that the generator polynomial of scrambler sequence has become, and in such as forth generation mobile communication LTE, the generator polynomial of scrambler sequence has reached 31 rank, and look-up table is no longer applicable.
Matrix method adopts the mode of matrix condition machine transfer, by the involution of multiple Matrix of shifting of a step, obtains Many steps shift matrix, thus once can realize the renewal of multiple state machine, achieve disturbing code parallel.Matrix method is applicable to the hardware implementing based on Parasites Fauna.But, although matrix method can realize arbitrary degree of parallelism in theory, but due to the transfer of needs realization matrix state machine, feedback in matrix method disturbance code generation device between some register cell is often comparatively complicated, when causing generating scrambler word, the time delay of some scrambler position is longer, due to wooden pail effect, the time delay generating whole scrambler word is also longer, and then causes the overall operation frequency of system to reduce.When scrambler exponent number higher (such as the scrambler of the LTE system on 31 rank), when degree of parallelism is higher, above-mentioned defect is particularly evident.In addition, matrix method is also not suitable for SIMD (single-instruction multiple-data) DSP and realizes, and when needing new scrambler, often need special hardware, versatility is more weak.
Sampling method is sampled to scrambler sequence, former scrambler sequence is decomposed into w sampled sequence (i.e. subsequence), each sampled sequence all designs independently generation unit, and export a scrambler in the same clock cycle, such w sampled sequence just can export w position scrambler a clock cycle, thus improves scrambler generating rate.Sampling method advantage is that degree of parallelism can be very high, scrambler sequence formation speed can be very fast, but each independent generation unit needs independently resource, and resource overhead is very large, and each independent generation unit needs to calculate initial value separately, cause the implementation complexity of initial value also larger like this.
Summary of the invention
The object of this invention is to provide a kind of M sequence that can overcome above-mentioned prior art defect to walk abreast production method and device.
According to an aspect of the present invention, provide a kind of M sequence and to walk abreast production method, comprise the following steps:
1) obtain the recurrence formula of M sequence, determine degree of parallelism w, input initial M sequence position;
2) the synchronous known M sequence position of w group of reading is as input data, synchronously carries out w road recurrence calculation, obtain original w unknown M sequence position according to recurrence formula; Wherein, one group of known M sequence position is corresponding to each power item on the right side of the recurrence formula of a road recurrence calculation;
3) recording step 2) w M sequence position calculating this w M sequence bit synchronization is exported, then re-execute step 2) to calculate w M sequence position of next group.
Wherein, described step 1) in, described degree of parallelism w is not more than maximum parallelism degree P=r-q, and wherein r represents the exponent number of described recurrence formula, and q represents the sequence number of the highest power item in the right side of recurrence formula.
Wherein, described step 1) in, described M sequence is the first M sequence in LTE protocol or the second M sequence in LTE protocol.
According to a further aspect in the invention, additionally provide and a kind ofly to walk abreast generation device for realizing the walk abreast M sequence of production method of aforementioned M sequence, suppose that the exponent number of the recurrence formula of M sequence is r, the sequence number of the highest power item in right side of recurrence formula is q, then the described M sequence generation device that walks abreast comprises r register and w recursive operation unit, and wherein w is not more than maximum parallelism degree P=r-q;
R described register is designated as respectively: 0 ~ r-1 register, and each register includes output, input and clock end, and w recursive operation unit is designated as respectively: 0 ~ w-1 recursive operation unit;
Wherein, corresponding power term coefficient is not the input that the output of i-th ~ i+q register of 0 and the output of No. i-th register are linked into No. i-th recursive operation unit simultaneously, No. i-th recursive operation unit is for completing the computing of the i-th road recurrence formula, and the output of No. i-th recursive operation unit connects the input of the i-th+r-w register, form first group of feedback line, wherein i is that the integer of 0 to w-1 is enumerated;
The output of jth+w register connects the input of jth register, forms second group of feedback line, and wherein j is that the integer of 0 to r-w-1 is enumerated.
Wherein, the output of described 0 ~ w-1 register is as the output of M sequence position.
Wherein, described 0 ~ w-1 register each cycle parallel output w position M sequence code.
According to another aspect of the invention, additionally provide another kind of method M sequence to walk abreast production method, described M sequence walks abreast production method based on the vectorial DSP realization with SIMD structure, wherein, the exponent number of the recurrence formula of M sequence is r, and the sequence number of the highest power item in right side of recurrence formula is q, then in DSP, the vector length of vector instruction is w, w is not more than maximum parallelism degree P=r-q, and wherein, r, q, w are natural number;
The described M sequence production method that walks abreast comprises the following steps:
1) from internal memory, read the known M sequence position of w group respectively by repeatedly vectorial reading command and read in data vector register at least two, wherein, read in data vector register described in each and receive w known M sequence position;
2) then by vectorial xor operation instruction, xor operation is carried out to the data that described at least two read in data vector register and obtain w new M sequence position, and vectorial xor operation result write is exported data vector register;
3) storing instruction by exporting the data buffer storage of data vector register to the relevant position in internal memory by vector, then returning step 1), start the calculating carrying out next group M sequence position.
Wherein, described M sequence is the first M sequence in LTE protocol or the second M sequence in LTE protocol.
Wherein, described step 3) also comprise: stored by vector instruction by the data buffer storage that exports data vector register to the relevant position in internal memory while, by w M sequence position output of institute's buffer memory in internal memory.
Compared with prior art, the present invention has following technique effect:
1, M sequence generation scheme degree of parallelism of the present invention is higher, and feedback is simple, and initialization is simple, is both applicable to the hardware implementing also applicable software simulating based on DSP.
2, M sequence of the present invention generates scheme and is particularly suitable for two-forty, high degree of parallelism, and the scrambler of high exponent number generates.
Accompanying drawing explanation
Fig. 1 is that M sequence walks abreast production method schematic diagram;
A kind of scrambler sequence that Fig. 2 shows to be provided according to one embodiment of the invention walks abreast the structural representation of generation device;
Fig. 3 show this device a kind of scrambler sequence provided according to a further embodiment of the invention walk abreast generation device program command perform schematic diagram.
Embodiment
In prior art, scrambler sequence both can generate in serial, also can parallel generation.And in serial generation technique, normally based on recurrence formula, with known scrambler position to pushing away unknown new scrambler position, and new scrambler position is exported one by one.The recurrence formula of inventor to serial scrambler is furtherd investigate, recurrence formula is diverted to parallel disturbance code sequence generator, and then propose a kind of parallel disturbance code sequence generation scheme, relative to traditional parallel disturbance code technology, program feedback is simple, and initialization is simple, both the hardware implementing also applicable software simulating based on software DSP had been applicable to, be particularly suitable for two-forty, high degree of parallelism, the scrambler of high exponent number generates.For the ease of understanding, first introduce the recurrence formula for generating scrambler sequence below.
As mentioned before, scrambler sequence is made up of pseudo random sequence M sequence usually.Mathematically can represent pseudo random sequence M sequence by primitive polynomial, can generate M sequence by the method for recursion by primitive polynomial, therefore this multinomial is also called the generator polynomial of M sequence.A general generator polynomial can be expressed as:
f(x)=x
r+c
r-1x
r-1+…+c
1x+1
Wherein r is generator polynomial exponent number, c
ieach coefficient in generator polynomial, i=1,2 ..., r-1; And c
i∈ { 0,1}.This multinomial can generate with 2
r-1 is the M sequence in cycle.This generator polynomial corresponds to recurrence formula:
x(n+r)=c
r-1x(n+r-1)+…+c
1x(n+1)+x(n),n=0,1,2,…,N
Wherein r is generator polynomial exponent number, c
ieach coefficient in generator polynomial, and c
i∈ 0,1}, N are the length of the M sequence that will generate, wherein generator polynomial every between "+" represent " mould 2 adds " operation, also can use " ^ " symbol, namely distance symbol represents same operation.
Inventor analyses in depth M sequence generator polynomial conventional at present, finds in general M sequence generation system, often only have front q to have value, and all the other coefficients is 0, i.e. c in generator polynomial coefficient
1, c
2..., c
qthere is value, and c
q+1, c
q+2..., c
r-1be 0 entirely.Use this character to realize the parallelization of scrambler sequence, its maximum parallelism degree P=r-q, wherein q equals the sequence number that coefficient is the highest power item correspondence of 1.
Below in conjunction with an embodiment generated for the scrambler realizing LTE system of the present invention the present invention done and describe further.
According to one embodiment of present invention, propose a kind of parallel generation method of scrambler sequence, comprise the following steps:
Step 1: recurrence formula x (the n+r)=c obtaining M sequence
qx (n+q) ^ ... ^c
1x (n+1) ^x
1n (), determines degree of parallelism w.Wherein symbol " ^ " represents nonequivalence operation (i.e. " mould 2 adds " computing).In this step, also generate r initial value of scrambler sequence, namely generate initialization sequence.
Adopt two-way M sequence xor operation to produce scrambler sequence in LTE, be first described for wherein first via M sequence, in LTE protocol, the recurrence formula of the first M sequence is:
x(n+31)=x(n+3)^x(n),n=0,1,…,N
Analyze recurrence formula, can find out that the exponent number r of the first M sequence in LTE protocol equals 31, the sequence number q of the highest power item equals 3, and maximum parallelism degree P is 28.Suppose that the degree of parallelism adopted in real system is w, so just need to ensure that w is not more than 28.
On the other hand, in the present embodiment, LTE first M sequence gives 31 initial values, and in the practical application of LTE protocol, need M sequence be from the 1600th of M sequence, therefore in sequence first 1600 be useless, if carry out output to these 1600 numerical value can cause waste.In the present embodiment, before carrying out M sequence generation, first directly utilize recurrence formula to carry out iterative computation according to 31 initial values to derive 31 values from the 1600th.Then carry out M sequence generation by 31 values derived as initial value input hardware or software, thus save the related resource producing M sequence.
Step 2: the synchronous known scrambler position of w group (scrambler position in fact just refers to the position of M sequence herein, i.e. M sequence code) of reading, as input data, is synchronously carried out w road recurrence calculation according to recurrence formula, obtained w unknown scrambler position.Wherein, often organize known scrambler position and correspond to a unknown scrambler position.In the present invention, be called scrambler position by being used for the data bit generated in the M sequence of scrambler.Illustrate below.
When the degree of parallelism w that the first M sequence in LTE protocol adopts is 16, corresponding multichannel recurrence formula is as follows:
With reference to above-mentioned multichannel recurrence formula, often group input data to be sequence number differences be 3 two scrambler positions, such as: x (n+3), x (n) is the 1st group of known scrambler position as input data, x (n+4), x (n+1) is the 2nd group of known scrambler position as input data, x (n+18), x (n+15) is the 16th group of known scrambler position as input data, often taking turns recurrence calculation needs synchronous reading 16 groups of scrambler positions as input data, take turns after parallelization recurrence calculation completes one, the scrambler position that x (n+31) to x (n+46) these 16 is new will be obtained.
When the degree of parallelism w that the first M sequence in LTE protocol adopts is 28, then multichannel recurrence formula is as follows:
Similar when carrying out scheme and the w=16 of parallelization recurrence calculation according to this multichannel recurrence formula, repeat no more herein.
Can find out, corresponding to General System, general multichannel recurrence formula can be drawn:
Wherein r is generator polynomial coefficient, c
qthat in generator polynomial, coefficient is the maximum power term coefficient of 1, c
qbe constantly equal to the degree of parallelism that 1, w is actual employing, maximum parallelism degree P=r-q, w is not more than P, so w+q is not more than r.
Similar when carrying out scheme and the w=16 of parallelization recurrence calculation according to this general multichannel recurrence formula, repeat no more herein.
Step 3: this w scrambler bit synchronization also exports by w the scrambler position that record calculates, and re-executes the input data that step 2 reads next round recurrence calculation.
Continuous execution above-mentioned steps 2,3, namely sustainably parallel generation and export scrambler.
In the parallel generation method of above-mentioned scrambler sequence, for often taking turns computing, the stepping type of w road computing is completely the same, therefore when hardware implementing, the computing of w road can use identical connection mode and arithmetic element, like this, the time delay generating the new scrambler in w position is identical, can avoid limiting hardware frequency because of wooden pail effect, contribute to the generating rate improving parallel disturbance code further.On the other hand, parallel data will experience identical computing and storage, and therefore the parallel generation method of above-mentioned scrambler sequence is also easy to use vector instruction to carry out programming realization, is therefore suitable for realizing in the vectorial DSP with SIMD structure.
Further, a kind of scrambler sequence that Fig. 2 shows to be provided according to one embodiment of the invention walks abreast the structural representation of generation device, and this embodiment is that the scrambler sequence realizing first via M sequence in LTE system walks abreast generation device.In the present embodiment, the scrambler sequence generation device that walks abreast comprises 31 registers, and compiling from top to bottom in Fig. 2 is 0 to No. 30 register.Wherein, the D end of each register is input, and Q end is output, and CLK end is input end of clock mouth, and whole device meets sequential logic, and whenever a clock cycle terminates, the data that register Q holds can be updated to the data of D end.XOR function is completed by combinatorial logic unit, because the recurrence formula of first via M sequence in LTE system is only containing an XOR, therefore can think that recursive operation comes into force immediately.
With reference to figure 2, hardware designs based on this register and XOR circuit is described below: first, for the structure of hardware designs, exponent number due to M sequence in the present embodiment is r (r=31), therefore the register capacity needed in hardware designs is also r (namely 31), and 0 ~ r-1 (namely 0 ~ 30) is set as to register number.Secondly, for the line of hardware designs, sequence number due to power item the highest on the right side of recurrence formula is q (in the present embodiment q=3), therefore need register output register number being differed q (namely 3) to carry out XOR line, required for carry out XOR register number depend on designed degree of parallelism.Again, for the output of hardware designs, because designed hardware degree of parallelism is w (w=16), therefore utilize the numerical value of register 0 ~ w-1 (namely 0 ~ 15) and register q ~ w+q-1 (namely 3 ~ 18) to carry out XOR, through a clock cycle, just can export the individual scrambler position of w (namely 16) simultaneously.Finally, for the feedback of hardware designs, because designed hardware degree of parallelism is w (w=16), therefore need the value of register w ~ r-1 (namely 16 ~ 30) to be assigned to register 0 ~ r-w-1 (namely 0 ~ 14), need w (namely 16) the individual bit exported to feed back to the register being numbered r-w ~ r-1 (namely 15 ~ 30) simultaneously.In such hardware designs, can ensure that 1 clock cycle produces w operation result and w road is fed back, thus can Parallel Implementation scrambler sequence produce.The hardware of the second M sequence or software simulating consistent with the first M sequence principle, repeat no more here.
Based on the embodiment of Fig. 2, the general parallel disturbance code hardware implementations based on recurrence formula can be drawn further.
Suppose that general multichannel recurrence formula is as follows:
Wherein r is generator polynomial coefficient, c
qthat in generator polynomial, coefficient is the maximum power term coefficient of 1, c
qbe constantly equal to the degree of parallelism that 1, w is actual employing, maximum parallelism degree P=r-q, w is not more than P, so w+q is not more than r.
Based on above-mentioned general multichannel recurrence formula, in conjunction with the embodiment with reference to figure 2, the corresponding general scrambler sequence generation device that walks abreast comprises r register and w recursive operation unit.R register is designated as respectively: 0 ~ r-1 register, and each register includes Q end (output), D end (input) and CLK end (clock end).W recursive operation unit is designated as respectively: 0 ~ w-1 recursive operation unit, for completing mould two add operation.
Wherein, corresponding power term coefficient is not that the Q end of i-th ~ i+q register of 0 holds with the Q of No. i-th register the input being simultaneously linked into No. i-th recursive operation unit, i is that the integer of 0 to w-1 is enumerated, and q is that in M sequence recurrence formula, coefficient is not the sequence number of the highest power item correspondence of 0.No. i-th recursive operation unit is for completing the computing of the i-th road recurrence formula, and the output of No. i-th recursive operation unit connects the D end of the i-th+r-w register, forms first group of feedback line.On the other hand, the Q end of jth+w register connects the D end of jth register, forms second group of feedback line.Wherein j is that the integer of 0 to r-w-1 is enumerated.
In addition, in the present embodiment, the Q of 0 ~ w-1 register holds the output as scrambler position, each cycle parallel output w position scrambler.In another embodiment, also can with the output of the output of 0 ~ w-1 recursive operation unit as scrambler position.
In above-described embodiment, because the time delay generating the new scrambler in w position is identical, therefore, it is possible to avoid limiting hardware frequency because of wooden pail effect, contribute to the generating rate improving parallel disturbance code further.
According to another embodiment of the invention, the parallel disturbance code sequence that the vectorial DSP providing a kind of SIMD of utilization structure realizes first via M sequence in LTE system based on program produces, and the program command that Fig. 3 shows this device performs schematic diagram.For parallelization software programming, need software environment support vector memory access mechanism and vector operation mechanism, for the present embodiment, degree of parallelism w=16, should need software environment at least support vector width be vectorial memory access and the vector calculation of 16, namely a software instruction can read while write 16 data from internal memory, and 16 data in two vector registors also can be allowed to participate in computing, and namely the vectorial DSP with SIMD structure meets above-mentioned requirements simultaneously.Utilize software programming, first, by twice vectorial reading command, from internal memory, read w (namely 16) individual data respectively in vector registor vr1 and vr2, the numbering of reading in the data of vr1 and vr2 is respectively 0 ~ w-1 (namely 0 ~ 15) and q ~ w+q-1 (namely 3 ~ 18) at every turn.Secondly, by a vectorial xor operation instruction, respectively xor operation is carried out to w (namely 16) the individual data in two vector registors, can obtain the part scrambler sequence that length is w (namely 16), the part scrambler sequence of gained is stored in another vector registor vr3.Finally, store instruction by a vector, the part scrambler sequence in vr3 is stored into the correspondence position of internal memory.Utilize this method to carry out multi-pass operation, can Parallel Implementation scrambler sequence produce.
In LTE system the hardware of the second M sequence or software simulating consistent with the first M sequence principle, be not repeated here.
Finally it should be noted that, above embodiment is only in order to describe technical scheme of the present invention instead of to limit this technical method, the present invention can extend in application other amendment, change, application and embodiment, and therefore think that all such amendments, change, application, embodiment are all in spirit of the present invention and teachings.
Claims (9)
1. M sequence walks abreast a production method, it is characterized in that, comprises the following steps:
1) obtain the recurrence formula of M sequence, determine degree of parallelism w, input initial M sequence position as initial known M sequence position set;
2) from the set of known M sequence position, the synchronous known M sequence position of w group of reading, as input data, is synchronously carried out w road recurrence calculation according to recurrence formula, is obtained original w unknown M sequence position; Wherein, one group of known M sequence position is corresponding to each power item on the right side of the recurrence formula of a road recurrence calculation;
3) by step 2) w M sequence position calculating add the set of known M sequence position, and this w M sequence bit synchronization exported, and then re-executes step 2) to calculate the M sequence position of w the unknown of next group.
2. M sequence according to claim 1 walks abreast production method, it is characterized in that, described step 1) in, described degree of parallelism w is not more than maximum parallelism degree P=r-q, wherein r represents the exponent number of described recurrence formula, and q represents the sequence number of the highest power item in the right side of recurrence formula.
3. M sequence according to claim 2 walks abreast production method, it is characterized in that, described step 1) in, described M sequence is the first M sequence in LTE protocol or the second M sequence in LTE protocol.
4. one kind to walk abreast generation device for realizing the walk abreast M sequence of production method of M sequence described in claim 1, wherein, the exponent number of the recurrence formula of M sequence is r, the sequence number of the highest power item in right side of recurrence formula is q, then the described M sequence generation device that walks abreast comprises r the register being designated as 0 ~ r-1 register respectively, and remember w recursive operation unit of 0 ~ w-1 recursive operation unit respectively, wherein w is not more than maximum parallelism degree P=r-q, and r, q, w are natural number;
Wherein, each register includes output, input and clock end; Corresponding power term coefficient is not the input that the output of i-th ~ i+q register of 0 and the output of No. i-th register are linked into No. i-th recursive operation unit simultaneously, No. i-th recursive operation unit is for completing the computing of the i-th road recurrence formula, and the output of No. i-th recursive operation unit connects the input of the i-th+r-w register, form first group of feedback line, wherein i is that the integer of 0 to w-1 is enumerated;
The output of jth+w register connects the input of jth register, forms second group of feedback line, and wherein j is that the integer of 0 to r-w-1 is enumerated.
5. M sequence according to claim 4 walks abreast generation device, it is characterized in that, the output of described 0 ~ w-1 register is as the output of M sequence position.
6. M sequence according to claim 5 walks abreast generation device, it is characterized in that, described 0 ~ w-1 register each cycle parallel output w position M sequence code.
7. a M sequence walks abreast production method, described M sequence walks abreast production method based on the vectorial DSP realization with SIMD structure, wherein, the exponent number of the recurrence formula of M sequence is r, the sequence number of the highest power item in right side of recurrence formula is q, then in DSP, the vector length of vector instruction is that w, w are not more than maximum parallelism degree P=r-q, wherein, r, q, w are natural number;
The described M sequence production method that walks abreast comprises the following steps:
1) from internal memory, read the known M sequence position of w group respectively by repeatedly vectorial reading command and read in data vector register at least two, wherein, read in data vector register described in each and receive w known M sequence position;
2) then by vectorial xor operation instruction, xor operation is carried out to the data that described at least two read in data vector register and obtain w new M sequence position, and vectorial xor operation result write is exported data vector register;
3) storing instruction by exporting the data buffer storage of data vector register to the relevant position in internal memory by vector, then returning step 1), start the calculating carrying out next group M sequence position.
8. M sequence according to claim 7 walks abreast production method, and it is characterized in that, described M sequence is the first M sequence in LTE protocol or the second M sequence in LTE protocol.
9. M sequence according to claim 7 walks abreast production method, it is characterized in that, described step 3) also comprise: stored by vector instruction by the data buffer storage that exports data vector register to the relevant position in internal memory while, by w M sequence position output of institute's buffer memory in internal memory.
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WO2018076894A1 (en) * | 2016-10-31 | 2018-05-03 | 深圳市中兴微电子技术有限公司 | Method and device for obtaining pseudo-random sequence and storage medium |
CN110310705A (en) * | 2018-03-16 | 2019-10-08 | 北京哲源科技有限责任公司 | Support the sequence alignment method and device of SIMD |
CN110310705B (en) * | 2018-03-16 | 2021-05-14 | 北京哲源科技有限责任公司 | Sequence comparison method and device supporting SIMD |
CN110457008A (en) * | 2018-05-08 | 2019-11-15 | 北京松果电子有限公司 | M-sequence generation method, device and storage medium |
CN110457008B (en) * | 2018-05-08 | 2021-08-03 | 北京小米松果电子有限公司 | m sequence generation method, device and storage medium |
EP3817251A4 (en) * | 2018-06-28 | 2021-08-25 | ZTE Corporation | Data processing method, device, and computer-readable storage medium |
CN110943955A (en) * | 2019-10-31 | 2020-03-31 | 北京时代民芯科技有限公司 | Method for generating parallel scrambler |
CN110943955B (en) * | 2019-10-31 | 2022-06-28 | 北京时代民芯科技有限公司 | Method for generating parallel scrambler |
WO2022128086A1 (en) * | 2020-12-16 | 2022-06-23 | Telefonaktiebolaget Lm Ericsson (Publ) | Bit sequence generation |
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