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CN105226089B - A kind of igbt chip and preparation method thereof - Google Patents

A kind of igbt chip and preparation method thereof Download PDF

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Publication number
CN105226089B
CN105226089B CN201510727727.4A CN201510727727A CN105226089B CN 105226089 B CN105226089 B CN 105226089B CN 201510727727 A CN201510727727 A CN 201510727727A CN 105226089 B CN105226089 B CN 105226089B
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Prior art keywords
igbt
igbt device
trap
well
forms
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CN105226089A (en
Inventor
谭灿健
罗海辉
黄建伟
刘国友
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Zhuzhou CRRC Times Electric Co Ltd
Zhuzhou CRRC Times Semiconductor Co Ltd
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Zhuzhou CSR Times Electric Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66325Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333Vertical insulated gate bipolar transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a kind of production methods of igbt chip, comprising: by way of ion implanting, boron is injected into IGBT device;High annealing is carried out to the IGBT device, activation is injected into the boron of the IGBT device, and boron is made to reach the predetermined depth of the IGBT device, forms p-well;Phosphorus is injected into the predetermined position under the p-well in such a way that energetic ion injects, and carries out high energy phosphorus described in high-temperature annealing activation, forms the N trap of the IGBT device.In addition to this, the invention also discloses a kind of igbt chips, and using the production method of such as above-mentioned igbt chip, including p-well, N trap and base area, the N trap is set between the p-well and the base area.The igbt chip improves the locomotivity of carrier in channel, reduces threshold voltage, reduce long process deviation and time cost, improve process efficiency, reduce process costs by making the higher N trap of impurity concentration between p-well and base area.

Description

A kind of igbt chip and preparation method thereof
Technical field
The present invention relates to semiconductor device technology manufacturing fields, more particularly to a kind of igbt chip and preparation method thereof.
Background technique
IGBT (Insulated Gate Bipolar Transistor), insulated gate bipolar transistor, due to having concurrently Of both the low conduction voltage drop of the high input impedance and BJT (Bipolar Transistor, bipolar junction transistor) of MOSFET Advantage.In converter system such as alternating current generator, frequency converter, Switching Power Supply, lighting circuit, the traction that DC voltage is 600V or more The fields such as transmission are widely applied.
It is all first to carry out trap to be injected into surface in the production method of existing IGBT (insulated gate bipolar transistor) trap, Then the depth of design is advanced to by a high position, so surface concentration highest, it is lower more to arrive bottom.But the concentration of surface impurity Height causes the threshold voltage of device that can not lower, and the locomotivity of carrier is also affected in channel, while between trap Isolation can also have a significant impact to device performance.
Summary of the invention
The object of the present invention is to provide a kind of igbt chips and preparation method thereof, and device threshold voltage is effectively reduced, and improve The mobility of carrier enhances the isolating power of trap, reduces leakage current;And the concentration and depth of trap are all easily controlled, It can be reduced Long Time Thermal process bring process deviation and time cost.
In order to solve the above technical problems, the embodiment of the invention provides a kind of production methods of igbt chip, comprising:
Step 1, by way of ion implanting, boron is injected into IGBT device;
Step 2 carries out high annealing to the IGBT device, and activation is injected into the boron of the IGBT device, and reaches boron To the predetermined depth of the IGBT device, p-well is formed;
Step 3, the predetermined position being injected into phosphorus in such a way that energetic ion injects under the p-well, and carry out high temperature Annealing activates the phosphorus, forms the N trap of the IGBT device;
Wherein, the N trap and the p-well form inversion type PN junction potential barrier.
Wherein, after the step 3, further includes:
Step 4 is doped the area N+ of the IGBT device, forms the emitter of the IGBT device.
Wherein, after the step 4, further includes:
Step 411 carries out the processing of spacer medium layer process to the IGBT device, forms spacer medium layer, and connect The contact hole is opened in contact hole photoetching;
Step 412 carries out smithcraft processing to the IGBT device, forms metal layer, goes forward side by side row metal photoetching and quarter The emitter and grid are drawn, are passivated technique, protect the front of the IGBT device by erosion.
Wherein, after the step 412, further includes:
Step 413, the back side of the IGBT device is carried out it is thinned, wherein to the IGBT device of 650V, thinned is final With a thickness of 50 μm -100 μm;To the IGBT device of 1200V, thinned final thickness is 100 μm -170 μm;To the IGBT of 1700V Device, final thickness are 170 μm -250 μm;To 2500V IGBT device, thinned final thickness is 250 μm -350 μm;It is right The IGBT device of 3300V, thinned final thickness are 350 μm -450 μm;To 4500V IGBT device, thinned final thickness is 450μm-600μm;To the IGBT device of 6500V, thinned final thickness is 600 μm -800 μm.
Wherein, after the step 413, further includes:
Step 414 carries out back side P+ injection, activation propulsion, metallization process to the IGBT device, forms back side current collection Pole and metal layer on back.
Wherein, after the step 4, further include
Step 421 carries out P+ injection in the back side to the IGBT device and anneals, and forms the backside collector of IGBT device.
Wherein, after the step 421, further includes:
Step 422 handles the spacer medium layer process of the IGBT device, forms spacer medium layer, and contacted The contact hole is opened in hole photoetching;
Step 423 carries out smithcraft processing to the IGBT device, forms metal layer, goes forward side by side row metal photoetching and quarter The emitter and grid are drawn, are passivated technique, protect the front of the IGBT device by erosion.
Wherein, after the step 423, further includes:
Step 424 carries out back side metallization technology to the IGBT device, forms backside collector metal layer.
In addition to this, the embodiment of the invention also discloses a kind of igbt chips, using IGBT as described in any one of the above embodiments Chip manufacture method, including p-well, N trap and base area, the N trap are set between the p-well and the base area.
Igbt chip production method and igbt chip provided by the embodiment of the present invention have compared with prior art Following advantages:
The embodiment of the invention provides igbt chip production method, comprising:
Step 1, by way of ion implanting, boron is injected into IGBT device;
Step 2 carries out high annealing to the IGBT device, and activation is injected into the boron of the IGBT device, and reaches boron To the predetermined depth of the IGBT device, p-well is formed;
Step 3, the predetermined position being injected into phosphorus in such a way that energetic ion injects under the p-well, and carry out high temperature Annealing activates the high energy phosphorus, forms the N trap of the IGBT device;
Wherein, the N trap and the p-well form inversion type PN junction potential barrier.
The igbt chip forms by the way that N trap is arranged between p-well and base area and is inverted well structure, so that igbt chip exists The potential barrier that a non-equilibrium hole enters p-well region is increased when conducting, avoids that device surface impurity concentration is excessively high to lead to threshold value The drawbacks of voltage can not lower improves the locomotivity of carrier in channel, while using the mode of high energy ion implantation, reducing Long Time Thermal process bring process deviation and time cost, improve process efficiency, reduce process costs.
Since the retrograde well bottom concentration of N-type is high, have some foreign ions inside trap just by it is compound fall, will not go to It is gone inside substrate, and since N trap concentration improves, the PN junction depletion width between N trap and p-well narrows, and the intensity of trap obtains Reinforce, improve the isolating power of p-well and N trap, reduces electric leakage.
The production of traditional handicraft N trap is all first to carry out trap to be injected into surface, is then advanced to design by long-time high temperature Depth, heat budget is big, and the inversion N trap in the present invention be can be obtained after being directly injected by short time high annealing it is required N well structure, the increased heat budget of institute is almost negligible to be disregarded;Since traditional handicraft is using injection pusher into forming N trap and P Trap, necessarily the big bottom concentration of p-well surface concentration is small, and the inversion N trap in the present invention can avoid to device surface impurity concentration Influence, N trap concentration can control arbitrarily;The surface concentration of traditional handicraft p-well is big, and threshold voltage is higher, carrier locomotivity It is restricted, and the inversion N trap in the present invention can reduce device threshold voltage, improve carrier locomotivity.
In conclusion igbt chip provided by the present invention and preparation method thereof, the side injected by using energetic ion Formula, which is formed, is inverted N trap, reduces threshold voltage, improves the locomotivity of carrier in channel, reduces Long Time Thermal process band The process deviation and time cost come, improves process efficiency, reduces process costs.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention Some embodiments for those of ordinary skill in the art without creative efforts, can also basis These attached drawings obtain other attached drawings.
Fig. 1 is the step schematic diagram of the manufacturing method of igbt chip provided by the embodiment of the present invention;
Fig. 2 is the vertical section structure schematic diagram of igbt chip provided by the embodiment of the present invention.
Specific embodiment
Just as described in the background section, the system of existing IGBT (insulated gate bipolar transistor) trap in the prior art Make in method, is all first to carry out trap to be injected into surface, the depth of design is then advanced to by a high position, so p-well surface concentration It is lower more to arrive bottom for highest.But the concentration height of surface impurity causes the threshold voltage of device that can not lower, current-carrying in channel The locomotivity of son is also affected, while being isolated between N trap and p-well can also have a significant impact to device performance.
Based on this, the embodiment of the invention provides a kind of production methods of igbt chip, comprising:
Step 1, by way of ion implanting, boron is injected into IGBT device;
Step 2 carries out high annealing to the IGBT device, and activation is injected into the boron of the IGBT device, and reaches boron To the predetermined depth of the IGBT device, p-well is formed;
Step 3, the predetermined position being injected into phosphorus in such a way that energetic ion injects under the p-well, and carry out high temperature Annealing activates the high energy phosphorus, forms the N trap of the IGBT device;
Wherein, the N trap and the p-well form inversion type PN junction potential barrier.
In addition to this, the embodiment of the invention also provides one kind to go back igbt chip, using igbt chip as described above Production method, including p-well, N trap and base area, the N trap are set between the p-well and the base area
In conclusion igbt chip and preparation method thereof provided by the embodiment of the present invention, is infused by using energetic ion The mode entered forms N trap between p-well and base area, that is, forms N-type and be inverted N well structure, so that igbt chip increases in conducting One non-equilibrium hole enters the potential barrier of p-well region, avoids that device p-well surface impurity concentration is excessively high causes threshold voltage can not The drawbacks of lowering reduces threshold voltage, improves the locomotivity of carrier in channel, while using the side of high energy ion implantation Formula reduces Long Time Thermal process bring process deviation and time cost, improves process efficiency, reduce process costs.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.
Detail is elaborated in the following description to fully understand the present invention.But the present invention can with it is a variety of not Other way described herein is same as to implement, those skilled in the art can do class without violating the connotation of the present invention Like popularization.Therefore the present invention is not limited to the specific embodiments disclosed below.
Referring to FIG. 1, Fig. 1 schemes the step of being the production method of the igbt chip provided by the embodiment of the present invention.
In a kind of concrete mode, the production method of the igbt chip, a kind of production method of igbt chip, comprising:
Step 1, by way of ion implanting, boron is injected into IGBT device;
Step 2 carries out high annealing to the IGBT device, and activation is injected into the boron of the IGBT device, and reaches boron To the predetermined depth of the IGBT device, p-well 11 is formed;
Step 3, the predetermined position being injected into phosphorus in such a way that energetic ion injects under the p-well, and carry out high temperature Annealing activates the high energy phosphorus, forms the N trap 12 of the IGBT device.
The production method of igbt chip N trap of the present invention, without using injection pusher into mode, formed one than lining The highly concentrated hole blocking layer in bottom.
After the completion of cellular 13 manufacturing process of grid of igbt chip, first with self-aligned technology, injects B (boron) and pass through High temperature promotes to form type p-well 11, then utilizes energetic ion injection technique, P (phosphorus) is injected into design position, and by short-term Between high-temperature annealing process make the P activation of injection, successfully realize and directly form a sky higher than substrate concentration in p-type trap periphery Cave barrier layer, i.e. N trap, next complete remaining technique by normal chip manufacturing process, obtain with the IGBT for being inverted well structure Chip.
The igbt chip forms by the way that N trap 12 is arranged between p-well and base area and is inverted well structure, so that igbt chip The potential barrier that a non-equilibrium hole enters 11st area of p-well is increased in conducting, avoids that device surface impurity concentration is excessively high to be caused The drawbacks of threshold voltage can not lower, reduces threshold voltage, improves the locomotivity of carrier in channel, uses simultaneously The mode of high energy ion implantation reduces Long Time Thermal process bring process deviation and time cost, improves process efficiency, reduce Process costs.
Since the retrograde well bottom concentration of N-type is high, have some foreign ions inside trap just by it is compound fall, will not go to Go inside substrate, and since 12 concentration of N trap improves, the PN junction depletion width between N trap 12 and p-well 11 narrows, trap it is strong Degree is strengthened, and the isolating power of p-well 11 and N trap 12 is improved, and reduces electric leakage.
The production of traditional handicraft N trap is all first to carry out trap to be injected into surface, is then advanced to design by long-time high temperature Depth, heat budget is big, and the inversion N trap in the present invention be can be obtained after being directly injected by short time high annealing it is required N well structure, the increased heat budget of institute is almost negligible to be disregarded;Since traditional handicraft is using injection pusher into forming N trap and P Trap, necessarily the big bottom concentration of p-well surface concentration is small, and the inversion N trap in the present invention can avoid to device surface impurity concentration Influence, N trap concentration can control arbitrarily;The surface concentration of traditional handicraft p-well is big, and threshold voltage is higher, carrier locomotivity It is restricted, and the inversion N trap in the present invention can reduce device threshold voltage, improve carrier locomotivity.
Certainly, generally can be after grid 13 manufacture completion, it, can also be in grid 13 before injection boron forms p-well 11 Upper surface grows one layer of polysilicon 14.
Due to N-type retrograde well bottom concentration height, have some foreign ions inside trap just by it is compound fall, will not go to serve as a contrast It is gone inside bottom, and since 12 concentration of N trap improves, the PN junction depletion width between N trap 12 and p-well 11 narrows, the intensity of trap It is strengthened, improves the isolating power of p-well 11 and N trap 12, reduce electric leakage.
In the manufacture craft of igbt chip, after the production for completing N trap 12, after the step 3, generally further include:
Step 4 is doped the area N+ of the IGBT device, forms the emitter of the IGBT device.
After completing the production of emitter of the IGBT device, first the IGBT device can be carried out behaviour is thinned Make, then carry out rear electrode production, manufacturing process is removed:
Wherein, after the step 4, further includes:
Step 411, the spacer medium layer process for carrying out the IGBT device form spacer medium layer, and carry out contact hole The contact hole is opened in photoetching;
Step 412 carries out smithcraft processing to the IGBT device, forms metal layer, goes forward side by side row metal photoetching and quarter The emitter and grid are drawn, are passivated technique, protect the front of the IGBT device by erosion.
Wherein, after the step 412, further includes:
Step 413, the back side of the IGBT device is carried out it is thinned, wherein to the IGBT device of 650V, thinned is final With a thickness of 50 μm -100 μm;To the IGBT device of 1200V, thinned final thickness is 100 μm -170 μm;To the IGBT of 1700V Device, final thickness are 170 μm -250 μm;To 2500V IGBT device, thinned final thickness is 250 μm -350 μm;It is right The IGBT device of 3300V, thinned final thickness are 350 μm -450 μm;To 4500V IGBT device, thinned final thickness is 450μm-600μm;To the IGBT device of 6500V, thinned final thickness is 600 μm -800 μm.
Wherein, after the step 413, further includes:
Step 414 carries out back side P+ injection, activation propulsion, metallization process to the IGBT device, forms back side current collection Pole and metal layer on back.
It should be noted that the present invention is not especially limited the thinned technique of the IGBT device.
It can also operate without thinning back side, directly be carried on the back after the production of the emitter of the IGBT device Face electrode fabrication, operating process are as follows;
Wherein, after the step 4, further include
Step 421 carries out P+ injection in the back side to the IGBT device and anneals, and forms the backside collector of IGBT device.
Wherein, after the step 421, further includes:
Step 422 carries out the processing of spacer medium layer process to the IGBT device, forms spacer medium layer, and connect The contact hole is opened in contact hole photoetching.
Step 423 carries out smithcraft processing to the IGBT device, forms metal layer, goes forward side by side row metal photoetching and quarter The emitter and grid are drawn, are passivated technique, protect the front of the IGBT device by erosion.
Wherein, after the step 423, further includes:
Step 424 carries out back side metallization technology processing to the IGBT device, forms backside collector metal layer.
It generally will also include BPSG technique in the manufacturing process of entire IGBT device, aluminium carried out after having beaten contact hole Sputtering and the techniques such as aluminium photoetching, the igbt chip eventually formed is as shown in Fig. 2, include being followed successively by emitter from top to bottom 19, polysilicon layer 14, grid 13, p-well 11, N trap 12, base area 15, buffer area 16, P+ layer 17 and collector 18,
After the production for completing igbt chip, it is also necessary to carry out getting scribing, test encapsulation ready.
In addition to this, the embodiment of the invention also discloses a kind of igbt chips, using igbt chip system as described above Make method, including p-well 11, N trap 12 and base area 15, the N trap 12 is set between the p-well 11 and the base area 15.
In conclusion igbt chip and preparation method thereof provided by the embodiment of the present invention, is infused by using energetic ion The mode entered forms N trap between p-well and base area, that is, forms N-type and be inverted well structure, so that igbt chip increases in conducting One non-equilibrium hole enters the potential barrier of p-well region, avoids that device p-well surface impurity concentration is excessively high causes threshold voltage can not The drawbacks of lowering improves the locomotivity of carrier in channel, while using the mode of high energy ion implantation, reducing Long Time Thermal Process bring process deviation and time cost, improve process efficiency, reduce process costs.
Igbt chip provided by the present invention and preparation method thereof is described in detail above.Tool used herein Principle and implementation of the present invention are described for body example, the above embodiments are only used to help understand this hair Bright method and its core concept.It should be pointed out that for those skilled in the art, not departing from the present invention , can be with several improvements and modifications are made to the present invention under the premise of principle, these improvement and modification also fall into right of the present invention It is required that protection scope in.

Claims (9)

1. a kind of production method of igbt chip characterized by comprising
Step 1, by way of ion implanting, boron is injected into IGBT device;
Step 2 carries out high annealing to the IGBT device, and activation is injected into the boron of the IGBT device, and boron is made to reach institute The predetermined depth of IGBT device is stated, p-well is formed;
Step 3, the predetermined position being injected into phosphorus in such a way that energetic ion injects under the p-well, and carry out high annealing The phosphorus is activated, the N trap of the IGBT device is formed;
Wherein, the N trap and the p-well form inversion type PN junction potential barrier.
2. the production method of igbt chip as described in claim 1, which is characterized in that after the step 3, further includes:
Step 4 is doped the area N+ of the IGBT device, forms the emitter of the IGBT device.
3. the production method of igbt chip as claimed in claim 2, which is characterized in that after the step 4, further includes:
Step 411 carries out the processing of spacer medium layer process to the IGBT device, forms spacer medium layer, and carry out contact hole The contact hole is opened in photoetching;
Step 412 carries out smithcraft processing to the IGBT device, forms metal layer, go forward side by side row metal photoetching and etching, will The emitter and grid are drawn, and are passivated technique, are protected the front of the IGBT device.
4. the production method of igbt chip as claimed in claim 3, which is characterized in that after the step 412, also wrap It includes:
Step 413, the back side of the IGBT device is carried out it is thinned, wherein to the IGBT device of 650V, thinned final thickness It is 50 μm -100 μm;To the IGBT device of 1200V, thinned final thickness is 100 μm -170 μm;To the IGBT device of 1700V, Final thickness is 170 μm -250 μm;To 2500V IGBT device, thinned final thickness is 250 μm -350 μm;To 3300V's IGBT device, thinned final thickness are 350 μm -450 μm;To 4500V IGBT device, thinned final thickness be 450 μm- 600μm;To the IGBT device of 6500V, thinned final thickness is 600 μm -800 μm.
5. the production method of igbt chip as claimed in claim 4, which is characterized in that after the step 413, also wrap It includes:
Step 414 carries out back side P+ injection, activation propulsion, metallization process processing to the IGBT device, forms back side current collection Pole and metal layer on back.
6. the production method of igbt chip as claimed in claim 2, which is characterized in that after the step 4, further include
Step 421 carries out P+ injection in the back side to the IGBT device and anneals, and forms the backside collector of IGBT device.
7. the production method of igbt chip as claimed in claim 6, which is characterized in that after the step 421, also wrap It includes:
Step 422 carries out the processing of spacer medium layer process to the IGBT device, forms spacer medium layer, and carry out contact hole The contact hole is opened in photoetching;
Step 423 carries out smithcraft processing to the IGBT device, forms metal layer, go forward side by side row metal photoetching and etching, will The emitter and grid are drawn, and are passivated technique, are protected the front of the IGBT device.
8. the production method of igbt chip as claimed in claim 7, which is characterized in that after the step 423, also wrap It includes:
Step 424 carries out back side metallization technology processing to the IGBT device, forms backside collector metal layer.
9. a kind of igbt chip, which is characterized in that the production side of the application such as described in any item igbt chips of claim 1-8 Method, including p-well, N trap and base area, the N trap are set between the p-well and the base area.
CN201510727727.4A 2015-10-29 2015-10-29 A kind of igbt chip and preparation method thereof Active CN105226089B (en)

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