CN105207669A - Method and circuit for reducing frequency source locking time - Google Patents
Method and circuit for reducing frequency source locking time Download PDFInfo
- Publication number
- CN105207669A CN105207669A CN201510510880.1A CN201510510880A CN105207669A CN 105207669 A CN105207669 A CN 105207669A CN 201510510880 A CN201510510880 A CN 201510510880A CN 105207669 A CN105207669 A CN 105207669A
- Authority
- CN
- China
- Prior art keywords
- loop filter
- frequency source
- frequency
- charge pump
- locking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention relates to a method and circuit for reducing frequency source locking time. The method comprises the following steps: before a first work time slot, a frequency source is started, the frequency of signals output by a frequency source circuit is enabled to be locked within a target frequency; after the first work time slot, the input end of a loop filter in a frequency source loop is switched to a high-resistance state so that charge released by the loop filter is alleviated; and before the next work time slot starts, a charge pump is connected with the loop filter and charges the loop filter until the target frequency is locked. According to the invention, through turning off the charge pump after the first work time slot, the output end and the input end of the loop filter are enabled to be at the high-resistance state, releasing of the charge is alleviated, and the loop filter is charged until the time for locking a needed charge amount is greatly reduced before the next work time slot; and at the same time, the charge in the loop filter is cyclically utilized so that power consumption is reduced.
Description
Technical field
The present invention relates to the frequency source in wireless communication RF circuit, more particularly, relate to a kind of method and the circuit that reduce frequency source locking time.
Background technology
This programme medium frequency source is realized by phase-locked loop, phase-locked loop (PLL:Phase-lockedloops) be a kind of utilize feedback control principle to realize frequency and the simultaneous techniques of phase place, its effect is that the clock that circuit exports is kept synchronous with the reference clock of its outside.When the frequency of reference clock or phase place change, phase-locked loop can detect this change, and carrys out regulation output frequency by the reponse system of its inside, until both re-synchronizations, to be thisly synchronously also called " phase-locked ".
In numerous phase-locked loop circuits, the advantages such as charge pump phase lock loop is easy to integrated with it, lock speed is fast, catching range is wide, become a kind of structure of extensive use.Passing judgment on one of Key Performance Indicator of phase-locked loop is locking time.The structural change mode that usual consideration reduces locking time has dynamic conditioning loop filter bandwidth, also has the method such as the range of linearity, increase charge pump initial state charge injection increasing voltage controlled oscillator in addition.
Along with the development of wireless communication technology, lead at TDMA (TimeDivisionMultipleAccess to the multi-slot transmitting/receiving wireless containing frequency generating units, time division multiple access) in system, more and more meticulousr to the division of time slot, this requires that frequency source can have the data transfer demands meeting stability and high efficiency faster locking time.And when frequency source broader bandwidth, different frequency conforming control lower locking time seems particularly important.Each frame of multi-time slot transceiver has several working time slot, and frequency source all needs the previous time slot T1 of operationally gap to terminate front locking, and when ensureing that working time slot T2 starts, frequency source is stablized.
When product powers on and starts shooting, carry out initialization to frequency source and join number, now namely frequency source enters operating state; All once number is joined to frequency source when each working time slot follow-up starts, make it be locked in target frequency; Loop filter is low resistive state always, until product is cut off the electricity supply, and frequency source power cut-off.
Carrying out charging to loop filter before the previous time slot that operationally gap starts terminates makes it be locked in target frequency, and after working time slot terminates, namely freedom of entry is discharged until electric charge discharges completely; Next time working time slot start front loop filter still charge to from 0V target frequency locking.The time that the method makes frequency source lock is longer.
Summary of the invention
The technical problem to be solved in the present invention is, provides a kind of method and the circuit that reduce frequency source locking time, for reducing the locking time of frequency source.
A kind of method reducing frequency source locking time of the present invention, comprises the steps:
Before first working time slot, initiation culture source, the signal frequency that described frequency source loop is exported is locked in target frequency;
After first working time slot terminates, the input of the loop filter in described frequency source is switched to high-impedance state, to slow down or to stop described loop filter to discharge electric charge;
Before subsequent work time slot starts, described charge pump is connected described loop filter and is charged to described loop filter, until the locking of described frequency source.
Preferably, the described input by the loop filter in described frequency source switches to high-impedance state, for: by turning off the connection between described loop filter and described charge pump, the input of described loop filter is switched to high-impedance state.
Preferably, the output load of described loop filter is high-impedance state, to slow down or to stop described loop filter to discharge electric charge.
Preferably, the input of the loop filter in described frequency source is switched to high-impedance state after also comprise the steps:
Before subsequent work time slot, retune receiver/transmitter work of being connected with described frequency source to specific channel.
Preferably, tuning described frequency source locks onto characteristic frequency required time and described charge pump to respond the time started to completing charging identical.
The present invention also provides a kind of circuit reducing frequency source locking time, comprise loop filter, voltage controlled oscillator, charge pump and processor, described charge pump is connected with described loop filter, and described loop filter is connected with described voltage controlled oscillator, also comprise phase discriminator
Described phase discriminator is connected with described processor and described voltage controlled oscillator, for the feedback signal that the standard signal and described voltage controlled oscillator that receive input export, and detect the phase difference value of described standard signal and described feedback signal, and the phase difference value detected is converted into phase signal exports described processor to;
Described processor is connected with described charge pump, for connection and the shutoff of described charge pump and described loop filter, and control according to the phase signal that described phase discriminator exports the quantity of electric charge that the adjustment of described charge pump exports described loop filter to, the frequency of input signal is made to equal the frequency outputed signal, frequency source loop-locking;
Preferably, when the connection between described loop filter and described charge pump turns off, the input of described loop filter then can switch to high-impedance state.
Preferably, the output load of described loop filter is high-impedance state, to slow down or to stop described loop filter to discharge electric charge.
Implement a kind of method and circuit reducing frequency source locking time of the present invention, there is following beneficial effect: when frequency source first time starts, the signal frequency that frequency source exports is locked in first object frequency, after working time slot terminates, the input of loop filter is switched to high-impedance state, thus avoid loop filter electric discharge and cause the loss of electric charge, upper before once working time slot starts, the charge pump be connected with loop filter charges to loop filter, owing to also remaining with electric charge in loop filter after a upper working time slot terminates, so the time that charge pump charges to required for lock onto target frequency to loop filter can reduce, the required quantity of electric charge also reduces, thus also reduce power consumption.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 is the structural representation that the present invention reduces the circuit of frequency source locking time;
Fig. 2 is the method flow schematic diagram that the present invention reduces frequency source locking time;
Fig. 3 is the circuit diagram of the output of loop filter of the present invention;
Fig. 4 is phase-locked loop chip external circuits schematic diagram of the present invention;
Fig. 5 a is first embodiment of the invention medium frequency source locking process schematic diagram;
Fig. 5 b is second embodiment of the invention medium frequency source locking process schematic diagram;
Fig. 6 a is the test result figure adopting prior art to carry out high-frequency locking in the present invention;
Fig. 6 b is the test result figure adopting prior art to carry out low frequency locking in the present invention;
Fig. 7 a is the test result figure carrying out high-frequency locking in the present invention in the first embodiment;
Fig. 7 b is the test result figure carrying out low frequency locking in the present invention in the first embodiment;
Fig. 8 a is the test result figure carrying out high-frequency locking in the present invention in the second embodiment;
Fig. 8 b is the test result figure carrying out low frequency locking in the present invention in the second embodiment.
Embodiment
As shown in Figure 1, in circuit first embodiment of reduction frequency source of the present invention locking time, the circuit reducing frequency source locking time comprises loop filter 1, voltage controlled oscillator 2, phase discriminator 3, charge pump 4, processor 5.
Phase discriminator 3 is connected with the output of processor 5 and voltage controlled oscillator 2, for the feedback signal of the output of the standard signal and voltage controlled oscillator 2 that receive input, and detect the phase difference value of input signal and output signal, and the phase difference value detected is converted into phase signal exports processor 5 to.Here, standard signal refers to standard clock signal.Processor 5 is connected with charge pump 4, for controlling connection between charge pump 4 and loop filter 1 and shutoff, and the phase signal also for exporting according to phase discriminator 3 controls the quantity of electric charge that charge pump 4 is adjusted to loop filter 1, when the frequency of the feedback signal that the frequency of input signal exports higher than voltage controlled oscillator 2, control charge pump 4 and increase the quantity of electric charge exporting loop filter 1 to, to improve the frequency of the feedback signal that voltage controlled oscillator 2 exports, the frequency of the standard signal inputted is made to equal the frequency of the feedback signal exported, the phase difference of the standard signal of input and the feedback signal of output maintains fixed value, frequency source loop-locking.
When the frequency of the standard signal inputted is less than the frequency of the feedback signal of output, processor 5 controls charge pump 4 and suspends to loop filter 1 output charge, the now of short duration electric discharge of loop filter, to reduce the frequency of the signal that voltage controlled oscillator 2 exports, the frequency of the standard signal inputted is made to equal the frequency of the feedback signal exported, the phase difference of the standard signal of input and the feedback signal of output maintains fixed value, frequency source loop-locking.
Further, processor 5 can be register, by being configured data to this register, control this register and produce control command, control connecting or disconnecting between charge pump 4 and loop filter 1, here, processor 5 periodically controls the connecting and disconnecting of charge pump 4, operationally before gap, connect loop filter 1 and charge for loop filter 1, operationally gap terminates rear disconnection, and the output pin that charge pump 4 is connected with loop filter 1 switches to high-impedance state, and the speed of the release electric charge of loop filter 1 is slowed down greatly.When connection between loop filter 1 and charge pump 4 turns off, the input of loop filter 1 then can switch to high-impedance state.
The electric charge that loop filter 1 exports for receiving charge pump 4, forms the control voltage to voltage controlled oscillator 2 after carrying out filtering and charge accumulated, control the frequency that voltage controlled oscillator 2 outputs signal.Wherein, the output of loop filter 1 is high-impedance state, with slow down or stop loop filter 1 operationally gap terminate rear release electric charge, the electric charge stored in the loop filter 1 of simultaneously can be recycled.Such as, as shown in Figure 3, between loop filter 1 and voltage controlled oscillator 2, be in series with resistance, electric capacity successively, an end of variable capacitance diode be connected between electric capacity and resistance, other end ground connection.The wherein change of voltage that exports along with loop filter of variable capacitance diode and embody different capacitance, form a variable capacitance with change in voltage, the electric capacity of series connection plays the effect of isolated DC.
As shown in Figure 4, Fig. 4 is phase-locked loop chip external circuits schematic diagram, the pump current output terminal being connected phase-locked loop chip internal charge pump 4 by the interface 3 of phase-locked loop chip is also charge pump outputs, and the 6th interface access analog power of phase-locked loop chip, the 0th interface accesses digital power and ground connection.
As shown in Figure 2, in the first embodiment of reduction frequency source method locking time of the present invention, comprise the steps:
S1. before the first working time slot, powered on by plug-in control frequency source, with initiation culture source, the signal frequency that frequency source is exported is locked in target frequency.Certainly in another embodiment, by manually connecting frequency source, frequency source electrifying startup can also be made.
Particularly, the feedback signal that the standard signal of input and collection voltage controlled oscillator 2 export is inputed to phase discriminator 3 simultaneously, phase discriminator 3 detects the phase signal between output signal and input signal, export the phase signal detected to processor 5, processor 5 controls the discharge and recharge of charge pump 4 pairs of loop filters 1, the frequency that voltage controlled oscillator 2 adjustment is outputed signal is consistent with the frequency of input signal, makes frequency source loop-locking.
S2. after the first working time slot terminates, the input of the loop filter 1 in frequency source is switched to high-impedance state, loop filter 1 is slowed down or stops discharging electric charge.
Particularly, by turning off the connection between loop filter 1 and charge pump 4, the input of loop filter 1 is switched to high-impedance state, and the output load of loop filter 1 itself is high-impedance state, loop filter 1 is hindered to discharge electric charge, make after operationally gap terminates, loop filter 1 externally discharges hardly, the quantity of electric charge in loop filter 1 approximately can be maintained state when being in working time slot.Certainly, in another embodiment, also can access a high resistance measurement between loop filter 1 and charge pump 4, make the input of loop filter 1 switch to high-impedance state.
S3. before subsequent work time slot, harmonic ringing is regenerated by processor 5, and export charge pump 4 to, after the harmonic ringing that charge pump 4 receiving processor 5 exports, loop filter 1 is charged, thus loop filter 1 forms the tuning control voltage acting on voltage controlled oscillator 2, voltage controlled oscillator 2 produces specific frequency according to control voltage, again the tuning specific frequency making frequency source work, makes the receiver/transmitter be connected with the voltage controlled oscillator 2 of frequency source to specific channel.Wherein, processor 5 regenerates harmonic ringing, it is identical that control voltage controlled oscillator 2 tuned receivers/transmitter responds to characteristic frequency required time and charge pump 4 time started to completing charging, so just, make after each working time slot terminates, the time consistency of loop filter 1 slow releasing electric charge, thus the quantity of electric charge discharged is also consistent, thus it is also consistent to charge to time needed for locking by charge pump 4 before subsequent work time slot, so lock required time consistency in same communication process.
Next time working time slot start before reset Configuration Data in processor 5, tuned frequency source circuit to specific frequency, to guarantee that receiver/transmitter is operated in specific channel.In processor 5, input instruction be operated in specific frequency to control voltage controlled oscillator 2, thus make receiver/transmitter be operated in the process of specific channel, loop filter 1 produces the tuning control voltage acting on voltage controlled oscillator 2 according to the harmonic ringing received, this process loops filter 1 can discharge a small amount of electric charge.
S4., before subsequent work time slot starts, the charge pump control unit 51 in processor 5 controls connect between charge pump 4 and loop filter 1 and charge to loop filter 1, until frequency source relocks.Due to after a upper working time slot terminates, high-impedance state is at the input of loop filter 1 and output, loop filter just discharges electric charge more lentamente and goes out a small amount of electric charge, so also preserve most electric charge in loop filter 1, before subsequent work time slot starts, charge pump 4 recloses loop filter 1 and charges to loop filter 1, when charge pump 4 charges to output signal to loop filter 1 is locked in the quantity of electric charge needed for target frequency, the time can increasing and reduce accordingly with the quantity of electric charge preserved in original loop filter.
The present invention also provides the second embodiment, in a second embodiment, selects successively to perform above-mentioned step S1, S2, S4.In above-mentioned steps, if do not perform step S3, then charge pump 4 response time shortens greatly, then the amount that loop filter 1 discharges electric charge also greatly reduces, before upper once working time slot, utilize charge pump 4 to charge, it is consistent and be exceedingly fast that each working time slot starts front locking time; Now locking time is faster than the first embodiment, and for different frequent points, locking time is consistent; Also save the energy consumption in frequency source locking process greatly simultaneously.Certainly, performing step S3 and mainly prevent phase-locked loop chip from makeing mistakes in the process of locking, in order to prevent makeing mistakes in phase-locked loop chip locking process, can select to perform step S3; Certainly, the phase-locked loop chip possibility of makeing mistakes in actual lock process is minimum.
As shown in Figure 5 a, in a first embodiment, after the second working time slot T2 terminates, charge pump 4 is connected and is charged to loop filter 1 by the t0 time period before the 3rd working time slot starts, simultaneously to frequency source configuration data, before each working time slot after the first working time slot, the electricity that loop filter 1 discharges is consistent, such as be 0.8V, so in a same communication process, the time consistency of frequency source locking.
As shown in Figure 5 b, in a second embodiment, only t0 time period configuration data before the first working time slot T1, and before the second working time slot T2 below the t0 time period just charge pump 4 is connected, charge to loop filter 1.Performing step S4 makes loop filter 1 increase the quantity of electric charge of release, and before subsequent work time slot, when utilizing charge pump 4 to charge, the amplitude that the time charging to the quantity of electric charge required for locking reduces also can increase relatively.
As shown in figures 6 a and 6b, Fig. 6 a adopts prior art to carry out first frequency locking, and the time needed for correspondence is approximately 4.0mS, Fig. 6 b is adopt prior art to carry out second frequency locking, and the time needed for correspondence is approximately 3.0mS.As shown in figs. 7 a and 7b, Fig. 7 a carries out first frequency locking in the first embodiment, and the time needed for correspondence is approximately 3.0mS, Fig. 7 b is carry out second frequency locking in the first embodiment, and the time needed for correspondence is approximately 3.0mS.As figures 8 a and 8 b show, Fig. 8 a carries out first frequency locking in the second embodiment, and the time needed for correspondence is approximately 2.4mS, Fig. 8 b is carry out second frequency locking in the second embodiment, and the time needed for correspondence is approximately 2.2mS.In sum, when frequency source locks, when target frequency not for the moment, also not necessarily, locking time, speed differed required charge volume; Simultaneously due to after each working time slot terminates, in loop filter, stored energy all discharges, and charge from 0 again before working time slot, electric charge has certain waste, also can increase the time needed for locking next time.
By method and the circuit of reduction frequency source locking time of above-described embodiment, after the first working time slot terminates, by turning off the charge pump 4 be connected with loop filter 1, the input of loop filter 1 is switched to high-impedance state, the output of loop filter is originally as high-impedance state simultaneously, so just greatly slow down loop filter 1 and operationally discharge electric charge after gap, avoid causing the waste to electric charge, before subsequent work time slot, the quantity of electric charge stored in loop filter 1 can reduce a little, restart the connection between charge pump 4 and loop filter 1 again, charge pump 4 starts as loop filter 1 charges, the quantity of electric charge current from loop filter 1 charges to the time of the quantity of electric charge needed for lock onto target frequency, can greatly reduce relative to the time needed for the quantity of electric charge charged to from 0 quantity of electric charge needed for lock onto target frequency, the required quantity of electric charge also reduces, thus also reduce power consumption.
Understandable, above embodiment only have expressed the preferred embodiment of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention; It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can carry out independent assortment to above-mentioned technical characterstic, can also make some distortion and improvement, these all belong to protection scope of the present invention; Therefore, all equivalents of doing with the claims in the present invention scope and modification, all should belong to the covering scope of the claims in the present invention.
Claims (8)
1. reduce the method for frequency source locking time, it is characterized in that, comprise the steps:
Before first working time slot, initiation culture source, the signal frequency that described frequency source loop is exported is locked in target frequency;
After first working time slot terminates, the input of the loop filter in described frequency source is switched to high-impedance state, to slow down or to stop described loop filter to discharge electric charge;
Before subsequent work time slot starts, described charge pump is connected described loop filter and is charged to described loop filter, until the locking of described frequency source.
2. the method for reduction frequency source according to claim 1 locking time, it is characterized in that, the described input by the loop filter in described frequency source switches to high-impedance state, for: by turning off the connection between described loop filter and described charge pump, the input of described loop filter is switched to high-impedance state.
3. the method for reduction frequency source according to claim 1 locking time, it is characterized in that, the output load of described loop filter is high-impedance state, to slow down or to stop described loop filter to discharge electric charge.
4. the method for the reduction frequency source locking time according to any one of claim 1-3, is characterized in that, also comprise the steps: after the input of the loop filter in described frequency source is switched to high-impedance state
Before subsequent work time slot, retune receiver/transmitter work of being connected with described frequency source to specific channel.
5. the method for reduction frequency source according to claim 4 locking time, is characterized in that, tuning described frequency source locks onto characteristic frequency required time and described charge pump, and to respond the time started to completing charging identical.
6. reduce the circuit of frequency source locking time, comprise loop filter, voltage controlled oscillator, charge pump and processor, described charge pump is connected with described loop filter, and described loop filter is connected with described voltage controlled oscillator,
It is characterized in that, also comprise phase discriminator,
Described phase discriminator is connected with described processor and described voltage controlled oscillator, for the feedback signal that the standard signal and described voltage controlled oscillator that receive input export, and detect the phase difference value of described standard signal and described feedback signal, and the phase difference value detected is converted into phase signal exports described processor to;
Described processor is connected with described charge pump, for connection and the shutoff of described charge pump and described loop filter, and control according to the phase signal that described phase discriminator exports the quantity of electric charge that the adjustment of described charge pump exports described loop filter to, the frequency of input signal is made to equal the frequency outputed signal, frequency source loop-locking.
7. the circuit of reduction frequency source according to claim 6 locking time, is characterized in that,
When connection between described loop filter and described charge pump turns off, the input of described loop filter then can switch to high-impedance state.
8. the circuit of reduction frequency source according to claim 6 locking time, is characterized in that,
The output load of described loop filter is high-impedance state, to slow down or to stop described loop filter to discharge electric charge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510510880.1A CN105207669A (en) | 2015-08-19 | 2015-08-19 | Method and circuit for reducing frequency source locking time |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510510880.1A CN105207669A (en) | 2015-08-19 | 2015-08-19 | Method and circuit for reducing frequency source locking time |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105207669A true CN105207669A (en) | 2015-12-30 |
Family
ID=54955148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510510880.1A Pending CN105207669A (en) | 2015-08-19 | 2015-08-19 | Method and circuit for reducing frequency source locking time |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105207669A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111327375A (en) * | 2018-12-14 | 2020-06-23 | 海能达通信股份有限公司 | Channel scanning method, communication terminal and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080106340A1 (en) * | 2006-10-20 | 2008-05-08 | Fci Inc. | Frequency synthesizer and frequency calibration method |
| US20080278248A1 (en) * | 2004-02-27 | 2008-11-13 | Sanyo Electric Co., Ltd | Pll Circuit |
| CN101888244A (en) * | 2010-07-16 | 2010-11-17 | 上海集成电路研发中心有限公司 | Low-power consumption phase-locked loop circuit |
| CN102210102A (en) * | 2008-11-12 | 2011-10-05 | 高通股份有限公司 | Techniques for minimizing control voltage ripple due to charge pump leakage in phase locked loop circuits |
| CN103957004A (en) * | 2014-04-16 | 2014-07-30 | 中科芯集成电路股份有限公司 | Phase-locked loop filter circuit applied to direct transmitter |
-
2015
- 2015-08-19 CN CN201510510880.1A patent/CN105207669A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080278248A1 (en) * | 2004-02-27 | 2008-11-13 | Sanyo Electric Co., Ltd | Pll Circuit |
| US20080106340A1 (en) * | 2006-10-20 | 2008-05-08 | Fci Inc. | Frequency synthesizer and frequency calibration method |
| CN102210102A (en) * | 2008-11-12 | 2011-10-05 | 高通股份有限公司 | Techniques for minimizing control voltage ripple due to charge pump leakage in phase locked loop circuits |
| CN101888244A (en) * | 2010-07-16 | 2010-11-17 | 上海集成电路研发中心有限公司 | Low-power consumption phase-locked loop circuit |
| CN103957004A (en) * | 2014-04-16 | 2014-07-30 | 中科芯集成电路股份有限公司 | Phase-locked loop filter circuit applied to direct transmitter |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111327375A (en) * | 2018-12-14 | 2020-06-23 | 海能达通信股份有限公司 | Channel scanning method, communication terminal and storage medium |
| CN111327375B (en) * | 2018-12-14 | 2022-06-24 | 海能达通信股份有限公司 | Channel scanning method, communication terminal and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5202906A (en) | Frequency divider which has a variable length first cycle by changing a division ratio after the first cycle and a frequency synthesizer using same | |
| CN102684685B (en) | Phase locked loop and method thereof | |
| US5475877A (en) | Mobile wireless set with improved intermittent operation control and reduced power consumption | |
| JP2001237699A5 (en) | ||
| CN102158221B (en) | Phase-locked loop and fast lockign apparatus thereof | |
| CN105577142A (en) | Clock duty cycle adjusting device and method | |
| CN101436859A (en) | Rapidly-locked frequency generator | |
| CN102122957A (en) | Phase-locking loop rapid locking circuit and method | |
| CN109547019B (en) | Double LC-VCO structure phase-locked loop applied to wide tuning range and calibration method | |
| CN101841229B (en) | External clock synchronizing device of switching power supply | |
| CN101409552B (en) | Phase-locked loop and control method utilizing the same | |
| CN103036446A (en) | Soft starting device and method for high-power transformer | |
| CN105610436B (en) | It is a kind of to have the adaptive charge pump phase lock loop for accelerating locking structure | |
| CN105207669A (en) | Method and circuit for reducing frequency source locking time | |
| CN104702271A (en) | Phase-locked loop circuit and calibration method for characteristic curves of voltage-controlled oscillator | |
| US11303284B1 (en) | Low-power fractional analog PLL without feedback divider | |
| KR101901321B1 (en) | Clock generation device and method thereof | |
| CN103166456B (en) | Charge pump circuit and phase-locked loop circuit | |
| US7283801B2 (en) | Circuit arrangement for phase locked loop, and phase locked loop based method to be used in cellular network terminals | |
| CN103618548B (en) | Frequency synthesis method and circuit based on rapid frequency locking of phase-locked loop | |
| CN108449085A (en) | Phaselocked loop and electronic system | |
| CN101414820A (en) | Digital frequency synthesis and synchronous circuit | |
| CN204886924U (en) | Frequency synthesizer with initial phase synchronization function | |
| CN103825611A (en) | Frequency correction circuit and method | |
| CN208046590U (en) | A kind of clock spectrum spreading circuit that can reduce EMI |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151230 |