CN105182833A - Double-power-supply power supply and power-off sequential control device and method - Google Patents
Double-power-supply power supply and power-off sequential control device and method Download PDFInfo
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- CN105182833A CN105182833A CN201510660897.5A CN201510660897A CN105182833A CN 105182833 A CN105182833 A CN 105182833A CN 201510660897 A CN201510660897 A CN 201510660897A CN 105182833 A CN105182833 A CN 105182833A
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Abstract
The invention relates to a double-power-supply power supply and power-off sequential control device and method. The device includes a PMOS field effect transistor, an NMOS field effect transistor, a first NPN triode, a second NPN triode, a PNP triode, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, all the hardware elements have specific connection relations, and positive and negative power supply turning-on and turning-off timing sequences are logically controlled through the hardware elements of the PMOS field effect transistor and the NMOS field effect transistor. The device avoids power supply and power-off timing errors of the positive and negative power supplies, thereby ensuring normal operation of equipment.
Description
Technical field
The present invention relates to the automatic monitoring technical fields such as the water conservancy hydrology, town and country flood control, communal facility safety, geologic hazard, be particularly applied to above-mentioned field and power without the negative and positive dual power of field data collection terminal device (hereinafter referred to as acquisition terminal or acquisition terminal equipment) that reliable source of power ensures and power-off time sequence control device and method.
Background technology
Under normal circumstances, the connection of positive supply, negative supply with shutoff sequential is: when opening power supply, first controls to connect positive supply, after wait positive voltage is set up and stablized, then controls to connect negative supply; During power cutoff, first turn off negative supply, wait for that negative supply voltage falls back in safe range, then control to turn off positive supply.
Usually, acquisition terminal performs relative program by inner MCU, controls opening of positive and negative power supply by the sequential control PIO port level of regulation and turns off sequential.But in the wild comparatively (thunderous electrical interference etc.) under bad electromagnetic environment, program may out of controlly cause positive-negative power connect and turn off sequential entanglement, making cmos device circuit in acquisition terminal produce bolt-lock effect causes circuit normally to work, and can damage acquisition terminal equipment time serious.
Summary of the invention
The present invention is directed to prior art by programmed control dual power supply and cut-out, cmos device bolt-lock may be caused even to damage the problem of acquisition terminal equipment because of program out of control compared with under bad electromagnetic environment in the wild, a kind of dual power supply and power-off time sequence control device are provided, control positive-negative power by hardware circuits such as PMOS field effect transistor and NMOS field effect transistor connect sequential and turn off sequential, this device can avoid positive and negative Power supply and power-off timing error, and guarantee equipment normally works.The invention still further relates to a kind of dual power supply and power-off sequential control method.
Technical scheme of the present invention is as follows:
A kind of dual power supply and power-off time sequence control device, it is characterized in that, comprise PMOS field effect transistor, NMOS field effect transistor, a NPN triode, the 2nd NPN triode, PNP triode, the first resistance, the second resistance, the first electric capacity, the second electric capacity, the 3rd electric capacity and the 4th electric capacity
Described PMOS field effect transistor is the control main switch of positive supply, and the source electrode of PMOS field effect transistor connects positive supply, and grid connects the collector of a NPN triode, and drain electrode connects positive supply and exports; Described NMOS field effect transistor is the control main switch of negative supply, and the source electrode of NMOS field effect transistor connects negative supply, and grid connects the collector of PNP triode, and drain electrode connects negative supply and exports; The base stage of a described NPN triode connects power switch control signal line, grounded emitter; The base stage of described PNP triode is connected with the collector of the 2nd NPN triode, the emitter of PNP triode connects one end of the first resistance and one end of the second resistance simultaneously, the other end ground connection of described first resistance, another termination positive supply of described second resistance exports; The base stage of described 2nd NPN triode connects power switch control signal line, grounded emitter;
Between the source electrode that described first electric capacity is arranged at PMOS field effect transistor and grid, described second electric capacity is arranged between the grid of PMOS field effect transistor and drain electrode, between the source electrode that described 3rd electric capacity is arranged at NMOS field effect transistor and grid, described 4th electric capacity is arranged between the grid of NMOS field effect transistor and drain electrode.
Described dual power supply and power-off time sequence control device also comprise the 3rd resistance, between the source electrode that described 3rd resistance and the first Capacitance parallel connection are arranged at PMOS field effect transistor and grid.
Described dual power supply and power-off time sequence control device also comprise the 4th resistance and the 5th resistance, the base stage of a described NPN triode connects power switch control signal line by the 4th resistance, the base stage of a described NPN triode also connects one end of the 5th resistance, the other end ground connection of described 5th resistance.
Described dual power supply and power-off time sequence control device also comprise the 6th resistance and the 7th resistance, the emitter of a described NPN triode to connect after the 6th resistance ground connection again, the emitter of a described NPN triode also connects one end of the 7th resistance, and the other end of described 7th resistance connects negative supply and exports.
Described dual power supply and power-off time sequence control device also comprise the 8th resistance, and described 8th resistance and the 3rd Capacitance parallel connection are between the source electrode and grid of NMOS field effect transistor.
Described dual power supply and power-off time sequence control device also comprise the 9th resistance, and the base stage of described 2nd NPN triode connects power switch control signal line by the 9th resistance.
A kind of dual power supply and power-off sequential control method, it is characterized in that, employing PMOS field effect transistor is the control main switch of positive supply, utilizes the grid of a NPN triode and first group of Capacity control PMOS field effect transistor and controls opening and disconnection of positive supply; Employing NMOS field effect transistor is the control main switch of negative supply, utilize the grid of PNP triode and second group of Capacity control NMOS field effect transistor and control negative supply and open and disconnection, between power switch control signal and PNP triode, adopt the 2nd NPN triode;
When opening power supply, power switch control signal makes a NPN triode ON and makes the conducting of PMOS field effect transistor to first group of capacitor charging with the source-gate voltage increasing PMOS field effect transistor, thus sets up positive supply output voltage; Power switch control signal controls the 2nd NPN triode ON simultaneously, when the positive voltage set up reaches unlatching negative supply threshold value, PNP triode conducting also makes the conducting of NMOS field effect transistor to second group of capacitor charging with the source-gate voltage increasing NMOS field effect transistor, thus sets up negative supply output voltage;
When turning off power supply, power switch control signal makes the 2nd NPN triode cut-off and then PNP triode cut-off, and second group of capacitance group electric discharge makes NMOS field effect transistor turn off with the source-gate voltage reducing NMOS field effect transistor, and negative supply output voltage gos up gradually to zero; Power switch control signal controls a NPN triode simultaneously and keeps conducting and then PMOS field effect transistor to keep conducting to maintain positive supply output voltage, negative supply output voltage go up gradually to zero time the one NPN triode cut-off, first group of capacitor discharge makes PMOS field effect transistor turn off with the source-gate voltage reducing PMOS field effect transistor, and positive supply output voltage makes zero gradually.
Utilize a NPN triode and first group of electric capacity and first group of resistance cooperating with the grid of control PMOS field effect transistor and control opening and disconnection of positive supply, and limiting the rush of current that positive supply opens moment; Utilize PNP triode and second group of electric capacity and second group of electric capacity cooperating with the grid of control NMOS field effect transistor and control negative supply and open and disconnection, and limiting the rush of current that negative supply opens moment.
When opening power supply, utilize the source-gate voltage of the Miller effect control PMOS field effect transistor of first group of electric capacity to increase gradually, make the slow conducting of PMOS field effect transistor; Utilize the source-gate voltage of the Miller effect control NMOS field effect transistor of second group of electric capacity to increase gradually, make the slow conducting of NMOS field effect transistor.
By MCU control power switch control signal level be logical one or negative supply output voltage effective time, open positive supply powered electronic switch; By MCU control power switch control signal level be logical one and positive supply output voltage is effective time, open negative supply powered electronic switch; Negative supply powered electronic switch is turned off when being logical zero by MCU control power switch control signal level; By MCU control power switch control signal level be logical zero and negative supply output voltage is invalid time, turn off positive supply powered electronic switch.
Technique effect of the present invention is as follows:
The dual power supply that the present invention relates to and power-off time sequence control device, comprise PMOS field effect transistor, NMOS field effect transistor, one NPN triode, 2nd NPN triode, PNP triode, first resistance, second resistance, first electric capacity, second electric capacity, the hardware element of the specific annexations such as the 3rd electric capacity and the 4th electric capacity, PMOS field effect transistor is the control main switch of positive supply, NMOS field effect transistor is the control main switch of negative supply, one NPN triode, first electric capacity and the second Capacity control PMOS fet gate, and control opening and disconnection of positive supply, PNP triode, first resistance, second resistance, 3rd electric capacity and the 4th Capacity control NMOS fet gate, and control opening and disconnection of negative supply.Connect sequential by each hardware element cooperating logic control positive-negative power such as PMOS field effect transistor and NMOS field effect transistor and turn off sequential, make when opening power supply, because positive supply output voltage is not set up, forbid opening negative supply, only have after positive voltage output voltage is built up, just open negative supply; When turning off power supply, because negative supply output voltage is not yet returned to zero, positive supply continues to keep open-minded, after negative supply output voltage returns zero, then turns off positive supply.Like this, sequential relationship strict when reliably keeping opening and turn off power supply, avoid prior art by programmed control dual power supply and cut-out can in the wild compared with under bad electromagnetic environment because program out of control may cause sequential entanglement and circuit for generating locking bolt even to damage the problem of acquisition terminal equipment, this device can avoid positive and negative Power supply and power-off timing error, avoid circuit locking bolt effect, guarantee equipment normally works.
Dual power supply of the present invention and power-off time sequence control device also arrange the 3rd resistance, when turning off power supply, the electric charge of the first electric capacity and the storage of the second electric capacity is by the 3rd conductive discharge, source-the gate voltage of PMOS field effect transistor is caused to reduce gradually again, when the source-gate voltage of PMOS field effect transistor is lower than its turn-on threshold voltage, PMOS field effect transistor turns off, positive supply output voltage is returned to zero, this structure is simple and easy to realize, by the hardware element logic control work be separated, ensure that dual power supply and power-off sequential accuracy.
The dual power supply that the present invention relates to and power-off sequential control method, corresponding with dual power supply of the present invention and power-off time sequence control device, can be regarded as is the method realizing above-mentioned dual power supply and power-off time sequence control device, or be interpreted as it is the method for work of above-mentioned dual power supply and power-off time sequence control device, employing PMOS field effect transistor is the control main switch of positive supply, utilizes the grid of a NPN triode and first group of Capacity control PMOS field effect transistor and controls opening and disconnection of positive supply; Employing NMOS field effect transistor is the control main switch of negative supply, utilize the grid of PNP triode and second group of Capacity control NMOS field effect transistor and control negative supply and open and disconnection, between power switch control signal and PNP triode, adopt the 2nd NPN triode; Detect power switch control signal and positive supply output voltage, negative supply output voltage by the hardware element be separated simultaneously, realize opening power supply at positive and negative power supply and turning off the accurate control of power supply timing, the normal work of guarantee equipment, overcome the drawback of prior art completely, improve the security performance of the application of automatic monitoring technical field such as the water conservancy hydrology, town and country flood control, communal facility safety, geologic hazard.
Accompanying drawing explanation
Fig. 1 is the preferred structure schematic diagram of dual power supply of the present invention and power-off time sequence control device.
Fig. 2 be dual power supply of the present invention and power-off time sequence control device open shutoff working timing figure.
Fig. 3 is the schematic diagram of dual power supply of the present invention and power-off sequential control method.
In figure, each label lists as follows:
ON_OFF-power switch; M1-PMOS field effect transistor; M2-NMOS field effect transistor; Q1-the one NPN triode; Q2-PNP triode; Q3-the 2nd NPN triode.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be described.
The invention discloses a kind of dual power supply and power-off time sequence control device, its preferred structure as shown in Figure 1, comprise PMOS field effect transistor M1, NMOS field effect transistor M2, one NPN triode Q1, PNP triode Q2, 2nd NPN triode Q3, first resistance R1, second resistance R2, first electric capacity C1, second electric capacity C2, 3rd electric capacity C3 and the 4th electric capacity C4, PMOS field effect transistor M1 is the control main switch of positive supply (+6V), the source electrode of PMOS field effect transistor M1 connects positive supply, grid connects the collector of a NPN triode Q1, drain electrode connects positive supply and exports, NMOS field effect transistor M2 is the control main switch of negative supply (-6V), and the source electrode of NMOS field effect transistor M2 connects negative supply, and grid connects the collector of PNP triode Q2, and drain electrode connects negative supply and exports, the base stage of the one NPN triode Q1 connects power switch ON_OFF control signal wire, grounded emitter, the base stage of PNP triode Q2 is connected with the collector of the 2nd NPN triode Q3, the emitter of PNP triode Q2 connects one end of the first resistance R1 and one end of the second resistance R2 simultaneously, the other end ground connection of the first resistance R1, another termination positive supply of the second resistance R2 exports, the base stage of the 2nd NPN triode Q3 connects power switch control signal line, grounded emitter, between the source electrode that first electric capacity C1 is arranged at PMOS field effect transistor M1 and grid, second electric capacity C2 is arranged between the grid of PMOS field effect transistor M1 and drain electrode, between the source electrode that 3rd electric capacity C3 is arranged at NMOS field effect transistor M2 and grid, the 4th electric capacity C4 is arranged between the grid of NMOS field effect transistor M2 and drain electrode.
The 3rd resistance R3 is also comprised in embodiment illustrated in fig. 1, 4th resistance R4, 5th resistance R5, 6th resistance R6, 7th resistance R7, 8th resistance R8 and the 9th resistance R9, 3rd resistance R3 and the first electric capacity C1 is arranged in parallel between the source electrode and grid of PMOS field effect transistor M1, the base stage of the one NPN triode Q1 connects power switch ON_OFF control signal wire by the 4th resistance R4, the base stage of the one NPN triode Q1 also connects one end of the 5th resistance R5, the other end ground connection of the 5th resistance R5, the emitter of the one NPN triode Q1 to connect after the 6th resistance R6 ground connection again, the emitter of the one NPN triode Q1 also connects one end of the 7th resistance R7, the other end of the 7th resistance R7 connects negative supply and exports, between the source electrode that 8th resistance R8 and the 3rd electric capacity C3 is parallel to NMOS field effect transistor M2 and grid, the base stage of the 2nd NPN triode Q3 connects power switch control signal line by the 9th resistance R9.
Dual power supply shown in Fig. 1 and power-off time sequence control device, PMOS field effect transistor M1 is the control main switch of positive supply (+6V); NMOS field effect transistor M2 is the control main switch of negative supply (-6V); Adopt a NPN triode Q1, resistance R3, R4, R5, R6, R7, electric capacity C1, C2 co-controlling PMOS field effect transistor M1 grid, control opening and disconnection of positive supply, and the rush of current of moment is opened in restriction; Adopt PNP triode Q2, resistance R1, R2, R8, electric capacity C3, C4 control NMOS field effect transistor M2 grid, control opening and disconnection of negative supply, and the rush of current of moment is opened in restriction.
The specific works of the present invention's device is as shown in Figure 1 as follows: when needing to open power supply, MCU control ON_OFF control signal is logical one (CMOS logic level, 3.3V), make a NPN triode Q1 conducting, charge to electric capacity C1, C2, PMOS field effect transistor M1 source-gate voltage increases gradually, and PMOS field effect transistor M1 gradually becomes conducting state by off state, and+6V output voltage of powering rises to+6V gradually by 0V; ON_OFF control signal controls the 2nd NPN triode Q3 conducting simultaneously, but not yet sets up because of+6V output voltage, PNP triode Q2 remain off, and NMOS field effect transistor M2 keeps turning off.When+6V output voltage rises to a certain degree, between resistance R1, R2, magnitude of voltage reaches PNP triode Q2 triode cut-in voltage V
be_Q2(about 0.7V), PNP triode Q2 conducting, to electric capacity C3, C4 charging, NMOS field effect transistor M2 gate source voltage increases gradually, and NMOS field effect transistor M2 gradually becomes conducting state by off state, and-6V output voltage of powering drops to-6V gradually by 0V.
When needing to turn off power supply, MCU control ON_OFF control signal is logical zero (CMOS logic level, 0V), and the 2nd NPN triode Q3 ends immediately, causes PNP triode Q2 also to end immediately.Electric capacity C3, C4 storing charge is discharged by resistance R8, causes the gate source voltage of NMOS field effect transistor M2 to reduce gradually, when the gate source voltage of NMOS field effect transistor M2 is lower than its turn-on threshold voltage V
thtime (about 1V), NMOS field effect transistor M2 turns off, and-6V electric power output voltage is gone up to 0V by-6V gradually; The ON_OFF control signal of MCU exports " 0 " logic level, causes a NPN triode Q1 base level V
bfor 0V, but now-6V electric power output voltage still maintains about-6V, causes partitioned level between resistance R6, R7 lower than-V
be_Q1(being about-0.7V), a NPN triode Q1 maintains conducting, and control PMOS field effect transistor M1 continues to keep conducting, and+6V electric power output voltage continues to remain+6V; When-6V electric power output voltage gradually becomes close to 0V, the partitioned level between resistance R6, R7 becomes higher than-V
be_Q1(being about-0.7V), a NPN triode Q1 ends, and electric capacity C1, C2 storing charge is discharged by resistance R3, causes the source-gate voltage of PMOS field effect transistor M1 to reduce gradually, when the source-gate voltage of PMOS field effect transistor M1 is lower than its turn-on threshold voltage V
thtime (about 1V), PMOS field effect transistor M1 turns off, and+6V electric power output voltage is returned to 0V by+6V gradually.
Fig. 2 be dual power supply of the present invention and power-off time sequence control device open shutoff working timing figure.When opening power supply, control at T1 moment switch power supply, positive supply delays firing current and changes from small to big, and sets up positive voltage gradually, until reach positive supply to open peak point current, positive supply steady state output voltage; In the process setting up positive voltage when T2 moment grid reaches out negative supply threshold value, negative supply delays firing current and changes from small to big, and sets up negative supply voltage gradually, until reach negative supply to open peak point current, negative supply steady state output voltage.When turning off power supply, close Energy control in the T3 moment, negative supply delays close current from large to small until be zero, and when T4 moment grid reaches pass positive supply threshold value, close positive supply, positive supply delays close current from large to small until be zero.Opening in+6V power supply ,-6V power supply process, within supply current being limited in particular value (as 200mA), avoid because capacitive load produces excessive dash current.To sum up, the beneficial effect of dual power supply of the present invention and power-off time sequence control device is: when opening power supply, first open+6V Power supply electronic switch, because+6V electric power output voltage is not set up, forbid opening-6V Power supply electronic switch, only have after+6V voltage output voltage establishes, just open-6V Power supply electronic switch; When turning off power supply, first turn off-6V Power supply electronic switch, because-6V electric power output voltage not yet returns 0V ,+6V Power supply electronic switch continues to keep open-minded, after-6V electric power output voltage disappears (namely returning 0V), then turn off+6V Power supply electronic switch.Like this, sequential relationship strict when reliably ensureing to open and turn off power supply, avoid circuit bolt-lock effect, guarantee equipment normally works.
The invention still further relates to a kind of dual power supply and power-off sequential control method, the dual power supply that the method is above-mentioned with the present invention and power-off time sequence control device corresponding, can be regarded as is the method realizing dual power supply of the present invention and power-off time sequence control device.The method employing PMOS field effect transistor is the control main switch of positive supply, utilize a NPN triode, first group of electric capacity and first group of resistance cooperating with the grid of control PMOS field effect transistor and control opening and disconnection of positive supply, and limiting the rush of current that positive supply opens moment; Employing NMOS field effect transistor is the control main switch of negative supply, utilize PNP triode, second group of electric capacity and second group of electric capacity cooperating with the grid of control NMOS field effect transistor and control negative supply and open and disconnection, and limiting the rush of current that negative supply opens moment; The 2nd NPN triode is adopted between power switch control signal and PNP triode.Its hardware circuit diagram realized can with reference to figure 1.When opening power supply, power switch control signal makes a NPN triode ON and makes the conducting of PMOS field effect transistor to first group of capacitor charging with the source-gate voltage increasing PMOS field effect transistor, thus sets up positive supply output voltage; Power switch control signal controls the 2nd NPN triode ON simultaneously, when the positive voltage set up reaches unlatching negative supply threshold value, PNP triode conducting also makes the conducting of NMOS field effect transistor to second group of capacitor charging with the source-gate voltage increasing NMOS field effect transistor, thus sets up negative supply output voltage; When turning off power supply, power switch control signal makes the 2nd NPN triode cut-off and then PNP triode cut-off, and second group of capacitance group electric discharge makes NMOS field effect transistor turn off with the source-gate voltage reducing NMOS field effect transistor, and negative supply output voltage gos up gradually to zero; Power switch control signal controls a NPN triode simultaneously and keeps conducting and then PMOS field effect transistor to keep conducting to maintain positive supply output voltage, negative supply output voltage go up gradually to zero time the one NPN triode cut-off, first group of capacitor discharge makes PMOS field effect transistor turn off with the source-gate voltage reducing PMOS field effect transistor, and positive supply output voltage makes zero gradually.
The method of the present invention, when opening power supply, utilizes the source-gate voltage of the Miller effect control PMOS field effect transistor of first group of electric capacity to increase gradually, makes the slow conducting of PMOS field effect transistor; Utilize the source-gate voltage of the Miller effect control NMOS field effect transistor of second group of electric capacity to increase gradually, make the slow conducting of NMOS field effect transistor.Slowly changed by the grid voltage of field effect transistor, make the slow conducting of field effect transistor, limit the charging current to capacitive load, avoid the formation of the heavy current impact opening power supply moment.
The method detects power switch control signal and positive supply output voltage, negative supply output voltage by the hardware element be separated simultaneously, realizes opening power supply at positive and negative power supply and turning off the accurate control of power supply timing.Its principle as shown in Figure 3, when being logical one level (3.3V) by MCU control power switch control signal level, or time-6V power supply output voltage effective (output-6V), delay startup, it is open-minded that circuit logic controls+6V power supply powered electronic switch; When being logical one level by MCU control power switch control signal level, and time+6V power supply output voltage effective (output+6V), delay startup, circuit logic control-6V power supply powered electronic switch is open-minded.When being logical zero level (0V) by MCU control power switch control signal level, circuit logic control-6V power supply powered electronic switch OFF; When being logical zero level by MCU control power switch control signal level, and time-6V power supply output voltage invalid (exporting 0V), circuit logic controls+6V power supply powered electronic switch OFF.
It should be pointed out that the above embodiment can make the invention of those skilled in the art's comprehend, but do not limit the present invention in any way creation.Therefore; although this instructions has been described in detail the invention with reference to drawings and Examples; but; those skilled in the art are to be understood that; still can modify to the invention or equivalent replacement; in a word, all do not depart from technical scheme and the improvement thereof of the spirit and scope of the invention, and it all should be encompassed in the middle of the protection domain of the invention patent.
Claims (10)
1. a dual power supply and power-off time sequence control device, it is characterized in that, comprise PMOS field effect transistor, NMOS field effect transistor, a NPN triode, the 2nd NPN triode, PNP triode, the first resistance, the second resistance, the first electric capacity, the second electric capacity, the 3rd electric capacity and the 4th electric capacity
Described PMOS field effect transistor is the control main switch of positive supply, and the source electrode of PMOS field effect transistor connects positive supply, and grid connects the collector of a NPN triode, and drain electrode connects positive supply and exports; Described NMOS field effect transistor is the control main switch of negative supply, and the source electrode of NMOS field effect transistor connects negative supply, and grid connects the collector of PNP triode, and drain electrode connects negative supply and exports; The base stage of a described NPN triode connects power switch control signal line, grounded emitter; The base stage of described PNP triode is connected with the collector of the 2nd NPN triode, the emitter of PNP triode connects one end of the first resistance and one end of the second resistance simultaneously, the other end ground connection of described first resistance, another termination positive supply of described second resistance exports; The base stage of described 2nd NPN triode connects power switch control signal line, grounded emitter;
Between the source electrode that described first electric capacity is arranged at PMOS field effect transistor and grid, described second electric capacity is arranged between the grid of PMOS field effect transistor and drain electrode, between the source electrode that described 3rd electric capacity is arranged at NMOS field effect transistor and grid, described 4th electric capacity is arranged between the grid of NMOS field effect transistor and drain electrode.
2. dual power supply according to claim 1 and power-off time sequence control device, is characterized in that, also comprises the 3rd resistance, between the source electrode that described 3rd resistance and the first Capacitance parallel connection are arranged at PMOS field effect transistor and grid.
3. dual power supply according to claim 1 and 2 and power-off time sequence control device, it is characterized in that, also comprise the 4th resistance and the 5th resistance, the base stage of a described NPN triode connects power switch control signal line by the 4th resistance, the base stage of a described NPN triode also connects one end of the 5th resistance, the other end ground connection of described 5th resistance.
4. dual power supply according to claim 3 and power-off time sequence control device, it is characterized in that, also comprise the 6th resistance and the 7th resistance, the emitter of a described NPN triode to connect after the 6th resistance ground connection again, the emitter of a described NPN triode also connects one end of the 7th resistance, and the other end of described 7th resistance connects negative supply and exports.
5. dual power supply according to claim 1 and 2 and power-off time sequence control device, is characterized in that, also comprises the 8th resistance, and described 8th resistance and the 3rd Capacitance parallel connection are between the source electrode and grid of NMOS field effect transistor.
6. dual power supply according to claim 1 and 2 and power-off time sequence control device, is characterized in that, also comprises the 9th resistance, and the base stage of described 2nd NPN triode connects power switch control signal line by the 9th resistance.
7. a dual power supply and power-off sequential control method, it is characterized in that, employing PMOS field effect transistor is the control main switch of positive supply, utilizes the grid of a NPN triode and first group of Capacity control PMOS field effect transistor and controls opening and disconnection of positive supply; Employing NMOS field effect transistor is the control main switch of negative supply, utilize the grid of PNP triode and second group of Capacity control NMOS field effect transistor and control negative supply and open and disconnection, between power switch control signal and PNP triode, adopt the 2nd NPN triode;
When opening power supply, power switch control signal makes a NPN triode ON and makes the conducting of PMOS field effect transistor to first group of capacitor charging with the source-gate voltage increasing PMOS field effect transistor, thus sets up positive supply output voltage; Power switch control signal controls the 2nd NPN triode ON simultaneously, when the positive voltage set up reaches unlatching negative supply threshold value, PNP triode conducting also makes the conducting of NMOS field effect transistor to second group of capacitor charging with the source-gate voltage increasing NMOS field effect transistor, thus sets up negative supply output voltage;
When turning off power supply, power switch control signal makes the 2nd NPN triode cut-off and then PNP triode cut-off, and second group of capacitance group electric discharge makes NMOS field effect transistor turn off with the source-gate voltage reducing NMOS field effect transistor, and negative supply output voltage gos up gradually to zero; Power switch control signal controls a NPN triode simultaneously and keeps conducting and then PMOS field effect transistor to keep conducting to maintain positive supply output voltage, negative supply output voltage go up gradually to zero time the one NPN triode cut-off, first group of capacitor discharge makes PMOS field effect transistor turn off with the source-gate voltage reducing PMOS field effect transistor, and positive supply output voltage makes zero gradually.
8. dual power supply according to claim 7 and power-off sequential control method, it is characterized in that, utilize a NPN triode and first group of electric capacity and first group of resistance cooperating with the grid of control PMOS field effect transistor and control opening and disconnection of positive supply, and limiting the rush of current that positive supply opens moment; Utilize PNP triode and second group of electric capacity and second group of electric capacity cooperating with the grid of control NMOS field effect transistor and control negative supply and open and disconnection, and limiting the rush of current that negative supply opens moment.
9. the dual power supply according to claim 7 or 8 and power-off sequential control method, it is characterized in that, when opening power supply, utilize the source-gate voltage of the Miller effect control PMOS field effect transistor of first group of electric capacity to increase gradually, make the slow conducting of PMOS field effect transistor; Utilize the source-gate voltage of the Miller effect control NMOS field effect transistor of second group of electric capacity to increase gradually, make the slow conducting of NMOS field effect transistor.
10. the dual power supply according to claim 7 or 8 and power-off sequential control method, is characterized in that, by MCU control power switch control signal level be logical one or negative supply output voltage effective time, open positive supply powered electronic switch; By MCU control power switch control signal level be logical one and positive supply output voltage is effective time, open negative supply powered electronic switch; Negative supply powered electronic switch is turned off when being logical zero by MCU control power switch control signal level; By MCU control power switch control signal level be logical zero and negative supply output voltage is invalid time, turn off positive supply powered electronic switch.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510660897.5A CN105182833B (en) | 2015-10-14 | 2015-10-14 | A kind of dual power supply and power-off time sequence control device and method |
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| CN201510660897.5A CN105182833B (en) | 2015-10-14 | 2015-10-14 | A kind of dual power supply and power-off time sequence control device and method |
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| CN105182833A true CN105182833A (en) | 2015-12-23 |
| CN105182833B CN105182833B (en) | 2018-04-17 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107425835A (en) * | 2016-05-23 | 2017-12-01 | 中兴通讯股份有限公司 | A kind of on/off circuit |
| CN110244636A (en) * | 2019-06-25 | 2019-09-17 | 北京机械设备研究所 | A kind of dual power supply on-off control circuit for servo-system |
| CN111555255A (en) * | 2020-03-31 | 2020-08-18 | 惠州市德赛西威汽车电子股份有限公司 | Accurate control circuit and method for discharge time and time sequence of power supply system |
| CN118137650A (en) * | 2024-05-06 | 2024-06-04 | 深圳市积加创新技术有限公司 | Positive and negative symmetrical dual-power switch control circuit of amplifier |
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| US6188210B1 (en) * | 2000-01-13 | 2001-02-13 | Ophir Rf, Inc. | Methods and apparatus for soft start and soft turnoff of linear voltage regulators |
| CN1674438A (en) * | 2004-03-23 | 2005-09-28 | 华为技术有限公司 | Circuit for positive power source inputting load electrifying slow starting |
| CN202309659U (en) * | 2011-11-17 | 2012-07-04 | 中兴通讯股份有限公司 | Power input load power-on slow starter |
| CN205015670U (en) * | 2015-10-14 | 2016-02-03 | 基康仪器股份有限公司 | Dual power supply and outage time schedule control device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6188210B1 (en) * | 2000-01-13 | 2001-02-13 | Ophir Rf, Inc. | Methods and apparatus for soft start and soft turnoff of linear voltage regulators |
| CN1674438A (en) * | 2004-03-23 | 2005-09-28 | 华为技术有限公司 | Circuit for positive power source inputting load electrifying slow starting |
| CN202309659U (en) * | 2011-11-17 | 2012-07-04 | 中兴通讯股份有限公司 | Power input load power-on slow starter |
| CN205015670U (en) * | 2015-10-14 | 2016-02-03 | 基康仪器股份有限公司 | Dual power supply and outage time schedule control device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107425835A (en) * | 2016-05-23 | 2017-12-01 | 中兴通讯股份有限公司 | A kind of on/off circuit |
| CN107425835B (en) * | 2016-05-23 | 2023-01-17 | 中兴通讯股份有限公司 | Startup and shutdown circuit |
| CN110244636A (en) * | 2019-06-25 | 2019-09-17 | 北京机械设备研究所 | A kind of dual power supply on-off control circuit for servo-system |
| CN111555255A (en) * | 2020-03-31 | 2020-08-18 | 惠州市德赛西威汽车电子股份有限公司 | Accurate control circuit and method for discharge time and time sequence of power supply system |
| CN118137650A (en) * | 2024-05-06 | 2024-06-04 | 深圳市积加创新技术有限公司 | Positive and negative symmetrical dual-power switch control circuit of amplifier |
| CN118137650B (en) * | 2024-05-06 | 2024-07-05 | 深圳市积加创新技术有限公司 | Positive and negative symmetrical dual-power switch control circuit of amplifier |
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| Publication number | Publication date |
|---|---|
| CN105182833B (en) | 2018-04-17 |
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