CN1051420C - Global bus network - Google Patents
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- CN1051420C CN1051420C CN93108467A CN93108467A CN1051420C CN 1051420 C CN1051420 C CN 1051420C CN 93108467 A CN93108467 A CN 93108467A CN 93108467 A CN93108467 A CN 93108467A CN 1051420 C CN1051420 C CN 1051420C
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Abstract
The invention of the overall bus network can increase the channel bandwidth using efficiency, providing high-speed data to have a more stable failure control and reduce the waste of the delay during sending data under the busy communication business load. The network includes devices and methods for detecting and controlling the failures from dual-node structure formed by the host processor nodes and processor nodes. The host processor node can detect the faults from the whole network, while the processor node can only detect their own fault and confirm by the failure detection signal from the host processor node. The network also includes devices and methods controlling the high-speed data transmission, and provides multi-frame circuits.
Description
The present invention relates to a communication network that uses global bus to realize the Serial Data Transfer Mode between a plurality of processors.More particularly, the present invention relates to a kind of network relevant with global bus, this class global bus has the character that can increase channel bandwidth utilization ratio and more stably control the error in the whole network.
Global bus network is a kind of of network topology, and it makes the transmission of serial data between microprocessor and reception become possibility by global bus's path that a plurality of processors that are connected in the network constitute.Simultaneously, in the system of global bus, between a plurality of processors,, be to operate by the token of round-robin scheduling (Round-Robin scheduing) by the Serial Data Transfer Mode of bus.
Prior art related to the present invention can be referring to United States Patent (USP) 4,608, and 559,5,249,183 and 5,299,193.
Consult Fig. 1 disclosed herein, the parts of traditional network comprise that processor 10, bus control unit 30 and bus failure detect and control unit 20.Total state of situation about taking place during described processor 10 control datas transmit.Described bus control unit 30 can and can be exported a bus acknowledge signal to described processor 10 according to the bus request signal input of from processor 10 with processor 10 interfaces.In addition, the fault of described bus failure detection and control unit 20 testbus when receiving the bus acknowledge signal, as detect fault and take place then to provide a fault recognition signal, and send a bus disenable signal to described bus control unit 30 simultaneously to processor 10.Now consult Fig. 2, the bus control unit 30 in traditional processor node (node) comprises DMAC (directmemoryaccess controller (Direct Memory Access Controller) 31, SIO (serial i/O) 32, bus driver 34 and a bus control module 33.
Described DMAC31 can transmit data in the local memory that there is processor 10 in zero access for rapid data.SIO32 obtains DMAC31 from the local memory of processor 10 parallel data converts the serial data that is used for serial data communication to.Bus driver 34 provides the actual connection between processor and the network (Ex, IEEE488) device.If think that this processor has token when receiving the bus request signal of from processor 10, then bus control module 33 oriented processors 10 send the bus acknowledge signal, and can send data from the affirmation of SIO32 by bus driver 34.And the data of delivering to SIO32 by network (GBI).Explain the common course of work of bus-structured legacy network below with reference to the accompanying drawings.
Will send the processor 10 of data in bus-structured network, after receiving the bus acknowledge signal, just can send data, the reception of bus acknowledge signal means permission use bus.Bus failure detects and control unit 20 starts as counter circuit energy and definite bus acknowledge signal Synchronization, and can come the maximum bus of processor controls node to determine the time by inside counting pulse during occupying bus.If processor node takies the time of network and determines the time above predetermined maximum bus, bus failure detects and control unit 20 just thinks that this is that certain fault has taken place processor node itself.Therefore, unit 20 sends a fault recognition signal and sends a bus disenable signal to bus control unit 30 to processor 10.As a result, processor node finally discharges bus, will finally obtain some recovery then.More particularly, the processing of described processor data communication can be described with reference to figure 3.When processor has the data that will send out (processor is confirmed a bus request signal to bus control module 33), affirmation bus request step 101 is carried out by the following step: bus control unit 33 counting affirmation synchronised clock to a fixing value (as, FFH), when being given the chance of using bus (as, token), unless network be not used.At this moment, asked the processor 10 of bus judge whether to receive the bus acknowledge signal (interrupt signal, Fig. 5).If interrupt to judge that 102 be "Yes", then DMAC/SIO starts 103 and begins with a bus acknowledge signal.It is beginning with signal 103 that data transmit 104, and makes the judgement 105 whether transmission is finished.Be judged as "Yes" as transmitting whether to finish, determine that then bus discharges 106; Be judged as "No" if transmit whether to finish, then continue data and transmit 104.After carrying out for 106 steps, system returned for 101 steps.Refer now to Fig. 1, in the processor node of bus-structured legacy network, the method for detection failure has limited maximum bus and has determined the time, to guarantee each processor node that connects in the network chance of identical use bus is arranged all.And in this traditional network, fault detect is only carried out in taking the processor node of network.Therefore, the system in the legacy network can not detect the former jade tablet that communication channel causes.This system also has another problem, promptly can not control other idle processor, because can not monitor mutually between a processor and another processor.When arbitrary idle processor work is not normal, very big problem can appear particularly.Referring to Fig. 2 and Fig. 3, the data transfer step in the legacy network is like this work, promptly send a bus request signal transmit with log-on data handle after, processor need wait until that the bus acknowledge signal is received.Therefore, during data transfer process multiple delay will take place; Because bus request signal all can produce in any moment of working regulation, thus the bus acknowledge signal produced at random by the conventional hardware of control bus, thereby the action of control bus also is at random; In other words, bus request signal and bus determine do not have rule between the interval of signal; Need a period of time to confirm the bus acknowledge signal; Start DMAC and SIO and need extra propagation delay.
This delay has limited the network utilisation in the network of bus form to a certain extent.Another problem of legacy network is the deterioration of performance under working condition; In legacy system, each processor node once can send the frame of identical maximum number, and does not consider the data volume that each processor comprises in the formation.Therefore, concerning the processor that big load is arranged in input rank, because crowding in the output queue, transmission lag will increase.This causes the delay of whole transmission.So in the very different each other network of the communication traffic load of processor, this system is inappropriate.
For addressing the above problem, an object of the present invention is to provide a fault detection algorithm and by binode structure i.e. a primary processor node and a device that constitutes from processor node.Here, the primary processor node can detect some faults of whole network; On the other hand, only can detect some faults of self and can determine fault detection signal from processor from primary processor.Another object of the present invention provides the device, method of control data transmission in a kind of communication network, and this method can improve the utilance of bus.
Therefore, an object of the present invention is to provide cheap and high performance improved network on the structure.
Another purpose of the present invention provides the execution of hardware supports mechanism with Control Network.
Another purpose of the present invention is to provide more effective hardware supports for network operation control.
In brief, the present invention forms by primary processor node identical on the structure with from processor node.The parts of each processor all are improved.In addition, some parts have also been added, to improve the performance of network.
The present invention proposes a kind of equipment that is used in the communication network control data transmission, described communication network comprises a plurality of nodes that are connected to common bus, each described node has a communication processor, communication processor has memory associated therewith and bus control device, be used for data being transferred to network from processor by bus, described bus control device comprises that a direct memory access (DMA) controller (DMAC) is used for visiting parallel data at memory, a serial conversion equipment is used for parallel data is converted to serial data or converts serial data to parallel data, a bus control module, be used for producing the bus acknowledge signal and in response to the bus request signal of processor with from the bus acknowledge signal of described bus control device at data transmission procedure, and bus driver, be connected with bus and be used for transfer of data, it is characterized in that this equipment comprises:
(a) fault detect/control device is provided in a node of described node, be used for detecting the fault of network and when detect fault to described fault-signal of node generation that comprises itself;
(b) failure detector is provided in each other the node beyond above-mentioned, is used for receiving described fault-signal from fault detect/control device by bus;
(c) diagnostic device is provided in each node, and in response to failure detector, whether the fault that is used for diagnostic detection betides its node; Wherein in malfunctioning node, described diagnostic device force processor stops data transfer operation and failure detector or fault detect/control device also forces bus control device and bus to disconnect, thereby has eliminated the fault in the network; And when described fault detect/control device detects the fault in the network continuously and does not receive the bus acknowledge signal, described fault detect/control device determines that fault occurs in the network of itself, produce alarm signal then, informing network the operator repair.
The present invention also proposes a kind of method that is used in the communication network control data transmission, described communication network comprises a plurality of nodes that are connected to common bus, each described node has a communication processor, communication processor has memory and bus control device, be used for producing the bus acknowledge signal to communication processor, and trouble-shooter, be used for tracing trouble, one in the described node further has a fault detect/control device, be used for detection failure and produce fault-signal, and each other node further has a failure detector, is used for detection failure, it is characterized in that this method comprises the steps:
(a) fault in the detection network and each node on bus produce a fault-signal in fault detect/control device;
(b) in each node in failure detector the detection failure signal;
(c), in the trouble-shooter in each node, determine whether to break down in response to bus control device;
(d), stop processor data transmission operation and disconnect being connected of bus control device and bus by the failure detector in the node that breaks down in response to trouble-shooter;
(e) when fault is detected continuously and do not receive bus acknowledge signal from any node, indicate this network failure to the network operator by described fault detect/control device.
The novel features of the embodiment of the invention will describe in detail below with reference to the accompanying drawings, wherein:
The structured flowchart of the conventional processors node that the network that Fig. 1 is with bus constitutes links to each other;
Fig. 2 is the block diagram of bus control unit shown in Figure 1;
Fig. 3 is the flow chart of data communication in the conventional processors node;
Fig. 4 is the block diagram that constitutes processor node of the present invention;
Fig. 5 and Fig. 6 have illustrated the fault detect in the global bus network shown in Figure 4 and the workflow diagram of control;
Fig. 7 is the expansion block figure of the bus control unit in the processor node of the present invention;
Fig. 8 is the more detailed block diagram of bus control module among Fig. 7;
Fig. 9 is the flow chart that constitutes data communication in the processor node of the present invention;
Figure 10 constitutes block diagram of the present invention, as to aim at the bus control unit of the multiframe transmission design in the global bus network;
Figure 11 is the relevant time synchronized curve charts of the various signals among Figure 10.
Referring to Fig. 4, constitute a processor node of the present invention and be divided into two groups: primary processor node and from processing node; The primary processor node comprises processor 40, only the interested Fault Control of the fault unit 50 that occurs in processor 40 self, the bus failure that detects and control fault in the whole network is detected and control unit 60 and include with the bus network interface and send the bus control unit 70 of bus acknowledge signal to processor 40; From the bus failure of processor by to host node detect and control unit (60, Fig. 4) sends fault-signal and confirm fault detection signal, and detection occurs over just some faults of self, and can not detect and control the fault in the whole network.Therefore, comprise bus failure detecting unit 80, be used to detect partial fault detection unit 50A, can and can send the bus control unit 70A and the processor 40A of bus acknowledge signal from processor node with the global bus network interface to processor 40A from the processor node faults itself.
Referring to Fig. 5 and Fig. 6, fault detect and Control work in the global bus network of the present invention will be divided into host node and explained in detail from node.
At first, the fault in the global bus network roughly is divided into two groups.A kind of fault is that the processor node that takies network produces.Another group fault produces from channel or from whole network.
At first referring to Fig. 5, the step that detects and control two class errors in the primary processor node is explained as follows: detect network failure and judge 210 judge whether detect a network failure.If be judged as "Yes", determine that fault recognition signal 211 is sent to each from processor by Fault Control unit 50.After the 211st step, carry out processor node self and judge 212, whether fault has taken place to judge.If be "Yes", then carry out and confirm primary processor judgement 213, to judge whether primary processor takies bus.If be "Yes", then change release bus state 214 over to; If be "No", this system repeated to begin the 210th step.If processor node self judges that 212 is "No", then carry out and confirm to judge 215 from processor, whether be determined from processor to judge; If judge that 215 are "Yes", the 210th step of system's backspace; If be "No", inform that network failure step 216 just informs the user to intrinsic network failure.
Referring to Fig. 6, wherein adopted and described the software manual flow chart that detects and control fault from processor node; Be from the bus failure detecting unit 80 of processor node, to make detection failure judgement 220, from processor node, whether breaking down to judge.Carry out and confirm whether fault judgement 221 receives the fault recognition signal that bus failure detects and control unit 60 sends with decision processor.Carry out bus acknowledge and detect judgement 222 so that (50A Fig. 4) has judged whether that processor takies network by local control unit.Judge that 222 is "Yes" if bus detects, then carry out and confirm processor self judgement 223, to judge (40A, Fig. 4) whether self takies bus from processor.If judge that 223 are "Yes", then carry out bus and discharge 224, confirm that this class fault is next since processor self.After the 224th step, (40A Fig. 4) discharges bus from processor; If judge that 223 are "No", then forward initial state to.As judge that 222 are "No", and carry out and inform network failure step 225, think that fault occurs in network.
Referring to Fig. 7, (70,70A Fig. 4) comprises a DMAC14, SIO15, DMAC/SIO linker 16, a bus control module 17 and a bus driver 18 to constitute bus control unit of the present invention.The work of described DMAC/SIO linker 16 control DMAC and SIO.Described bus driver 18 is provided to the connection of global bus (GB2).Described bus control module 17 is confirmed a bus acknowledge signal to DMAC/SIO linker 16 after it receives the bus request signal of from processor.
Referring to Fig. 8, and bus control module (17, Fig. 7) comprise buffer control unit 5, bus arbitraction program 6 and local counter 7; Described bus control unit 5 is also delivered to SIO15 to the bus driver of delivering to from the serial data of SIO15 and BRCLK (bus request clock) is synchronous 18 to the data from bus through bus driver 18.Described local counter 7 is (priority number is such as FFM) counting synchronised clock from an initial value to a determined value; When arrive this determined value (as, in the time of FFH), have processor just can take bus as this determined value of priority number.If the minimum of priority is set, then local counter 7 makes the counter of each processor node get back to initial value by producing a FRS (frame reset synchronization) signal.Described bus arbitraction program 6 is with the input of the bus request signal of from processor with from the ASTCLK and the AST input of local counter, output bus confirmation signal.The work of the bus control module of said structure will be described in detail as follows; The given constant mark number of each processor uses the chance of bus with control.This identification number is transfused in the described local counter 7 as initial value.Local counter 7 is synchronous with ASTCLK after starting, and local counter 7 is counting when bus is idle only.When reach a certain determined value (such as, in the time of FFH), bus is allowed to use.
When a processor obtains bus, as not keeping bus, bus can not be confirmed by processor.But when processor obtains bus, keep bus as processor, then bus will be confirmed as follows by processor; Bus arbitraction program shown in Figure 8 (6, Fig. 8) local counter can not be used, and notice buffer control unit 5 bus acknowledge states are done by sending an AST signal.Buffer control unit drives bus driver then.The bus arbitraction program is also informed 16 1 bus acknowledge signals of DMAC/SIO linker, with the beginning Data Receiving.When Data Receiving was finished, signal was finished in bus arbitraction program checkout bus request signal and transmission shown in Fig. 8.Finish the signal existence if only have to transmit, 6 of bus arbitraction programs discharge bus.Buffer control unit 5 shown in Fig. 8 can not be worked bus driver 18, so that all local counters are counted again, becomes possibility thereby make next processor take bus.If all processors have all taken bus once, the processor (processor that the lowest priority number is promptly arranged) that then takies bus at last use with all different id numbers of each processor of FRS signal Synchronization set local counter (6, Fig. 8).
Referring to Fig. 9, the course of work that constitutes the data communication in the processor node that comprises bus control unit of the present invention is such: when described processor will transmit data, to bus control module (17, Fig. 7) request bus (the 301st step), finished for the 301st step after, drive DMAC and the SIO step (the 302nd step) simultaneously.When carrying out for 302 steps, the DMAC/SIO linker blocks the data communication between DMAC and the SIO, because also do not receive the bus acknowledge signal from described bus control module.After bus control module 17 was received bus request signal in the 301st step, carrying out bus access provided judgement 303, whether can take bus with the processor of judging the request bus; If judge 303 for "No", then bus control module still will be judged, till processor can take bus after predetermined; If judge that 303 are "Yes", then send following carrying out of data step (the 304th step): after bus control module 17 took bus, it started bus driver 18, sent the bus acknowledge signal to DMAC/SIO linker 16 then.
DMAC/SIO linker identification bus confirmation signal then drives DAMC14 and SIO15 with a kind of special control signal, makes the processor of being scheduled to bus can carry out data processing, and does not consider the processor of any other request bus.The 304th step carried out data and is sent completely judgement 305 after finishing.Determine whether to produce transmission by 305 results that go on foot and finish signal.Be judged as "Yes" as the 305th step, then discharge bus (the 306th step), thereby make next processor can take bus.After finishing in the 306th step, in system's backspace the 301st step, restart.
Referring to Figure 10, constitute bus control unit of the present invention and that send design for multiframe and comprise: frame counter 100, bus determine that confirmation unit 200, data sending request unit 300, bus determine that control unit 400, frame period control unit 500, SIO600, SIO/DMA linker 700, DMA800 and frame are sent completely unit 900.The number of the frame that described frame counter 100 countings once send.It is identical that described bus determines that confirmation unit 200 effects and its title are pointed out.Described data sending request unit 300 informs whether processor has data to send.The LMULTI whether described definite control unit 400 decision buses can be produced by frame counter 100
*Signal input, bus are determined Tx-AL-LOW signal input that confirmation unit 200 produces and from the TxSTB of data sending request unit 300
*Import shared.The interval that described frame period control unit 500 is eliminated between the frame.Described SIO600 sends serial data to bus.Whether the transmission that described frame sending controling unit 900 detects a frame is finished.Described SIO/DMA linker 700 is at the STRE that receives from SIO600
*Signal and determine the Tx-RDF of control unit 400 from bus
*Behind the signal, produce DTX REQ
*(data sending request) signal is to DMA.The Tx-COM of bus acknowledge unit 400 is transported in the input representative of frame counter 100
*The frame number of (being sent completely) signal.
Referring to Figure 11, the operation of the bus control unit that above-mentioned parts constitute will be explained as follows; Figure 11 has illustrated the time synchronized figure that sends the input and output of the bus control unit of handling according to multiframe.
The multiframe sending order is as follows:
1. when processor will send data, and this processor command data sending request unit (300, Figure 10) produce TXSTB
*Signal (A, Figure 11), and notify subsequently bus determine control unit (400, Figure 10) have the data that will send; (beginning)
2.SIO (600, Figure 10) reset to response TXSTB
*(A) initial condition of signal.Then, SIO produces STXREQ
*Signal (B, Figure 11);
3. when bus arrives, bus determine confirmation unit (200, Figure 10) produce a Tx ALLOW
*Signal (G, Figure 11), and it send to frame counter (100, Figure 10) and bus determine control unit (400, Figure 10);
4. described frame counter (100, Figure 10) and bus determine control unit (400, Figure 10) with TX ALLOW (G, Figure 11) signal responds; Predetermined frame count value (the P of corresponding frame counter input
1P
N).If TXSTB
*(A) signal is identified, and then corresponding bus control unit produces an ASTRDF
*Signal (H, Figure 11);
Bus determine control unit (400, Figure 10) after bus is determined, also produce a TX RDF
*(I, Figure 11) signal is delivered to DMA to data from SIO;
6. the STXREQ that produces in response to SIO (600)
*Signal (B), and the SIO/DMA linker (700, Figure 10) produce a DTXREQ
*(C, Figure 11) signal to DMA (500, Figure 10);
7. in response to STXREQ
*Signal (B), and described DMA (800, Figure 10) produce a TX ACK
*Signal (D, Figure 11) to frame be sent completely the unit (900, Figure 10) and SIO (600, Figure 10);
8. in response to TXACK
*Signal, SIO sends the data that bus is received from DMA.When DMA finished the transmission of a frame, it produced DONE
*Signal (E, Figure 11).DMA determines DONE at the point that each frame is sent completely
*Signal.
9. in response to DONE
*Signal and TXACK
*, frame be sent completely the unit (900, Figure 10) produce TX DONE
*Signal (F, Figure 11).
10. work as TXDONE
*When signal is determined, frame counter (100, Figure 10) number of the frame that sends in during bus takies of counting, and, the frame period control unit (500, Figure 10) TXCOMP of generation
*The signal of a lasting set time (J, Figure 11), to provide the interval between the frame.
11. in response to TXCOMP
*Signal (J), bus determine control unit (400, Figure 10) produce an inactive TXRDF
*Signal (I, Figure 11); (800, Figure 10) Be Controlled does not produce DTXREQ to DMA like this
*Signal (C, Figure 11);
12. when the frame period control unit (500, Figure 10) refusal TXCOMP
*(J in the time of Figure 11), produces a bus RES to signal
*(K, Figure 11);
13. according to bus RES
*Signal (K), TXSTB
*Signal (A) and LMVLTI
*Signal (L, Figure 11), bus determines (400, Figure 10) whether the decision processor still keeps bus to control unit; Above-mentioned decision is performed such; If TXSTB
*(A) is stand-by for signal, and has produced LMULTI
*Signal (L), bus determine control unit (400, Figure 10) produce ASTRDF
*Signal is waited for the bus of release busy.But, if TXSTB
*Signal (L) does not produce, bus determine control unit (400, Figure 10) then keep bus and send (end) to finish multiframe.
Be the abbreviation of triumph among Figure 11 below:
TX STB
*-transmission strobe pulse
STX REQ
*-ask from SIO TX
DTX REQ
*-data sending request
TX ACK
*-send and confirm
TX DONE
*-be sent completely (Transmirsion Done)
TX ALLOW
*-transmission allows
ASTRDF
*-determine to prepare to indicate
TX RDF
*-send and prepare sign
TX COMP
*-be sent completely
BUS RES
*-bus discharges
LMULTI
*-last a plurality of frames (Last Multiframe)
Claims (3)
1. be used for equipment in the communication network control data transmission, described communication network comprises a plurality of nodes that are connected to common bus, each described node has a communication processor, communication processor has memory associated therewith and bus control device, be used for data being transferred to network from processor by bus, described bus control device comprises that a direct memory access (DMA) controller (DMAC) is used for visiting parallel data at memory, a serial conversion equipment is used for parallel data is converted to serial data or converts serial data to parallel data, a bus control module, be used for producing the bus acknowledge signal and in response to the bus request signal of processor with from the bus acknowledge signal of described bus control device at data transmission procedure, and bus driver, be connected with bus and be used for transfer of data, it is characterized in that this equipment comprises:
(a) fault detect/control device is provided in a node of described node, be used for detecting the fault of network and when detect fault to described fault-signal of node generation that comprises itself;
(b) failure detector is provided in each other the node beyond above-mentioned, is used for receiving described fault-signal from fault detect/control device by bus;
(c) diagnostic device is provided in each node, and in response to failure detector, whether the fault that is used for diagnostic detection betides its node; Wherein in malfunctioning node, described diagnostic device force processor stops data transfer operation and failure detector or fault detect/control device also forces bus control device and bus to disconnect, thereby has eliminated the fault in the network; And when described fault detect/control device detects the fault in the network continuously and does not receive the bus acknowledge signal, described fault detect/control device determines that fault occurs in the network of itself, produce alarm signal then, informing network the operator repair.
2. the equipment of claim 1, it is characterized in that a connector is provided between DMAC and the serial conversion equipment, be used for allowing transfer of data when bus control module is received from DMAC to the serial conversion equipment when the bus acknowledge signal, and when transfer of data is finished, be used for finishing signal to bus control module generation transfer of data, so that disconnect with bus.
3. be used for method in the communication network control data transmission, described communication network comprises a plurality of nodes that are connected to common bus, each described node has a communication processor, communication processor has memory and bus control device, be used for producing the bus acknowledge signal to communication processor, and trouble-shooter, be used for tracing trouble, one in the described node further has a fault detect/control device, be used for detection failure and produce fault-signal, and each other node further has a failure detector, is used for detection failure, it is characterized in that this method comprises the steps:
(a) fault in the detection network and each node on bus produce a fault-signal in fault detect/control device;
(b) in each node in failure detector the detection failure signal;
(c), in the trouble-shooter in each node, determine whether to break down in response to bus control device;
(d), stop processor data transmission operation and disconnect being connected of bus control device and bus by the failure detector in the node that breaks down in response to trouble-shooter;
(e) when fault is detected continuously and do not receive bus acknowledge signal from any node, indicate this network failure to the network operator by described fault detect/control device.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92-12576 | 1992-07-15 | ||
| KR1019920012576A KR970008905B1 (en) | 1992-07-15 | 1992-07-15 | Apparatus and method for transmisson control of global bus network |
| KR92016308A KR970008910B1 (en) | 1992-09-07 | 1992-09-07 | Apparatus and method for trouble diagnosis and control of global bus network |
| KR92-16308 | 1992-09-07 | ||
| KR1019920022865A KR0139967B1 (en) | 1992-11-30 | 1992-11-30 | Multi-frame transmission control circuit of global bus |
| KR92-22865 | 1992-11-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1083644A CN1083644A (en) | 1994-03-09 |
| CN1051420C true CN1051420C (en) | 2000-04-12 |
Family
ID=27348844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN93108467A Expired - Fee Related CN1051420C (en) | 1992-07-15 | 1993-07-14 | Global bus network |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1051420C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012164417A1 (en) * | 2011-06-01 | 2012-12-06 | International Business Machines Corporation | Sideband error signaling |
| US8880956B2 (en) | 2011-06-01 | 2014-11-04 | International Business Machines Corporation | Facilitating processing in a communications environment using stop signaling |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08163636A (en) * | 1994-12-09 | 1996-06-21 | Sony Corp | Digital cordless telephone system |
| CN116484947B (en) * | 2023-06-25 | 2023-09-08 | 上海燧原科技有限公司 | Operator automatic generation method, device, equipment and medium |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2181542A2 (en) * | 2007-08-31 | 2010-05-05 | Nokia Corporation | Discovering peer-to-peer content using metadata streams |
-
1993
- 1993-07-14 CN CN93108467A patent/CN1051420C/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2181542A2 (en) * | 2007-08-31 | 2010-05-05 | Nokia Corporation | Discovering peer-to-peer content using metadata streams |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012164417A1 (en) * | 2011-06-01 | 2012-12-06 | International Business Machines Corporation | Sideband error signaling |
| GB2503404A (en) * | 2011-06-01 | 2013-12-25 | Ibm | Sideband error signaling |
| US8644136B2 (en) | 2011-06-01 | 2014-02-04 | International Business Machines Corporation | Sideband error signaling |
| GB2503404B (en) * | 2011-06-01 | 2014-04-30 | Ibm | Sideband error signaling |
| US8787155B2 (en) | 2011-06-01 | 2014-07-22 | International Business Machines Corporation | Sideband error signaling |
| US8880956B2 (en) | 2011-06-01 | 2014-11-04 | International Business Machines Corporation | Facilitating processing in a communications environment using stop signaling |
| US8880957B2 (en) | 2011-06-01 | 2014-11-04 | International Business Machines Corporation | Facilitating processing in a communications environment using stop signaling |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1083644A (en) | 1994-03-09 |
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