CN105117170A - Computer system architecture - Google Patents

Abstract

The invention discloses a computer system architecture, including an information processing module, a PCIE exchange module and a GPU computing module, the GPU computing module includes a plurality of GPUs, and any two GPUs perform data communication through an NVLink link; the information processing module passes the PCIE The switching module establishes a PCIE link connection with the GPU computing module, and data communication is performed between the information processing module and the GPU computing module through the PICE link. This application realizes the redundant design based on the information processing module as management, which improves the redundancy of the system; at the same time, any two GPUs can directly perform data communication, and the data communication is based on the NVLink link, and the NVLink link It is a dedicated high-speed interconnect channel for each GPU, which can provide a bandwidth of up to 20GB/s, thus effectively improving the efficiency of data transmission between GPUs.

Description

A computer system architecture

technical field

The present invention relates to the field of computer technology, and more specifically, to a computer system architecture.

Background technique

With the explosive growth of the current network and data volume, high-performance computing for data is becoming more and more important.

Since the general-purpose processors in the current computer system architecture are not specially designed for high-performance computing of data, there is a problem of low computing efficiency when using them to complete high-performance computing of data. Therefore, processors are usually used with GPUs ( GraphicsProcessingUnit, graphics processor) to complete high-performance computing for data. However, in the current computer architecture, data transmission cannot be directly performed between GPUs, but the data of one GPU is processed by the processor and sent to another GPU to complete the data transmission between the two GPUs. Since the data transmission between the GPU and the processor is usually based on the PCIE (Peripheral Component Interface Express, bus and interface standard) 3.0x16 link, the maximum bandwidth it can currently provide is only 16GB/s, and the processor used as the transmission medium has low computing efficiency Therefore, the efficiency of data transmission between GPUs is low.

To sum up, the computer system architecture in the prior art has the problem of low data transmission efficiency between GPUs.

Contents of the invention

The purpose of the present invention is to provide a computer system architecture to solve the problem of low efficiency of data transmission between GPUs existing in the computer system architecture of the prior art.

In order to achieve the above object, the present invention provides the following technical solutions:

A kind of computer system framework, comprises information processing module, PCIE exchange module and GPU calculation module, described GPU calculation module comprises a plurality of GPUs, all carries out data communication by NVLink link between any two described GPUs; Described information processing module Establishing a PCIE link connection with the GPU computing module through the PCIE switching module, and performing data communication between the information processing module and the GPU computing module through the PICE link.

Preferably, data communication is performed between the PCIE switching module and the information processing module through a PCIE3.0x8 link, and data communication is performed between the PCIE switching module and the GPU computing module through a PCIE3.0x16 link.

Preferably, the GPU calculation module includes L calculation enhancement units, the number of GPUs is 4L, each of the calculation enhancement units includes 4 GPUs, and the PCIE switch module includes L PCIE switch units , the PCIE switching unit is connected to the computing enhancement unit in a one-to-one correspondence, and L is a positive integer.

Preferably, the information processing module includes an information processing unit, and the information processing unit is specifically an X86 processor or an ARM processor.

Preferably, the number of the information processing units is two.

Preferably, the information processing module further includes a centralized management unit, and the centralized management unit is configured to centrally manage the I/O communication devices in the computer system architecture under the control of the information processing unit.

Preferably, the information processing module further includes an information collection unit configured to monitor the temperature and voltage of the computer system architecture in real time under the control of the centralized management unit.

Preferably, the centralized management unit is connected to the information processing unit through a DMI bus, and the centralized management unit is connected to the information collection unit through a PCIE3.0x1 link.

Preferably, the computer system architecture further includes a SAS extension module, the SAS extension module includes M physical disks, and M is a positive integer;

The SAS expansion module is connected to the information processing module through a PCIE3.0x8 link, and is used to complete data storage and reading under the control of the information processing module.

Preferably, the information processing module further includes a disk storage array, and the disk storage array includes N physical disks, where N is a positive integer;

The disk storage array performs data communication with the SAS expansion module through SAS signals.

A computer system architecture provided by the present invention includes an information processing module, a PCIE exchange module and a GPU computing module, the GPU computing module includes a plurality of GPUs, and any two GPUs perform data communication through an NVLink link; the information processing module passes the PCIE The switching module establishes a PCIE link connection with the GPU computing module, and data communication is performed between the information processing module and the GPU computing module through the PICE link. Compared with the prior art, firstly, this application realizes the redundant design based on the information processing module as management, which improves the redundancy of the system; secondly, realizes the full interconnection between GPUs, that is, any two GPUs are It can directly carry out data communication, and its data communication is based on the NVLink link. The NVLink link is a proprietary high-speed interconnection channel for each GPU, and the bandwidth it can provide can reach 20GB/s. The bandwidth of the PCIE3.0x16 link based on data communication between processors is 25% higher. Therefore, high-speed data transmission based on point-to-point mode is realized, which effectively improves the efficiency of data transmission between GPUs.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can also obtain other drawings according to the provided drawings on the premise of not paying creative efforts.

FIG. 1 is a schematic structural diagram of a computer system architecture provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram when L is 2 in a computer system architecture provided by an embodiment of the present invention;

FIG. 3 is a model diagram when L is 2 in a computer system architecture provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of an information processing module in a computer system architecture provided by an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Please refer to Fig. 1, which shows a schematic structural diagram of a computer system architecture provided by an embodiment of the present invention, the computer system architecture can include an information processing module 1, a PCIE switching module 2 and a GPU computing module 3, and the GPU computing module 3 includes Multiple GPUs, data communication between any two GPUs through the NVLink link; the information processing module 1 establishes a PCIE link connection with the GPU computing module 3 through the PCIE switching module 2, and the information processing module 1 and the GPU computing module 3 pass the PICE link for data communication.

Wherein, the number of GPUs may be determined according to actual needs.

First of all, this application realizes the redundant design based on the information processing module as management, which improves the redundancy of the system; secondly, it realizes the full interconnection between GPUs, that is, any two GPUs can directly perform data communication, and Its data communication is based on the NVLink link. The NVLink link is a proprietary high-speed interconnection channel for each GPU. The bandwidth it can provide can reach 20GB/s, which is higher than the data communication between the GPU and the processor in the prior art. The bandwidth of the PCIE3.0x16 link is 25% higher. Therefore, high-speed data transmission based on point-to-point mode is realized, which effectively improves the efficiency of data transmission between GPUs.

Among them, the GPU in the GPU computing module is a high-performance computing device for data, which mainly provides high-intensity floating-point computing performance for the system. The information processing module is the information processing core of the whole system, and it controls the GPU in the GPU computing module to complete related work. The PCIE switching unit can act as a transmission intermediary, which can make the information processing module and the GPU computing module indirectly connected through the PCIE switching module, and then make the information processing unit control the GPU computing module to complete related work through the PCIE information.

It should be noted that deep learning is a new field in machine learning research, and its motivation is to establish and simulate the neural network of the human brain for analysis and learning, which imitates the mechanism of the human brain to interpret data, such as images, sounds and texts. Deep learning includes high-performance computing for data. For example, feature extraction for a picture requires 170G floating-point calculations, and 1.2 million pictures for a network training requires 318P floating-point calculations. If a CPU (CentraMProcessingUnit, Central processing unit) needs 22 days to complete the above-mentioned workload, and if a GPU is used to complete the above-mentioned workload, it only needs about 18 hours. Therefore, the high-performance computing of data using GPU has the advantages of high computing efficiency in the present invention. advantage.

Preferably, in a kind of computer system framework that the embodiment of the present invention provides, can carry out data communication through PCIE3.0x8 link between PCIE switch module and information processing module, can pass PCIE3.0x16 link for data communication.

It should be noted that both the PCIE3.0x8 link and the PCIE3.0x16 link belong to the PCIE link, and the PCIE3.0x8 link is more in line with the characteristics of data communication between the PCIE switching module and the information processing module, while the PCIE3.0x16 link The path is more in line with the characteristics of data communication between the PCIE switching module and the GPU computing module, and the experiment proves that using the above link for communication between related modules not only saves bandwidth resources, but also achieves normal communication of data.

Preferably, a kind of computer system framework that above-mentioned embodiment provides, GPU calculation module can comprise L calculation enhancement unit, the quantity of GPU can be 4L, and each calculation enhancement unit can comprise 4 GPUs, and PCIE switch module can comprise L PCIE switching units, the PCIE switching units are connected to the computing enhancement units in one-to-one correspondence, and L is a positive integer.

It should be noted that the specific value of L can be determined according to actual needs. When the number of GPUs is 4L, in order to reasonably allocate the arrangement of each module in actual production, it can be set that every 4 GPUs belong to the same computing enhancement unit, thus, the GPU computing module includes L computing enhancement units, each The computing enhancement units are all connected to the information processing module through a PCIE switching unit. For example, when L is 2, a schematic diagram of a computer system architecture provided by an embodiment of the present invention is shown in Figure 2, and a model diagram of the computer system architecture is shown in Figure 3, including an information processing module 1, a PCIE switching module and A GPU computing module, wherein the PCIE switching module includes a PCIE switching unit 21, and the GPU computing module includes a computing enhancement unit 31.

As a result, the layout of each module can be reasonably allocated during actual production, and it is avoided that the wrong component cannot be accurately positioned when the system detects an error due to the messy layout.

Preferably, in the computer system architecture provided by the foregoing embodiments, the information processing module may include an information processing unit, and the information processing unit may specifically be an X86 processor or an ARM (Advanced RISC (Reduced Instruction Set Computer, reduced instruction set computer) Machines, an advanced RISC machine )processor.

The information processing unit is the core of the information processing module, which completes the main work of the information processing unit, and the X86 processor or ARM processor is relatively excellent in terms of data processing capability and work efficiency, which is consistent with the requirements of the embodiment of the present invention. Information processing unit requirements.

Preferably, in the computer system architecture provided by the above embodiment, the number of information processing units may be two.

Therefore, when the computer system architecture provided by the embodiment of the present invention works normally, the work of the information processing module can be completed by two information processing units at the same time, avoiding the damage of the information processing unit due to overwork; and, when any When an information processing unit fails, the work of the information processing module can be completed by another information processing unit, so as to avoid affecting the overall operation of the computer system architecture.

Preferably, in the computer system architecture provided by the above-mentioned embodiments, the information processing module may also include a centralized management unit, and the centralized management unit is used to control the I/O (input/output, input/output) communication equipment for centralized management.

Thus, the centralized management unit can centrally manage the I/O communication equipment under the control of the information processing unit, can select the working status of the I/O communication equipment according to the needs, and know in time when any I/O communication equipment fails, In order to avoid affecting the overall operation of the system due to the long-term failure of I/O communication equipment.

Preferably, in the computer system architecture provided by the above embodiment, the information processing module may further include an information collection unit, which is used to monitor the temperature and voltage of the computer system architecture in real time under the control of the centralized management unit.

The information acquisition unit can monitor the temperature and voltage of the computer system architecture in real time, including the monitoring of all devices in the computer system architecture, so that when the temperature of any device does not meet the normal range or when the voltage of any device does not meet the normal range, it is promptly informed In order to avoid the temperature or voltage of any component not meeting the normal range and causing it to become a fault voltage, thereby affecting the overall operation of the system.

Preferably, in the computer system architecture provided by the foregoing embodiments, the centralized management unit and the information processing unit can be connected through a DMI (DirectMediaInterface, direct media interface) bus, and the centralized management unit and the information collection unit can be connected through a PCIE3.0x1 link connection.

The centralized management unit receives the instructions sent by the information processing unit through the DMI bus to centrally manage the I/O communication equipment according to the instructions, and the information acquisition unit receives the instructions sent by the centralized management unit through the PCIE3.0x1 link to monitor in real time according to the instructions Temperature and voltage of computer system architecture. Wherein, the information collection unit may specifically adopt an ASP2400 series chipset. Experiments have proved that the above connection mode conforms to the characteristics of data communication between related components, and can normally play a role in data communication while saving bandwidth resources.

When the information processing module includes an information processing unit 11 , a centralized management unit 12 and an information collection unit 13 , its structural diagram is shown in FIG. 3 .

Preferably, a kind of computer system framework that above-mentioned embodiment provides, computer system framework can also comprise SAS (SerialconnectionSCSI (SmallComputerSystemInterface, small computer system interface), serial connection SCSI) expansion module, SAS expansion module comprises M physical disks, M is a positive integer;

The SAS expansion module is connected to the information processing module through a PCIE3.0x8 link, and is used to complete data storage and reading under the control of the information processing module.

It should be noted that the specific value of M can be determined according to actual needs. In actual setup, the front end of the SAS expansion module can be used to install physical disks, and the rear end is connected to the system backplane through the hard disk backplane, and then connected to the information processing module by the system backplane. The information processing module may also include a disk controller, which is used to control the storage and reading and writing of data in the physical disk of the SAS expansion module.

Therefore, by adding a SAS expansion module to the computer system architecture, the data storage capacity of the entire system can be enhanced and the system's functions can be improved.

Preferably, in the computer system architecture provided in the foregoing embodiment, the information processing module may further include a disk storage array, and the disk storage array includes N physical disks, where N is a positive integer;

The disk storage array communicates with the SAS expansion module through SAS signals.

It should be noted that the specific value of N can be determined according to actual needs. For example, the disk storage array may include four 2.5-inch physical disks.

The disk storage array communicates with the SAS expansion module through the SAS signal. The SAS expansion module receives the control information sent by the information processing module, converts it into data based on the SAS signal, and then transmits it to the disk storage array to control the disk storage array. Storage and reading and writing of data on physical disks. Therefore, the data storage capacity of the system is enhanced through the cooperation of the disk storage array and the SAS expansion module, and when one of them fails, the other can complete the data storage, reading and writing, ensuring the normal operation of the system.

In addition, RAID0 or RAID5 can also be formed through the physical disks in the SAS expansion module to meet the requirements for high-speed data access or redundancy.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A kind of computer system framework, it is characterized in that, comprise information processing module, PCIE exchange module and GPU calculation module, described GPU calculation module comprises a plurality of GPUs, all carry out data communication by NVLink link between any two described GPUs The information processing module establishes a PCIE link connection with the GPU computing module through the PCIE switching module, and the information processing module and the GPU computing module perform data communication through the PICE link. 2. The computer system architecture according to claim 1, wherein data communication is carried out between the PCIE switching module and the information processing module through a PCIE3.0x8 link, and the PCIE switching module and the GPU computing The data communication between the modules is carried out through the PCIE3.0x16 link. 3. The computer system architecture according to claim 2, wherein the GPU calculation module includes L calculation enhancement units, the number of the GPUs is 4L, and each of the calculation enhancement units includes 4 calculation enhancement units. The GPU, the PCIE switching module includes L PCIE switching units, the PCIE switching units are connected to the computing enhancement unit in a one-to-one correspondence, and L is a positive integer. 4. The computer system architecture according to claim 1, wherein the information processing module comprises an information processing unit, and the information processing unit is specifically an X86 processor or an ARM processor. 5. The computer system architecture according to claim 4, wherein the number of the information processing units is two. 6. The computer system architecture according to claim 4, wherein the information processing module further comprises a centralized management unit configured to control the computer system architecture under the control of the information processing unit Centralized management of the I/O communication devices in the system. 7. The computer system framework according to claim 6, wherein the information processing module further comprises an information collection unit, and the information collection unit is used to control the computer system framework under the control of the centralized management unit Real-time monitoring of temperature and voltage. 8. The computer system architecture according to claim 7, characterized in that, the centralized management unit and the information processing unit are connected by a DMI bus, and the centralized management unit and the information collection unit are connected by a PCIE3 .0x1 link connection. 9. The computer system architecture according to any one of claims 1 to 8, wherein the computer system architecture also includes a SAS extension module, the SAS extension module includes M physical disks, and M is a positive integer; The SAS expansion module is connected to the information processing module through a PCIE3.0x8 link, and is used to complete data storage and reading under the control of the information processing module. 10. The computer system architecture according to claim 9, wherein the information processing module further includes a disk storage array, and the disk storage array includes N physical disks, where N is a positive integer; The disk storage array performs data communication with the SAS expansion module through SAS signals.