CN105049394A - Synchronous detection method based on synchronization sequence overcoming large frequency offset - Google Patents

Abstract

The invention discloses a synchronous detection method based on synchronization sequence overcoming large frequency offset. The method adopts a means of combining rough synchronization and fine synchronization. When rough synchronization fails, fine synchronization does not have to be conducted in order to save computing time. In addition, the rough synchronization firstly determines a large synchronization scope of position and then fine synchronization detection is performed. In this way, the synchronization time and computing complexity can be effectively reduced. The method provided in the invention adopts a new CAZAC sequence, which produces small deviation in position synchronization under the condition of high frequency offset, therefore, making the system quite suitable for the anti-frequency-offset request in a rough synchronization sequence.

Description

A kind of synchronization detecting method based on overcoming large frequency deviation synchronizing sequence

Technical field

The present invention relates to signal detection technique field, particularly relating to a kind of synchronization detecting method based on overcoming large frequency deviation synchronizing sequence.

Background technology

Frame receives synchronous, normally under 4 times or 8 sampling speed, realize the confirmation of sync bit, but the pseudo random sequence that existing synchronous detection algorithm adopts is when carrying out autocorrelation calculation, very responsive to frequency deviation, frequency deviation reaches certain thresholding and performance can be caused sharply to decline.Therefore can only use in the situation that frequency deviation is very little.Signal reception for antenna all can adopt 4xchip speed to receive (namely the sampling interval is 1/4Tc).Correlation value calculation calculates respectively for 4 samplings.Synchronizing sequence length adopts 4096 long (synchronizing sequence is longer, and the probability of synchronous empty inspection is lower, and net synchronization capability is also better).

The long W=4096chip of window of each synchronous window, the window's position offset Δ W=256chip, over-sampling multiple Rupsample=4.The s road Received signal strength that kth a antenna, a Nm window are corresponding is expressed as:

$r_s^{(ka,N_m)}\left(n\right)=\left(r_s^{\left(ka\right)}\right(n),r_s^{\left(ka\right)}(n+1),...,r_s^{\left(ka\right)}(n+W-1),...),n=N_m\·\mathrm{\Δ}W$

For strengthening net synchronization capability, the mode of sampling multistage cascade obtains correlation, section length Δ T=256chip:

${\mathrm{corr}}_s^{(ka,N_m)}(1:\mathrm{\Δ}T,C_m)=\underset{m=0}{\overset{\mathrm{\Δ}T-1}{\Σ}}\{\underset{n=0}{\overset{\mathrm{\Δ}T-1}{\Σ}}\left(r_s^{(ka,N_m)}\right(C_m\·\mathrm{\Δ}T+n+m)\·s^{*}(C_m\·\mathrm{\Δ}T+n))\},C_m=0,\mathrm{...},(\frac{W}{\mathrm{\Δ}T}-1)$

Wherein s (n) represents the local synchronization sequence (midamble sequence) of plural numberization, and Cm represents the index of modular cascade sequence.Each detection window needs to carry out 4096 long correlation computations, as long as the synchronous relevant peak-peak of this window does not reach synchronous thresholding, detection window is slip Δ W=256chip successively, points to next window, re-starts 4096 long correlation computations.If current window inter-sync detects successfully, so detection of end, and exports synchronized result: i.e. sync bit.

In the implementation procedure of above-mentioned existing technical scheme, the long W=4096chip of window of each synchronous window, the window's position offset Δ W=256chip, if sync bit more rearward, under limiting case, altogether need to carry out the long correlation computations of 64 (4096*4/ (256*4)) secondary 4096; The relevant amount of calculation brought of sliding is larger, and lock in time also can be longer.

Summary of the invention

In view of this, the invention provides a kind of synchronization detecting method based on overcoming large frequency deviation synchronizing sequence, the net synchronization capability under large frequency deviation can be improved, effectively reduce synchronous time and algorithm complex simultaneously.

A kind of synchronization detecting method based on overcoming large frequency deviation synchronizing sequence of the present invention, comprises the steps:

Step 1, thick synchronous detection:

Setting receiver sampling window width be 2048 × 4, and control receiver with the mode of 4 sampling speed to input data receive, obtain the 4 thick synchrodatas in road that length is 2048;

The thick synchrodata of local synchronization CAZAC sequence and every road is carried out relevant treatment respectively, obtains 4 row correlations; Judge in 4 row correlations, whether maximum is greater than the thick synchronous thresholding of setting:

If be more than or equal to, record the position in described maximum input data after sampling, as the thick sync bit of frame head, then perform step 2;

If be less than, then thought and do not find the thick sync bit of frame head by synchronization failure, the sampling window deflected length controlling receiver is 2048 × 4, returns step 1;

Wherein, the length of described CAZAC sequence is 2048, and its growth pattern is:

$x\left(n\right)=e^{-j\frac{\mathrm{\μ}n\·n}{pilotLen}};$

Wherein, μ represents the root sequence number of CAZAC sequence, 0≤n≤pilotLen-1, μ=3, pilotLen=2048;

Step 2, essence synchronously detect:

S201, according to the thick sync bit obtained in step 1, in the input data after the sampling that described step 1 receives, with the thick sync bit of described frame head for reference point moves forward p × 4 data point, as the synchronous starting point of essence; From the synchronous starting point of this essence, get the data that length is 2048 × 4, form 4 tunnel essence synchronizing sequences; Wherein, the span of p is 3 ~ 40;

S202, using Δ T=256 as section length, the local Midamble sequence being 2048 by each road essence synchronizing sequence and length obtains correlation by the mode of multistage cascade, namely obtains 4 row correlations;

S203, judge in 4 row correlations, whether maximum is greater than the synchronous thresholding of essence of setting:

If be more than or equal to, record the position at described maximum place, namely as the exact position of frame head, then perform step 3;

If be less than, then essence detects unsuccessfully, and the sampling window deflected length of control receiver is after 2048 × 4, returns step 1;

The exact position of step 3, output frame head.

The present invention has following beneficial effect:

The implementation that the synchronous detection algorithm of the present invention adopts thick synchronous+essence synchronous, thick synchronous time failure after, it is synchronous no longer to carry out essence, saving computing time; In addition, thick synchronously first determine a large sync bit scope, and then carry out precise synchronization detection, can effectively lower synchronous time and algorithm complex;

The present invention adopts new CAZAC sequence, can under high Frequency Offset, and sync bit can produce deviation (less than existing ZC sequence synchronization position deviation is many) among a small circle, can meet the anti-frequency deviation requirement of thick synchronizing sequence very well.

Accompanying drawing explanation

Fig. 1 is ZC sequence autocorrelator trace figure of the prior art;

Fig. 2 is ZC sequence auto-correlation of the prior art and CAZAC sequence autocorrelator trace figure comparative result of the present invention;

Fig. 3 be the ZC sequence of the new CAZAC sequence determined of the present invention and prior art in the energy of correlation peak and position with the situation of change of frequency deviation, wherein, sync bit is 100, SNR=25, frequency deviation respectively 0,10kHz and 20kHz;

Fig. 4 is that the slip correlation peak location of m sequence in the present invention is subject to frequency deviation and affects situation, and wherein, sync bit is 100, SNR=25, frequency deviation respectively 0,10kHz and 20kHz;

Fig. 5 is method flow diagram of the present invention.

Embodiment

To develop simultaneously embodiment below in conjunction with accompanying drawing, describe the present invention.

Because existing pseudo random sequence is when carrying out autocorrelation calculation, very responsive to frequency deviation, frequency deviation reaches certain thresholding and performance can be caused sharply to decline.Therefore can only use in the situation that frequency deviation is very little, therefore the present invention finds new CAZAC sequence nucleotide sequence, to overcoming the problem of large frequency deviation.

The generation expression formula of the ZC sequence used in LTE is as follows:

Wherein, N is sequence length, m=0,1 ..., N-1, μ are any positive integer relatively prime with N.

Go out below by the derivation of equation, ZC sequence deposits auto-correlation formula in case there being frequency deviation:

M=0, namely $corr\left(0\right)=r_0{s}_0^{*}+r_1{s}_1^{*}+......+r_{N-1}{s}_{N-1}^{*}$

M=1, namely $corr\left(1\right)=(r_0{s}_1^{*}+r_1{s}_2^{*}+......+r_{N-2}{s}_{N-1}^{*})+r_{N-1}{s}_0^{*}$

M=2, namely $corr\left(2\right)=(r_0{s}_2^{*}+r_1{s}_3^{*}+......+r_{N-3}{s}_{N-1}^{*})+r_{N-2}{s}_0^{*}+r_{N-1}{s}_1^{*}$

M=3, namely $corr\left(3\right)=(r_0{s}_3^{*}+r_1{s}_4^{*}+......+r_{N-4}{s}_{N-1}^{*})+r_{N-3}{s}_0^{*}+r_{N-2}{s}_1^{*}+r_{N-1}{s}_2^{*}$

Wherein, r represents after channel, the synchronizing sequence data received; S represents original synchronizing sequence.

$\begin{array}{c}\mathrm{co}rr\left(m\right)=\underset{n=0}{\overset{N-m-1}{\Σ}}\left(r_n{s}_{n+m}^{*}\right)+\underset{n=N-m}{\overset{N-1}{\Σ}}\left(r_n{s}_{n+m-N}^{*}\right),m=0,1,\mathrm{2......},N-1\\ =\underset{n=0}{\overset{N-m-1}{\Σ}}\exp (-\frac{{\mathrm{j\π\μn}}^2}{N}+j2{\mathrm{\πf}}_d{T}_{c}n+\frac{j\mathrm{\π}\mathrm{\μ}{(n+m)}^2}{N})+\underset{n=N-m}{\overset{N-1}{\Σ}}\exp (-\frac{{\mathrm{j\π\μn}}^2}{N}+j2{\mathrm{\πf}}_d{T}_{c}n+\frac{j\mathrm{\π}\mathrm{\μ}{(n+m-N)}^2}{N})\\ =\underset{n=0}{\overset{N-m-1}{\Σ}}\exp (j2{\mathrm{\πf}}_d{T}_{c}n+\frac{j\mathrm{\π}\mathrm{\μ}(m^2+2nm)}{N})+\underset{n=N-m}{\overset{N-1}{\Σ}}\exp (-\frac{{\mathrm{j\π\μn}}^2}{N}+j2{\mathrm{\πf}}_d{T}_{c}n+\frac{j\mathrm{\π}\mathrm{\μ}{(n+m-N)}^2}{N})\\ =\underset{n=N-m}{\overset{N-1}{\Σ}}\exp (-\frac{{\mathrm{j\π\μn}}^2}{N}+j2{\mathrm{\πf}}_d{T}_{c}n+\frac{j\mathrm{\π}\mathrm{\μ}{(n+m)}^2}{N})\\ =\exp \left(\frac{{\mathrm{j\π\μn}}^2}{N}\right)\underset{n=0}{\overset{N-1}{\Σ}}\·\exp (-\frac{j\mathrm{\π}\mathrm{\μ}2mn}{N}+j2{\mathrm{\πf}}_d{T}_{c}n)\end{array}$

Can be found out by above formula, the position affecting correlation peak is: identical at root sequence μ, under different frequency deviation scenes, correlation peak and correlation peak location affect comparatively large by frequency deviation, as shown in Figure 1.

For avoiding ZC sequence pair frequency deviation sensitive issue, devise a new CAZAC sequence, under formula is shown in:

$x\left(n\right)=e^{-j\frac{\mathrm{\μ}n\·n}{pilotLen}}$

The position of new CAZAC sequence autocorrelation peak than physical location offset very little, and secondary lobe is also very little, as shown in Figure 2.

Use brand-new CAZAC sequence, under different length, different frequency deviation, the position of correlation peak is in less deviation range all the time, and visible correlated performance can meet the requirement of thick synchronizing sequence.Determine so final to adopt this new CAZAC sequence as the thick synchronous synchronizing sequence used.

Below all with ideal synchronisation position for 100, SNR=25, frequency deviation respectively 0,5kHz, 10kHz and 20kHz be that example is described respectively, the energy of paper examines correlation peak and position are with the situation of change of frequency deviation.

The energy of the ZC sequence main peak of new CAZAC sequence of the present invention and existing LTE all slightly reduces with the increase of frequency deviation, and namely main peak energy still keeps higher; But exist under high Frequency Offset, sync bit can produce deviation among a small circle, and new CAZAC sequence nucleotide sequence of the present invention is when frequency deviation is up to 20kHz, sync bit skew is not still very large, and the ZC sequence synchronization position of LTE has offset very large, new CAZAC sequence nucleotide sequence of the present invention has met the anti-frequency deviation requirement of thick synchronizing sequence.

The generating mode of the new CAZAC sequence nucleotide sequence that the present invention determines is:

$x\left(n\right)=e^{-j\frac{\mathrm{\μ}n\·n}{pilotLen}},0\≤n\≤pilotLen-1$

Wherein: root sequence number is: μ=3, pilotLen=2048.

As shown in Figure 5, synchronization detecting method of the present invention comprises the steps:

Step 1, thick synchronous detection:

Setting receiver sampling window width be 2048 × 4, and control receiver with 4 times adopt speed mode to input data receive, obtain the 4 thick synchrodatas in road that length is 2048; Such as, when the data received are [a, b, c, d], 4 samplings are carried out to these data, namely 4 samplings are carried out to each data point, the sampled data then obtained is [a1, a2, a3, a4, b1, b2, b3, b4, c1, c2, c3, c4, d1, d2, d3, d4], then form the 4 thick synchrodatas in road, be: [a1, b1, c1, d1], [a2, b2, c2, d2], [a3, b3, c3, d3], [a4, b4, c4, d4].

The thick synchrodata of local synchronization CAZAC sequence and described every road is carried out relevant treatment respectively, obtains 4 row correlations; Judge in 4 row correlations, whether maximum is greater than the thick synchronous thresholding of setting:

If be more than or equal to, recorded row sequence number h and the line order k at described maximum place, namely determine the position of maximum in sampled data, as the coarse position of frame head, then perform step 2;

If be less than, then thought and do not find the coarse position of frame head by synchronization failure, the sampling window deflected length controlling receiver is 2048 × 4, returns step 1;

Wherein, the length of described new CAZAC sequence is 2048, and its generating mode is:

$x\left(n\right)=e^{-j\frac{\mathrm{\μ}n\·n}{pilotLen}},0\≤n\≤pilotLen-1$

Wherein, μ=3, pilotLen=2048;

Why the data of direct 2048 long local CAZAC sequences and reception are correlated with, and this sequence effectively can resist the phase effect that frequency deviation is brought, and just there is skew slightly synchronous position, and the size of side-play amount and frequency deviation has relation.The sliding length of thick synchronous window is 2048chip, can effectively lower synchronous time and algorithm complex.

Step 2, essence synchronously detect:

S201, according to the thick sync bit obtained in step 1, in the sampled data received in described step 1, with thick sync bit for reference point moves forward p × 4 data point, as this essence synchronously starting point; The smart synchrodata that length is 2048 × 4 is got from the synchronous starting point of this essence;

S202, using Δ T=256 as section length, the mode that M (Midamble) sequence being this locality of 2048 by each road essence synchronizing sequence and length carries out multistage cascade obtains correlation, namely obtains 4 row correlations; The length of described M sequence is 2048;

S203, judge in 4 row correlations, whether maximum is greater than the synchronous thresholding of essence of setting:

If be more than or equal to, the synchronous success of essence, records row sequence number h and the line order k at described maximum place, namely determines the smart position of frame head, then perform step 3;

If be less than, then represent that essence detects unsuccessfully, the sampling window deflected length of control receiver is after 2048 × 4, returns step 1;

The exact position of step 3, output frame head, in order to carry out synchronously signal.

Under the condition that there is frequency deviation, doing on reception synchronizing sequence the relevant frequency deviation that can be subject to of sliding affects.All with ideal synchronisation position for 100, SNR=25, frequency deviation respectively 0,10kHz and 20kHz be that example is described respectively, the energy of paper examines correlation peak and position are with the situation of change of frequency deviation.

As shown in Figures 3 and 4, the slip correlation peak location of m sequence can not be subject to frequency deviation impact, but peak energy presents the trend of reduction along with the increase of frequency deviation, the energy of new CAZAC sequence main peak slightly reduces with the increase of frequency deviation, but the amplitude of reduction is lower than m sequence, namely main peak energy still keeps higher, but exists under high frequency deviation example condition, and sync bit can produce deviation among a small circle.

In sum, these are only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (1)

1., based on the synchronization detecting method overcoming large frequency deviation synchronizing sequence, it is characterized in that, comprise the steps:

Step 1, thick synchronous detection:

Setting receiver sampling window width be 2048 × 4, and control receiver with the mode of 4 sampling speed to input data receive, obtain the 4 thick synchrodatas in road that length is 2048;

The thick synchrodata of local synchronization CAZAC sequence and every road is carried out relevant treatment respectively, obtains 4 row correlations; Judge in 4 row correlations, whether maximum is greater than the thick synchronous thresholding of setting:

If be more than or equal to, record the position in described maximum input data after sampling, as the thick sync bit of frame head, then perform step 2;

If be less than, then thought and do not find the thick sync bit of frame head by synchronization failure, the sampling window deflected length controlling receiver is 2048 × 4, returns step 1;

Wherein, the length of described CAZAC sequence is 2048, and its growth pattern is:

$x\left(n\right)=e^{-j\frac{\mathrm{\μ}n\·n}{pilotLen}};$

Wherein, μ represents the root sequence number of CAZAC sequence, 0≤n≤pilotLen-1, μ=3, pilotLen=2048;

Step 2, essence synchronously detect:

S201, according to the thick sync bit obtained in step 1, in the input data after the sampling that described step 1 receives, with the thick sync bit of described frame head for reference point moves forward p × 4 data point, as the synchronous starting point of essence; From the synchronous starting point of this essence, get the data that length is 2048 × 4, form 4 tunnel essence synchronizing sequences; Wherein, the span of p is 3 ~ 40;

S202, using Δ T=256 as section length, the local Midamble sequence being 2048 by each road essence synchronizing sequence and length obtains correlation by the mode of multistage cascade, namely obtains 4 row correlations;

S203, judge in 4 row correlations, whether maximum is greater than the synchronous thresholding of essence of setting:

If be more than or equal to, record the position at described maximum place, namely as the exact position of frame head, then perform step 3;

If be less than, then essence detects unsuccessfully, and the sampling window deflected length of control receiver is after 2048 × 4, returns step 1;

The exact position of step 3, output frame head.