CN105006449A - Preparation method for MTM anti-fuse unit structure - Google Patents
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- CN105006449A CN105006449A CN201510422692.3A CN201510422692A CN105006449A CN 105006449 A CN105006449 A CN 105006449A CN 201510422692 A CN201510422692 A CN 201510422692A CN 105006449 A CN105006449 A CN 105006449A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
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Abstract
The invention relates to a preparation method for an MTM anti-fuse unit structure. The preparation method includes steps: (1) accomplishing the deposition of a first intermetallic dielectric material and a lower layer metal material; (2) accomplishing the deposition of a first barrier layer material; (3) accomplishing the deposition of an anti-fuse dielectric material; (4) accomplishing the coating of an ion implantation barrier layer; (5) accomplishing the exposure and development of the ion implantation barrier layer; (6) accomplishing ion implantation; (7) accomplishing the deposition of a second barrier layer material; (8) accomplishing the etching of an anti-fuse dielectric layer; (9) accomplishing the etching of a lower layer metal layer; and (10) accomplishing the deposition and etching of a second intermetallic dielectric material and an upper layer metal material so that the MTM anti-fuse unit structure is formed. According to the preparation method, the process of ion implantation is employed so that the area in the anti-fuse dielectric layer with easy leakage realizes non-crystallization, the consistency of breakdown voltage of the anti-fuse dielectric layer is improved, and the MTM anti-fuse unit has smaller leakage characteristic and programming consistency with the same breakdown voltage.
Description
Technical field
The present invention relates to a kind of preparation method of antifuse unit structure, especially a kind of preparation method of the MTM antifuse unit structure applied on Bulk CMOS, extension EPI and silicon-on-insulator SOI material in integrated circuits.
Background technology
The technology of current programming device mainly contains three kinds: based on antifuse technology, based on Flash technology with based on SRAM technology.The feature of antifuse technology is: anti-fuse cell is in high resistant not on-state in the un-programmed state, and programmed rear anti-fuse cell is then in low-resistance conducting state.Programming device based on antifuse technology relies on the advantages such as its integrated level is high, speed is fast, reliability is high, non-volatile, hardware resource is abundant, capability of resistance to radiation is strong, becomes the mainstream technology of space field.
For anti-fuse cell, typically there are three kinds of structures: gate oxide antifuse unit structure, ONO antifuse unit structure, MTM antifuse unit structure.For deep submicron process, gate oxide antifuse unit structure, program voltage is lower, but resistance discreteness large (500 ohm ~ several megohm) after being less than the antifuse hole programming of 0.5 μm.ONO antifuse unit structure, program voltage is high, makes the requirement of withstand voltage of programming high-voltage tube higher, and the thickness of gate oxide is comparatively large, and the integrated level of ONO antifuse unit structure is lower relative to MTM antifuse unit structure simultaneously, conducting resistance and parasitic capacitance larger.It is low that MTM antifuse unit structure has program voltage, low to the requirement of withstand voltage of high-voltage tube, is conducive to the radiation hardened technique of high tension apparatus, is widely used in FPGA and PROM electronic product.
MTM anti-fuse cell is made up of two-layer dielectric layer and the antifuse dielectric layer between two-layer dielectric layer, then on upper strata metal to the through hole of lower metal or the complete MTM antifuse unit structure of lower formation.Its operation principle uses default program voltage and program current when being programming between the upper/lower electrode of MTM antifuse unit structure, antifuse dielectric layer burn through is allowed in very short programming time, make it have stable electrical characteristics conductive channel, then need to carry out programming to form different data messages according to integrated circuit.
MTM antifuse unit structure is owing to adopting antifuse medium (as silicon, silicon compound etc.), its leakage current is bigger than normal, when whole integrated circuit adopts a large amount of MTM antifuse unit structures, its leakage current is by jumbo increase, the application requirement of integrated circuit cannot be met, add the discreteness that the depositing technics of antifuse dielectric layer exists, the operating current of integrated circuit is large under normal circumstances, and the qualification rate of programming is low.
Summary of the invention
The technical problem to be solved in the present invention overcomes existing technical problem, a kind of preparation method of MTM antifuse unit structure is provided, ion implantation technology method is adopted to inject ion in antifuse dielectric layer, the region of easily electric leakage in antifuse dielectric layer is made to realize decrystallized, improve the consistency of antifuse dielectric layer puncture voltage, make MTM anti-fuse cell under identical puncture voltage, have less leakage current characteristic and programming consistency, finally greatly reduce the power consumption of MTM anti-fuse cell place integrated circuit.
In order to solve the problems of the technologies described above, the invention provides following technical scheme:
The preparation method of a kind of MTM antifuse unit structure of the present invention, comprises the following steps:
(1) based on the device layer of silicon substrate carrying out the first inter-metal medium deposition of materials, form the first intermetallic dielectric layer, then carry out underlying-metallic material deposit on the first intermetallic dielectric layer, form lower metal layer;
(2) in lower metal layer, carry out the first barrier material deposit, form the first barrier layer;
(3) on the first barrier layer, carry out the deposit of antifuse dielectric material, form antifuse dielectric layer;
(4) on antifuse dielectric layer, carry out gluing, form ion implantation barrier layer;
(5) the left and right two parts on ion implantation barrier layer are exposed, developed, leave mid portion;
(6) by the part that the ion implantation barrier layer that step (5) obtains stops, ion implantation technology process is not carried out to antifuse dielectric layer, complete after injecting and remove ion implantation barrier layer;
(7) on antifuse dielectric layer, carry out the second barrier material deposit, form the second barrier layer;
(8) etch left and right two parts of antifuse dielectric layer, the width leaving mid portion is greater than the width on the ion implantation barrier layer that step (5) obtains, and form the electric pole plate of antifuse unit structure, etching stopping is on the first barrier layer of lower floor;
(9) etch lower metal layer, form the lower electrode plate of antifuse unit structure, etching stopping is on the first intermetallic dielectric layer of lower floor;
(10) electric pole plate of the antifuse unit structure obtained in step (8) carries out the second inter-metal medium deposition of materials, form the second intermetallic dielectric layer, again the mid portion of the second intermetallic dielectric layer is etched, form through-hole structure, finally on the second intermetallic dielectric layer, carry out upper strata depositing metal material, form upper metal layers, upper metal layers is etched, form MTM antifuse unit structure.
Further, ion implantation technology process utilizes the ion produced in ion implantor, and by the energy of 30-80Kev, the dosage of 1E11-5E13 is not carried out ion implantation by the part that the ion implantation barrier layer that step (5) obtains stops to antifuse dielectric layer.
Further, the injection ionic type in ion implantation technology process is the one of Ar ion or silicon ion.
Further, the dielectric material in the antifuse dielectric layer obtained in step (3) is the one in amorphous silicon, polysilicon, silicon or silicon dioxide, and the thickness of antifuse dielectric layer is 30 ~ 150nm.
Further, the dielectric material in the ion implantation barrier layer obtained in step (4) is the one in photoresist, silicon nitride or silicon dioxide.
Further, the first inter-metal medium deposition of materials in step (1) and the second inter-metal medium deposition of materials in step (10) all adopt PECVD method; The second barrier material deposit in the first barrier material deposit in underlying-metallic material deposit in step (1), step (2), the antifuse dielectric material deposit in step (3), step (7) and the upper strata depositing metal material in step (10) all adopt magnetron sputtering method.
Further, the thickness of the second intermetallic dielectric layer obtained in the first intermetallic dielectric layer obtained in step (1) and step (10) is 500nm ~ 1200nm; The thickness of the upper metal layers obtained in the lower metal layer obtained in step (1) and step (10) is 400nm ~ 800nm; The material on the second barrier layer obtained in the first barrier layer obtained in step (1) and step (7) is the one in tungsten, tungsten titanium or titanium, and the thickness on the first barrier layer and the second barrier layer is 20nm ~ 300nm.
Beneficial effect of the present invention:
1. pair antifuse dielectric layer carries out selective ion implantation technology process, the region of easily electric leakage in antifuse dielectric layer is made to realize decrystallized, improve the consistency of antifuse dielectric layer puncture voltage, make MTM anti-fuse cell under identical puncture voltage, have less leakage current characteristic and programming consistency, finally greatly reduce the power consumption of MTM anti-fuse cell place integrated circuit.
The processing technology of 2.MTM anti-fuse cell is simple, and controllability is strong, has very strong operability.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for specification, together with embodiments of the present invention for explaining the present invention, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is based on the schematic diagram device layer of silicon substrate completing the first inter-metal medium deposit and lower metal deposit;
Fig. 2 has been the schematic diagram of the first barrier material deposit;
Fig. 3 has been the schematic diagram of antifuse dielectric material deposit;
Fig. 4 is the schematic diagram complete the coating of ion implantation barrier layer on antifuse dielectric layer after;
Fig. 5 is the schematic diagram after ion implantation barrier layer completes etching;
Fig. 6 is schematic diagram antifuse dielectric layer being carried out to ion implantation technology process;
Fig. 7 has been the schematic diagram of the second barrier layer deposition;
Fig. 8 is the schematic diagram after the electric pole plate of formation antifuse unit structure;
Fig. 9 is the schematic diagram after the lower electrode plate of formation antifuse unit structure;
Figure 10 is the overall schematic of MTM antifuse unit structure.
Description of reference numerals: 1-based on the device layer of silicon substrate, 2a-first intermetallic dielectric layer, 2b-second intermetallic dielectric layer, 3-lower metal layer, 4a-first barrier layer, 4b-second barrier layer, 5-antifuse dielectric layer, 6-upper metal layers, 7-ion implantation barrier layer.
Embodiment
Embodiment cited by the present invention; just understand the present invention for helping; should not be construed as limiting the scope of the present invention; for those skilled in the art; without departing from the inventive concept of the premise; can also improve the present invention and modify, these improve and modification also falls in the scope of the claims in the present invention protection.
The preparation method of a kind of MTM antifuse unit structure of the present invention, comprises the following steps:
(1) as shown in Figure 1, be 625nm at thickness, what meet SEMI standard adopts PECVD(plasma enhanced CVD based on the device layer 1 of silicon substrate) method carries out the first inter-metal medium deposition of materials, form the first intermetallic dielectric layer 2a that thickness is 500nm ~ 1200nm, on the first intermetallic dielectric layer 2a, adopt magnetron sputtering method to carry out underlying-metallic material deposit again, form the lower metal layer 3 that thickness is 400nm ~ 800nm;
(2) as shown in Figure 2, lower metal layer 3 adopt magnetron sputtering method carry out the first barrier material (one in tungsten, tungsten titanium or titanium) deposit, form the first barrier layer 4a that thickness is 20nm ~ 300nm, antifuse dielectric material and underlying-metallic material for preventing deposit in step 3 react, and cause inefficacy;
(3) as shown in Figure 3, the first barrier layer 4a adopts magnetron sputtering method carry out antifuse dielectric material (one in amorphous silicon, polysilicon, silicon or silicon dioxide) deposit, form the antifuse dielectric layer 5 that thickness is 30nm ~ 150nm;
(4) as shown in Figure 4, antifuse dielectric layer 5 carries out gluing, form ion implantation barrier layer 7, dielectric material is wherein the one in photoresist, silicon nitride or silicon dioxide;
(5) as shown in Figure 5, the left and right two parts on ion implantation barrier layer 7 are exposed, developed, leaves mid portion, for ion implantation technology is prepared;
(6) as shown in Figure 6, utilize the ion (one in Ar ion or silicon ion) produced in ion implantor, by the energy of 30-80Kev, the dosage of 1E11-5E13 is not carried out ion implantation technology process by the part that the ion implantation barrier layer 7 that step (5) obtains stops to antifuse dielectric layer 5, antifuse dielectric layer 5 is not realized by stop portions decrystallized, complete after injecting and remove ion implantation barrier layer 7;
(7) as shown in Figure 7, antifuse dielectric layer 5 adopt magnetron sputtering method carry out the second barrier material (one in tungsten, tungsten titanium or titanium) deposit, form the second barrier layer 4b that thickness is 20nm ~ 300nm, for preventing the dielectric material in the antifuse dielectric layer 5 of ion implantation process that obtains in step (6) and upper strata metal material from reacting, cause inefficacy;
(8) as shown in Figure 8, left and right two parts of antifuse dielectric layer 5 are etched, the width leaving mid portion is greater than the width on the ion implantation barrier layer 7 that step (5) obtains, just in time also there is non-crystallization degree in antifuse dielectric layer 5 both sides of the edge (region of namely easily leaking electricity) after making to etch, thus reduction antifuse dielectric layer 5 leaks electricity, form the electric pole plate of antifuse unit structure, etching stopping is on the first barrier layer 4a of lower floor;
(9) as shown in Figure 9, etch lower metal layer 3, form the lower electrode plate of antifuse unit structure, etching stopping is on the first intermetallic dielectric layer 2a;
(10) as shown in Figure 10, the electric pole plate of the antifuse unit structure obtained in step (8) adopts PECVD(plasma enhanced CVD) method carries out the second inter-metal medium deposition of materials, form the second intermetallic dielectric layer 2b that thickness is 500nm ~ 1200nm, again the mid portion of the second intermetallic dielectric layer 2b is etched, form through-hole structure, finally on the second intermetallic dielectric layer 2b, magnetron sputtering method is adopted to carry out upper strata depositing metal material, form the upper metal layers 6 that thickness is 400nm ~ 800nm, upper metal layers 6 is etched, form MTM antifuse unit structure.
The present invention adopts ion implantation technology processing method, the type injecting ion is the one of Ar ion or silicon ion, the ion of this two type is more stable, neutral or easily form covalent bond, unnecessary electronics is not had to move, and implanting p-type or N-type ion can cause antifuse dielectric layer 5 to become conductive semiconductor, voltage is had to leak electricity; Ion implantor is cleaner, is not easy to cause secondary to stain to antifuse dielectric layer 5, controls and implantation homogeneity is good simultaneously easily; The thickness of the ion implantation energy of ion implantor and the selection of dosage and ion implantation type, antifuse dielectric layer 5 is relevant, energy, dosage need to mate with the thickness of antifuse dielectric layer 5, thus realize comparatively Low dark curient, that improves antifuse dielectric layer 5 punctures uniformity; The thickness of material at all levels is according to concrete technology platform selecting; The mid portion of antifuse dielectric layer 5 is not decrystallized or non-crystallization degree is not high, default program voltage and program current is used in order to allow between the upper and lower electrode of MTM anti-fuse cell, in very short programming time, make antifuse dielectric layer 5 burn through, make it have stable electrical characteristics conductive channel.
Claims (7)
1. a preparation method for MTM antifuse unit structure, is characterized in that: comprise the following steps:
Carrying out the first inter-metal medium deposition of materials based on the device layer (1) of silicon substrate, form the first intermetallic dielectric layer (2a), then carry out underlying-metallic material deposit on the first intermetallic dielectric layer (2a), form lower metal layer (3);
(2) in lower metal layer (3), carry out the first barrier material deposit, form the first barrier layer (4a);
(3) on the first barrier layer (4a), carry out the deposit of antifuse dielectric material, form antifuse dielectric layer (5);
(4) on antifuse dielectric layer (5), carry out gluing, form ion implantation barrier layer (7);
(5) the left and right two parts of ion implantation barrier layer (7) are exposed, developed, leave mid portion;
(6) by the part that the ion implantation barrier layer (7) that step (5) obtains stops, ion implantation technology process is not carried out to antifuse dielectric layer (5), complete after injecting and remove ion implantation barrier layer (7);
(7) on antifuse dielectric layer (5), carry out the second barrier material deposit, form the second barrier layer (4b);
(8) left and right two parts of antifuse dielectric layer (5) are etched, the width leaving mid portion is greater than the width on the ion implantation barrier layer (7) that step (5) obtains, form the electric pole plate of antifuse unit structure, etching stopping is on first barrier layer (4a) of lower floor;
(9) etch lower metal layer (3), form the lower electrode plate of antifuse unit structure, etching stopping is on first intermetallic dielectric layer (2a) of lower floor;
(10) electric pole plate of the antifuse unit structure obtained in step (8) carries out the second inter-metal medium deposition of materials, form the second intermetallic dielectric layer (2b), again the mid portion of the second intermetallic dielectric layer (2b) is etched, form through-hole structure, finally on the second intermetallic dielectric layer (2b), carry out upper strata depositing metal material, form upper metal layers (6), upper metal layers (6) is etched, form MTM antifuse unit structure.
2. the preparation method of MTM antifuse unit structure according to claim 1, it is characterized in that: described ion implantation technology process utilizes the ion produced in ion implantor, by the energy of 30-80Kev, the dosage of 1E11-5E13 is not carried out ion implantation by the part that the ion implantation barrier layer (7) that step (5) obtains stops to antifuse dielectric layer (5).
3. the preparation method of MTM antifuse unit structure according to claim 1 and 2, is characterized in that: the injection ionic type in described ion implantation technology process is the one of Ar ion or silicon ion.
4. the preparation method of MTM antifuse unit structure according to claim 1, it is characterized in that: the dielectric material in the antifuse dielectric layer (5) obtained in described step (3) is the one in amorphous silicon, polysilicon, silicon or silicon dioxide, and the thickness of antifuse dielectric layer (5) is 30 ~ 150nm.
5. the preparation method of MTM antifuse unit structure according to claim 1, is characterized in that: the dielectric material in the ion implantation barrier layer (7) obtained in described step (4) is the one in photoresist, silicon nitride or silicon dioxide.
6. the preparation method of MTM antifuse unit structure according to claim 1, is characterized in that: the first inter-metal medium deposition of materials in described step (1) and the second inter-metal medium deposition of materials in step (10) all adopt PECVD method; The second barrier material deposit in the first barrier material deposit in underlying-metallic material deposit in described step (1), step (2), the antifuse dielectric material deposit in step (3), step (7) and the upper strata depositing metal material in step (10) all adopt magnetron sputtering method.
7. the preparation method of MTM antifuse unit structure according to claim 1, is characterized in that: the thickness of the second intermetallic dielectric layer (2b) obtained in the first intermetallic dielectric layer (2a) obtained in described step (1) and step (10) is 500nm ~ 1200nm; The thickness of the upper metal layers (6) that the lower metal layer (3) obtained in described step (1) and step (10) obtain is 400nm ~ 800nm; The material on the second barrier layer (4b) obtained in the first barrier layer (4a) obtained in described step (1) and step (7) is the one in tungsten, tungsten titanium or titanium, and the thickness of the first barrier layer (4a) and the second barrier layer (4b) is 20nm ~ 300nm.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105448888A (en) * | 2014-08-21 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Interlayer dielectric layer, manufacturing method thereof, and semiconductor device |
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| US5821558A (en) * | 1995-12-29 | 1998-10-13 | Vlsi Technology, Inc. | Antifuse structures |
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| JPH046873A (en) * | 1990-04-24 | 1992-01-10 | Seiko Epson Corp | Semiconductor device |
| US5353246A (en) * | 1991-10-18 | 1994-10-04 | Lattice Semiconductor Corporation | Programmable semiconductor antifuse structure and method of fabricating |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448888A (en) * | 2014-08-21 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Interlayer dielectric layer, manufacturing method thereof, and semiconductor device |
| CN105448888B (en) * | 2014-08-21 | 2019-02-26 | 中芯国际集成电路制造(上海)有限公司 | Interlayer dielectric layer, the production method of interlayer dielectric layer and semiconductor devices |
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