CN104993804B - A kind of processing method of MEMS resonant structure - Google Patents
A kind of processing method of MEMS resonant structure Download PDFInfo
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Abstract
The present invention discloses a kind of processing method of MEMS resonant structure, there is provided Silicon Wafer is as substrate silicon, in the mask layer of superficial growth first of substrate silicon；Opening patterns are processed on the first mask layer；The first mask layer and substrate silicon with opening patterns corresponding part is removed by dry etching, groove structure is formed in substrate silicon；The mask layer of growth regulation two, the second mask layer is formed in the recess sidewall and bottom portion of groove of the groove structure, compound mask layer is formed in the substrate silicon surface；Second mask layer is removed by dry etching, second mask layer of the bottom portion of groove is all removed；The substrate silicon is performed etching again by dry etching, deepens the groove structure, and does not have mask layer covering in the recess sidewall for newly to etch；By wet etching, open communication pattern forms cavity inside the substrate silicon；Deposit bottom electrode, piezoelectricity functional material and Top electrode；Graphically and resonance structure is discharged by dry etching.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of processing method of MEMS resonant structure, especially
Be related to it is a kind of on same wafer and meanwhile the resonance structure that makes different silicon film thicknesses method.
Background technology
MEMS oscillator refers to a kind of programmable oscillator produced by MEMS, and it is to conventional quartz
One upgrading of crystal oscillator product updates, and shockproof effect is the former 25 times, has not affected by vibration, non-friable spy
Point.
There are as below methods for the processing of MEMS resonant structure in the prior art：
1st, the substrate wafer after its surface oxidation with another pre-processed cavity is bonded in one using SOI wafer
Rise.After SOI wafer is thinned, then upper lower metal electrode, piezoelectricity functional material and electrode of metal are deposited respectively.Last figure
After changing electrode of metal, then top layer silicon is carved out, discharge resonance structure.Or SOI wafer is still based on, it is raw in the SOI wafer
After long insulating barrier, deposit lower metal electrode, piezoelectricity functional material and electrode of metal, patterned metal Top electrode, finally from
Wafer rear removes substrate silicon, discharges resonance structure.
2nd, using general substrate, utilize " cavity on silicon substrate ", to realize that the suspension structure of resonance structure manufactures.Its base
Present principles are to etch two-dimentional stria or thin cylindrical cavity on a silicon substrate, and the physics migrated using high temperature lower surface silicon atom is showed
As being finally closed into a complete silicon fiml by high annealing (annealing), there is a cavity below silicon fiml.In shape
While into silicon fiml, aperture can be reserved on silicon fiml, or is formed after silicon fiml, then etches aperture.Utilize these apertures, silicon
The two sides of film can be oxidized to form silica material, reach the work that original silicon materials are carried out with resonant frequency temperature-compensating
With.After silicon oxide layer is carried out, equally deposit bottom electrode, piezoelectricity functional material and Top electrode, graphical Top electrode with
Afterwards, carved from wafer frontside and open silicon fiml, discharge resonating device.
The defects of above method, is：SOI wafer is used, although technique is relatively easy, the cost of SOI wafer is very
It is high.Secondly, wafer bonding technique has been used, cost is high, and yield is nor be easily controlled；Discharged using the method for back-etching
Resonance structure, when silica material is etched into, it is difficult to avoid having some over etchings, so cause the oxygen on silicon fiml two sides
Silicon nitride material variable thickness causes, and reduces the performance of device.
" cavity on the silicon substrate " technology of utilization processes suspension structure on common Silicon Wafer, and cost has excellent than SOI wafer
Gesture.But this special process technology is, it is necessary to specific annealing device, including high temperature (being typically greater than 1050 DEG C) and special
Atmosphere (hydrogen or argon gas) is very big for the fixed assets investment of chip foundries.
The content of the invention
It is an object of the present invention to：A kind of processing method of MEMS resonant structure is provided, it uses common Silicon Wafer
As substrate silicon, it is not necessary to which, using expensive SOI wafer, the cost of material is low.
It is another object of the present invention to：A kind of processing method of MEMS resonant structure is provided, process need not adopt
With special process equipment, production cost is reduced.
Another object of the present invention is：A kind of processing method of MEMS resonant structure is provided, it can be in same
The resonance structure of different thickness is processed on Silicon Wafer.
To use following technical scheme up to this purpose, the present invention：
A kind of processing method of MEMS resonant structure, comprises the following steps：
Step S1, Silicon Wafer is provided as substrate silicon, in the mask layer of superficial growth first of the substrate silicon；
Step S2, opening patterns are processed on first mask layer；
Step S3, first mask layer and the substrate silicon of the removal with the opening patterns corresponding part, in institute
State and groove structure is formed in substrate silicon；
Step S4, the mask layer of growth regulation two, form second in the recess sidewall and bottom portion of groove of the groove structure and cover
Film layer, compound mask layer is formed in the substrate silicon surface；
Step S5, etching removes second mask layer, second mask layer of the bottom portion of groove is all removed,
And substrate silicon surface and recess sidewall still have mask layer covering；
Step S6, the substrate silicon is performed etching again, deepens the groove structure, form second level groove, and
So that there is no mask layer covering in the recess sidewall newly etched；
Step S7, by wet etching, open communication pattern forms cavity inside the substrate silicon；
Step S8, bottom electrode, piezoelectricity functional material and Top electrode are deposited；
Step S9, it is graphical and resonance structure is discharged by dry etching.
The processing method of MEMS resonant structure according to claim 1, it is characterised in that the step S7 is also wrapped
Include：
Step S71, after the completion of wet etching, all mask Rotating fields before removing；
Step S72, one or more layers resonance structure frequency temperature is uniformly grown again in all surface of the substrate silicon
Spend compensating material layer.
Preferably, the resonance structure temperature frequency compensating material layer uses silica material.
As a kind of optimal technical scheme of the processing method of MEMS resonant structure, graphical specific bag described in step S9
Include：
Step S91, graphical Top electrode；
Step S92, graphical piezoelectricity functional material；
Step S93, graphical bottom electrode；
Step S94, graphical resonance structure.
As a kind of optimal technical scheme of the processing method of MEMS resonant structure, the opening patterns is multigroup, every group
Two dimension of picture are identical in the opening patterns, and it is different that difference organizes the opening patterns dimension of picture.
As a kind of optimal technical scheme of the processing method of MEMS resonant structure, while etch multigroup opening figure
Sample, multigroup opening patterns are made to form the groove structure of different depth.
As a kind of optimal technical scheme of the processing method of MEMS resonant structure, the etching is carved using deep reactive ion
Lose (DRIE).
As a kind of optimal technical scheme of the processing method of MEMS resonant structure, the opening patterns is multigroup, every group
Dimension of picture is identical in the opening patterns, and it is identical that difference organizes the opening patterns dimension of picture.
As a kind of optimal technical scheme of the processing method of MEMS resonant structure, to opening patterns described in one of which
During performing etching, using other pattern positions on protection materials protection wafer, it is avoided to etch.
As a kind of optimal technical scheme of the processing method of MEMS resonant structure, the protection materials are photoresist.
As a kind of optimal technical scheme of the processing method of MEMS resonant structure, the substrate silicon uses the ＞ crystal orientation of ＜ 111
Silicon Wafer, the mask layer uses silica material, and the wet etching uses potassium hydroxide (KOH) or tetramethyl hydrogen-oxygen
Change ammonium (TMAH) etchant solution.
Beneficial effects of the present invention are：Whole set process avoids, using expensive SOI wafer, using common MEMS foundries showing
Some process equipments complete whole technological process, reduce material cost and production equipment cost；It is resonance knot in production process
Structure provides passive temperature-compensating, can reduce the frequency-temperature coefficient of resonance structure, reach more preferable frequency stability；Can be
With the resonance structure that different thickness are processed on wafer；It can be processed in the case where extra light shield need not be increased
The silicon fiml of different-thickness；When increasing extra light shield processing resonance structure, different thickness can be more accurately controlled.
Brief description of the drawings
The present invention is described in further detail below according to drawings and examples.
Fig. 1 is the processing method flow chart of MEMS resonant structure described in embodiment.
Fig. 2 is that substrate silicon surface described in embodiment covers the first mask layer structural representation.
Fig. 3 is that dry etching removes the first mask layer and section substrate silicon structure schematic diagram in pattern.
Fig. 4 be in Fig. 3 A-A to sectional view.
Fig. 5 is structural representation after the second mask layer of growth.
Fig. 6 is to etch away structural representation after the mask layer of groove structure bottom second.
Fig. 7 is that dry etching performs etching rear structural representation to the substrate silicon again.
Fig. 8 is that open communication pattern forms structural representation after cavity inside the substrate silicon by wet etching.
Fig. 9 is schematic diagram after all mask Rotating fields of removing.
Figure 10 is structural representation after growth silicon dioxide material layer.
Figure 11 is Fig. 9 top views (figure in figure within dotted line is the cavity pattern that corrosion is formed).
Figure 12 is structural representation after deposit bottom electrode, piezoelectricity functional material, Top electrode simultaneously graphical Top electrode.
Figure 13 is graphical piezoelectricity functional material, bottom electrode and dry etching release resonance structure schematic diagram.
Figure 14 is to make different size figure structural representations in the first mask layer in an embodiment.
Figure 15 is structural representation after etching.
Figure 16 is structural representation after the second mask layer of making.
Figure 17 is different depth forms cavity structure schematic diagram in substrate silicon after wet etching.
Figure 18 is to make identical size figure structural representation in the first mask layer in another embodiment.
Figure 19 is the structural representation of figure beyond protection etching groove.
Figure 20 is the structural representation that figure beyond etching groove is protected when etching another figure.
Figure 21 is structural representation after the second mask layer of making.
Figure 22 is to perform etching rear structural representation to the substrate silicon again.
Figure 23 is different depth forms cavity structure schematic diagram in substrate silicon after wet etching.
In figure：
1st, substrate silicon；2nd, the first mask layer；3rd, the second mask layer；4th, groove structure；5th, second level groove；6th, cavity；7、
Earth silicon material；8th, photoresist.
Embodiment
Further illustrate technical scheme below in conjunction with the accompanying drawings and by embodiment.
As shown in figures 1-13：
A kind of processing method of MEMS resonant structure, comprises the following steps：
Step S1, Silicon Wafer is provided as substrate silicon 1, in the first mask layer of superficial growth 2 of the substrate silicon 1；
Step S2, opening patterns are processed on first mask layer 2；
Step S3, the first mask layer 2 and substrate silicon with the opening patterns corresponding part are removed by dry etching
1, groove structure 4 is formed in substrate silicon 1；
Step S4, the mask layer 3 of growth regulation two, second is formed in the recess sidewall and bottom portion of groove of the groove structure 4
Mask layer 3, compound mask layer is formed on the surface of substrate silicon 1；
Step S5, second mask layer 3 is removed by dry etching, makes the bottom portion of groove and substrate silicon surface
Second mask layer 3 all removes；
Step S6, the substrate silicon 1 is performed etching again by dry etching, deepens the groove structure 4, formed
Second level groove 5, and there is no mask layer covering in the part recess side wall for newly to etch；
Step S7, cavity 6 is formed in the inside open communication pattern of substrate silicon 1 by wet etching；
Step S71, all mask Rotating fields before being removed by wet etching；
Step S72,7 layers of earth silicon material is grown in the substrate silicon 1；
Step S8, bottom electrode, piezoelectricity functional material and Top electrode are deposited；
Step S9, graphical Top electrode；Graphical piezoelectricity functional material；Graphical bottom electrode；Graphical resonance structure is simultaneously
Resonance structure is discharged by dry etching.
The substrate silicon 1 described in the present embodiment uses the Silicon Wafer of the ＞ crystal orientation of ＜ 111, and the mask layer uses silica material
Material, the wet etching use potassium hydroxide (KOH) etchant solution.
Specifically：Use<111>The Silicon Wafer of crystal orientation grows one layer of silica as substrate silicon 1 first in substrate silicon 1
Material is as the first mask layer.Make a series of small opening patterns by lithography on the first mask layer, and use dry etching, remove
Component masking layer and substrate silicon 1.The thickness of dry etching substrate silicon 1 determines the thickness of resonance structure.
On this basis, second layer silica is grown as the second mask layer 3, due to the first mask layer before crystal column surface
2 are not removed, therefore form the compound mask layer of the first mask layer 2 and the second mask layer 3 in crystal column surface.
Without any graphical treatment, directly the second mask layer of bottom portion of groove is removed using the method for dry etching.
Because the thickness of compound mask layer is more than the thickness of the second mask layer 3, so be completely removed when the mask layer of bottom portion of groove
When, crystal column surface still has mask layer protection, and because the anisotropy of dry etching, recess sidewall also still have mask layer
Protection.
Without any graphical treatment, deep reaction ion etching DRIE technologies are directly used, continue to carve deeper recessed
Groove.Because the dry etching of use has the selectivity of good mask layer and silicon, therefore, the same of deeper groove is being carved
When, it can be ignored substantially for crystal column surface and the mask layer of recess sidewall etching.
It is rotten for silicon materials using it directly using potassium hydroxide (KOH) etchant solution without any graphical treatment
Anisotropic of the erosion along different crystal orientations, corrodes and a chamber and hanging silicon fiml.All mask layers before wet etching removal
After, newly grow one layer of uniform earth silicon material 7.The purpose for growing this layer of material be using earth silicon material 7 with
The characteristics of Young's modulus temperature coefficient symbol of silicon materials is opposite, carry out the passive temperature-compensating of resonance knot resonant frequency.
Bottom electrode, piezoelectricity functional material and Top electrode, and graphical Top electrode are deposited on the basis of this respectively.Continue figure
Change piezoelectricity functional material and bottom electrode, expose bottom electrode to facilitate follow-up electrical connection.Last graphical and dry etching release
Resonance structure.
As shown in Fig. 1,14-17：
Silicon Wafer is provided as substrate silicon 1, in the first mask layer of superficial growth 2 of the substrate silicon 1, is covered described first
When being patterned in film layer 2, groove structure 4 of different sizes is opened up,
A kind of processing method of MEMS resonant structure, comprises the following steps：
Step S1, the Silicon Wafer of the ＞ crystal orientation of ＜ 111 is provided as substrate silicon 1, is covered in the superficial growth first of the substrate silicon 1
Film layer 2；
Step S2, the different opening patterns of processing dimension on first mask layer 2；
Step S3, the first mask layer 2 and substrate silicon with the opening patterns corresponding part are removed by dry etching
1, groove structure 4 is formed in substrate silicon 1；
, can due to the etch rate of dry etching (DRIE) relation directly proportional to the size of opening (DRIE lag effects)
To form the groove of different depth in an etching process, the groove of these different depths also determines resonance structure silicon fiml
Thickness is different.
Step S4, the mask layer 3 of growth regulation two, second is formed in the recess sidewall and bottom portion of groove of the groove structure 4
Mask layer 3, compound mask layer is formed on the surface of substrate silicon 1；
Step S5, second mask layer 3 is removed by dry etching, makes second mask layer of the bottom portion of groove
3 all remove, and substrate silicon surface and recess sidewall still have mask layer covering；
Step S6, the substrate silicon 1 is performed etching again by dry etching, deepens the groove structure 4, formed
Second level groove 5, and there is no mask layer covering in the recess sidewall for newly to etch；
Also due to the relation that dry etching (DRIE) etch rate is directly proportional to the size of opening, second level groove 5
Depth is also different.
Step S7, using TMAH (TMAH) etchant solution, by wet etching inside the substrate silicon 1
Open communication pattern forms cavity 6；
Step S71, all mask Rotating fields before being removed by wet etching；
Step S72, regrowed 7 layers of earth silicon material in all surface of the substrate silicon 1；
Step S8, bottom electrode, piezoelectricity functional material and Top electrode are deposited；
Step S9, graphical Top electrode, graphical piezoelectricity functional material, graphical bottom electrode, and released by dry etching
Put resonance structure.
By this method, the resonance structure of different silicon film thicknesses can be processed on same wafer.
As shown in Fig. 1,18-23：
The difference of the present embodiment and above-described embodiment is, when pattern is made after the mask layer 2 of growth regulation on Silicon Wafer one
The size making of pattern is identical, during dry etching, other patterns are used into light when etching the groove of different depth
Photoresist 8 is protected, and is etched since the shallow groove of etching depth and is successively finished the recess etch of different depth on wafer
By that analogy, the etching of groove structure 4 of different depth on wafer is finished.According still further to the growth regulation two described before
The method of layer mask layer 3 and etching, form second level groove 5.Because the A/F of groove structure 4 is consistent, therefore the second level is recessed
The depth of groove 5 is the same.Finally corrode the resonance structure silicon fiml for different-thickness with the method for wet etching.
In description herein, it is to be understood that the orientation such as term " on ", " under " or position relationship is based on accompanying drawing institutes
The orientation or position relationship shown, it is for only for ease of description and simplifies operation, rather than indicates or imply signified device or member
Part must have specific orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.This
Outside, term " first ", " second ", it is used only for being distinguish between in description, not special implication.
It is to be understood that above-mentioned embodiment is only that presently preferred embodiments of the present invention and institute's application technology are former
Reason, in technical scope disclosed in this invention, change that any one skilled in the art is readily apparent that or
Replace, should all cover within the scope of the present invention.
Claims (9)
1. a kind of processing method of MEMS resonant structure, it is characterised in that comprise the following steps：
Step S1, Silicon Wafer is provided as substrate silicon, in the mask layer of superficial growth first of the substrate silicon；
Step S2, opening patterns are processed on first mask layer；
Step S3, first mask layer and the substrate silicon of the removal with the opening patterns corresponding part, in the lining
Groove structure is formed on the silicon of bottom；
Step S4, the mask layer of growth regulation two, the second mask layer is formed in the recess sidewall and bottom portion of groove of the groove structure,
Compound mask layer is formed in the substrate silicon surface；
Step S5, etching removes second mask layer, second mask layer of the bottom portion of groove is all removed, and serves as a contrast
Bottom silicon face and recess sidewall still have mask layer covering；
Step S6, the substrate silicon is performed etching again, deepens the groove structure, form second level groove, and cause
There is no mask layer covering in the recess sidewall newly etched；
Step S7, by wet etching, open communication pattern forms cavity inside the substrate silicon；
Step S8, bottom electrode, piezoelectricity functional material and Top electrode are deposited；
Step S9, it is graphical and resonance structure is discharged by dry etching；
The step S7 also includes：
Step S71, after the completion of wet etching, all mask Rotating fields before removing；
Step S72, the drift of one or more layers resonance structure frequency temperature is uniformly grown again in all surface of the substrate silicon
Move compensating material layer.
2. the processing method of MEMS resonant structure according to claim 1, it is characterised in that graphical described in step S9
Specifically include：
Step S91, graphical Top electrode；
Step S92, graphical piezoelectricity functional material；
Step S93, graphical bottom electrode；
Step S94, graphical resonance structure.
3. the processing method of MEMS resonant structure according to claim 1, it is characterised in that the opening patterns are more
Group, two dimension of picture are identical in opening patterns described in every group, and it is different that difference organizes the opening patterns dimension of picture.
4. the processing method of MEMS resonant structure according to claim 3, it is characterised in that while etch multigroup described open
Mouth pattern, makes multigroup opening patterns form the groove structure of different depth.
5. the processing method of MEMS resonant structure according to claim 4, it is characterised in that the etching is using deep reaction
Ion etching (DRIE).
6. the processing method of MEMS resonant structure according to claim 1, it is characterised in that the opening patterns are more
Group, dimension of picture is identical in opening patterns described in every group, and it is identical that difference organizes the opening patterns dimension of picture.
7. the processing method of MEMS resonant structure according to claim 6, it is characterised in that to being opened described in one of which
During mouth pattern performs etching, using other pattern positions on protection materials protection wafer, it is avoided to etch.
8. the processing method of MEMS resonant structure according to claim 7, it is characterised in that the protection materials are photoetching
Glue.
9. the processing method of MEMS resonant structure according to any one of claim 1 to 8, it is characterised in that the lining
Bottom silicon uses the Silicon Wafer of the ＞ crystal orientation of ＜ 111, and the mask layer uses silica material, and the wet etching uses potassium hydroxide
Or TMAH (TMAH) etchant solution (KOH).
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| CN105245198A (en) * | 2015-11-13 | 2016-01-13 | 中国科学院上海微系统与信息技术研究所 | Temperature compensation structure of micromechanical silicon resonator and manufacture method thereof |
| CN106840469A (en) * | 2015-12-04 | 2017-06-13 | 上海新微技术研发中心有限公司 | Pressure sensor integrated with multiple gears and manufacturing method thereof |
| WO2020082245A1 (en) * | 2018-10-23 | 2020-04-30 | 华为技术有限公司 | Method for preparing monolithic integrated baw resonator |
| CN112073025B (en) * | 2020-09-23 | 2024-02-02 | 浙江大学 | Self-supporting air gap type bulk acoustic wave resonator based on porous silicon and preparation method thereof |
| CN112871614B (en) * | 2021-01-12 | 2022-03-15 | 武汉大学 | MEMS ultrasonic transducer with high emission performance |
| CN115465834B (en) * | 2022-09-21 | 2024-08-09 | 四川广义微电子股份有限公司 | MEMS resonance structure based on temperature compensation and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1749153A (en) * | 2005-09-16 | 2006-03-22 | 中国电子科技集团公司第二十四研究所 | Method for producing MEMS sensor suspension beam structure |
| CN102190284A (en) * | 2010-03-11 | 2011-09-21 | 苏州敏芯微电子技术有限公司 | MEMS sensor and methods for manufacturing MEMS sensor, film, mass block and cantilever beam |
| CN102320560A (en) * | 2011-09-14 | 2012-01-18 | 上海先进半导体制造股份有限公司 | Production method of MEMS component film |
| CN102502479A (en) * | 2011-11-17 | 2012-06-20 | 上海先进半导体制造股份有限公司 | Composite integrated sensor structure and manufacture method thereof |
| CN102616727A (en) * | 2011-01-31 | 2012-08-01 | 中芯国际集成电路制造(上海)有限公司 | Micro electro mechanical system (MEMS) device and manufacture method of MEMS device |
-
2015
- 2015-06-24 CN CN201510353815.2A patent/CN104993804B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1749153A (en) * | 2005-09-16 | 2006-03-22 | 中国电子科技集团公司第二十四研究所 | Method for producing MEMS sensor suspension beam structure |
| CN102190284A (en) * | 2010-03-11 | 2011-09-21 | 苏州敏芯微电子技术有限公司 | MEMS sensor and methods for manufacturing MEMS sensor, film, mass block and cantilever beam |
| CN102616727A (en) * | 2011-01-31 | 2012-08-01 | 中芯国际集成电路制造(上海)有限公司 | Micro electro mechanical system (MEMS) device and manufacture method of MEMS device |
| CN102320560A (en) * | 2011-09-14 | 2012-01-18 | 上海先进半导体制造股份有限公司 | Production method of MEMS component film |
| CN102502479A (en) * | 2011-11-17 | 2012-06-20 | 上海先进半导体制造股份有限公司 | Composite integrated sensor structure and manufacture method thereof |
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