CN104991883A

CN104991883A - Sending and receiving apparatuses with chip interconnection and sending and receiving method and system

Info

Publication number: CN104991883A
Application number: CN201510305010.0A
Authority: CN
Inventors: 赵守磊; 于岗
Original assignee: Qingdao Hisense Xinxin Technology Co Ltd
Current assignee: Qingdao Hisense Electronics Co Ltd
Priority date: 2015-06-04
Filing date: 2015-06-04
Publication date: 2015-10-21
Also published as: WO2016192211A1

Abstract

An embodiment of the invention provides sending and receiving apparatuses with chips interconnection and sending and receiving methods and systems, which relate to the technical field of integrated circuits, wherein the sending apparatus comprises a serial data conversion circuit and at least a sending pin; an input end of the serial data conversion circuit is connected to a data sending processor; an output end of the serial data conversion circuit is connected to at least the sending pin; the serial data conversion circuit is used for obtaining n bit serial data from the data sending processor according to the vld/ rdy handshake protocol; the n bit serial data is converted into a m bit transmission data; then according to the vld/ rdy handshake protocol, the m bit transmission data is sent to the receiving apparatus with chips interconnection through m sending pins; n is an integer greater than 1; and m is an integer greater than 0 less than 1. The invention is suitable for the scene of data transmission.

Description

Sending and receiving device and sending and receiving method and system for inter-chip interconnection

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a transmitting and receiving device and a transmitting and receiving method and system for interconnection among chips.

Background

After the semiconductor industry enters the ultra-deep submicron and even nanometer processing era, a complex electronic system, such as a mobile phone chip, a digital television chip and the like, can be realized on a single integrated circuit chip. As technology advances, more functions are expected to be implemented on a single chip. SOC (System On Chip) technology IS generated in the general direction of Integrated Circuit (IC) to Integrated System (IS) conversion, and as semiconductor process technology develops, IC designers can integrate more and more complex functions into a single silicon Chip. Since the SOC can sufficiently utilize the existing design accumulation, the design capability and integration capability of a single CPU are significantly improved, and thus, the development is rapidly made.

The SOC usually uses an FPGA (Field-Programmable Gate Array) to customize a logic function module, so the function of the FPGA must be verified during the development of the SOC. However, as the SOC has a larger logic scale, it is difficult for a single FPGA to implement the function of the entire SOC, so that when the FPGA is verified, the function must be divided, and the function of the SOC is respectively verified in two or more FPGAs. In the prior art, when the SOC function is realized by interconnecting at least two FPGAs, signal transmission including to-be-processed data, and/or control data, and/or address data is generally performed by directly interconnecting the two FPGAs. When at least two FPGAs are directly interconnected, n-bit data needs to be transmitted through n pins. The n-bit data includes data to be processed, and/or control data, and/or address data.

For example, the SOC function is realized by interconnecting two FPGAs FPGA _1 and FPGA _2, and the FPGA _1 and the FPGA _2 are directly interconnected at the moment. If i-bit signals (Signal _1 to Signal _ i) need to be transmitted from FPGA _1 to FPGA _2, i-bit signals need to be transmitted through i pins, and the i-bit signals need to be received by FPGA _2 through i pins. At this time, i pins are required for both FPGA _1 and FPGA _2, as shown in fig. 1.

The prior art has at least the following problems: if the SOC function verification is performed by directly interconnecting at least two FPGAs, more pins are required to be occupied when the number of bits of the interactive signal is large, and at this time, the routing of the signal line connected between at least two FPGAs is also complicated, which increases the complexity of interconnection between FPGAs.

Disclosure of Invention

The embodiment of the invention provides a sending and receiving device, a sending and receiving method and a sending and receiving system for inter-chip interconnection, which are used for reducing pins used when the inter-chip interconnection is realized, reducing the complexity of routing of signal lines connected between at least two FPGAs and further reducing the complexity of the inter-chip interconnection.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

in a first aspect, an embodiment of the present invention provides an inter-chip interconnection sending apparatus, including: a parallel-serial data conversion circuit, at least one transmission pin; the output end of the parallel-serial data conversion circuit is connected with the at least one sending pin; the input end of the parallel-serial data conversion circuit is connected with the data sending processor; the parallel-serial data conversion circuit is used for acquiring n-bit parallel data from the data sending processor according to a vld/rdy handshake protocol, converting the n-bit parallel data into m-bit transmission data, and sending the m-bit transmission data to an inter-chip interconnected receiving device through m sending pins according to the vld/rdy handshake protocol; n is an integer greater than 1, and m is an integer greater than 0 and less than n.

In a second aspect, an embodiment of the present invention provides an inter-chip interconnection receiving apparatus, including: at least one receiving pin, a serial-to-parallel data conversion circuit; the input end of the serial-parallel data conversion circuit is connected with the at least one receiving pin, and the output end of the serial-parallel data conversion circuit is connected with the data processor; the serial-parallel data conversion circuit is used for acquiring m bits of transmission data sent by sending devices which are interconnected among chips through m receiving pins according to a vld/rdy handshake protocol, converting the m bits of transmission data into n bits of parallel data, and sending the n bits of parallel data to the data processor according to the vld/rdy handshake protocol; m is an integer greater than 0; and n is an integer greater than m.

In a third aspect, an embodiment of the present invention provides a method for sending inter-chip interconnection, including: the sending device interconnected among the chips acquires n-bit parallel data according to a vld/rdy handshake protocol; n is an integer greater than 1; converting the n-bit parallel data into m-bit transmission data; m is an integer which is more than 0 and less than n; and sending the m bits of transmission data to receiving devices interconnected among the chips through m sending pins according to the vld/rdy handshake protocol.

In a fourth aspect, an embodiment of the present invention provides a method for receiving interconnection between chips, including: the inter-chip interconnected receiving device acquires m bits of transmission data sent by the inter-chip interconnected sending device through m receiving pins according to a vld/rdy handshake protocol; m is an integer greater than 0; converting the m bits of transmission data into n bits of parallel data, and sending the n bits of parallel data to a data processor according to the vld/rdy handshake protocol, so that the data processor processes the n bits of parallel data; and n is an integer greater than m.

In a fifth aspect, an embodiment of the present invention provides an inter-chip interconnection system, including: a transmitting device for inter-chip interconnection, and a receiving device for inter-chip interconnection; wherein, the sending device of the inter-chip interconnection is the sending device of the inter-chip interconnection described in the above embodiment; the receiving device for inter-chip interconnection is the receiving device for inter-chip interconnection described in the above embodiment.

The embodiment of the invention provides a sending and receiving device and a sending and receiving method and a system for inter-chip interconnection, wherein the sending device for inter-chip interconnection comprises: a parallel-serial data conversion circuit, at least one transmission pin; the input end of the parallel-serial data conversion circuit is connected with the data sending processor, and the output end of the parallel-serial data conversion circuit is connected with at least one sending pin. And the parallel-serial data conversion circuit is used for acquiring n-bit parallel data from the data sending processor according to the vld/rdy handshake protocol, converting the n-bit parallel data into m-bit transmission data, and sending the m-bit transmission data to the inter-chip interconnected receiving devices through m sending pins according to the vld/rdy handshake protocol. Therefore, the sending device of the inter-chip interconnection can convert n-bit parallel data needing to be sent into m-bit transmission data through the parallel-serial data conversion circuit, and then can send the m-bit transmission data to the receiving device of the inter-chip interconnection by only using m sending pins. Compared with the prior art that a sending device for inter-chip interconnection needs n sending pins to send n-bit parallel data to a receiving device for inter-chip interconnection, the sending device for inter-chip interconnection can send data only through m sending pins, reduces the number of used pins when the inter-chip interconnection is realized, and further reduces the complexity of routing of signal lines connected between at least two FPGAs, thereby reducing the complexity of inter-chip interconnection.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of the structure of the interconnection between FPGAs in the prior art;

fig. 2 is a schematic structural diagram of an inter-chip interconnection transmitting apparatus according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another inter-chip interconnection transmission apparatus according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another inter-chip interconnection transmission apparatus according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another inter-chip interconnection transmission apparatus according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of an inter-chip interconnection receiving apparatus according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of another inter-chip interconnection receiving apparatus according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of another inter-chip interconnection receiving apparatus according to an embodiment of the present invention;

fig. 9 is a schematic flowchart of a method for sending inter-chip interconnection according to an embodiment of the present invention;

fig. 10 is a schematic flowchart of a method for receiving inter-chip interconnection according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of an inter-chip interconnection system according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

An embodiment of the present invention provides an inter-chip interconnection transmitting apparatus, as shown in fig. 2, including: a parallel-serial data conversion circuit 11, at least one transmission pin 12.

Wherein the output of the parallel-to-serial data conversion circuit 11 is connected to at least one transmit pin 12. An input terminal of the parallel-serial data conversion circuit 11 is connected to the data transmission processor.

And the parallel-serial data conversion circuit 11 is configured to obtain n-bit parallel data from the data sending processor according to the vld/rdy handshake protocol, convert the n-bit parallel data into m-bit transmission data, and send the m-bit transmission data to the inter-chip interconnected receiving devices through the m sending pins 12 according to the vld/rdy handshake protocol.

Wherein n is an integer greater than 1. m is an integer greater than 0 and less than n.

It should be noted that the parallel data in the embodiment of the present invention refers to data including data to be processed, and/or control data, and/or address data. The transmission data also refers to data including data to be processed, and/or control data, and/or address data.

Specifically, when the data sending processor needs to send data to other devices, n bits of parallel data can be generated according to actual requirements. The n-bit parallel data is transmitted to the transmitting means of the inter-chip interconnection. The parallel-to-serial data conversion circuit 11 in the inter-chip interconnected transmission apparatus may determine the bit number of the transmission data, that is, determine m, according to the number of transmission pins that can be used by the inter-chip interconnected transmission apparatus. The n-bit parallel data are divided into k groups, each group has m bits, thus each group of data is used as transmission data, the n-bit parallel data can be converted into m-bit transmission data, and the m-bit transmission data is sent to the receiving devices interconnected among the chips through m sending pins. Therefore, transmission data can be adjusted according to the available sending pin data, so that the adjusted transmission data is sent through the available sending pin, the flexibility of chip-to-chip interconnection is enhanced, and the complexity of chip-to-chip interconnection is reduced.

Wherein k is an integer greater than 0.

It should be noted that, if n-bit parallel data is divided into k groups and each group is m bits, if the n-bit parallel data is less than m bits when divided into the last group, the last group may be padded to m bits by zero padding through zero padding processing.

Further, in the transmitting apparatus for realizing the inter-chip interconnection, the elements are usually connected by an on-chip bus, that is, the data transmitting processor is connected to the parallel-serial data converting circuit 11 by the on-chip bus. In order to be compatible with protocols of on-chip buses, such as an AXI (advanced extensible Interface) protocol, an APB (advanced peripheral Bus) protocol, and the like, in the invention, different elements can transmit data according to a vld/rdy handshake protocol.

It should be noted that the vld (valid)/rdy (ready) handshake protocol is a protocol for transmitting respective current states of different elements to each other before the different elements transmit data. The vld/rdy handshake protocol is a protocol compatible with the on-chip bus protocol. In the vld/rdy handshake protocol, the current states of the vld _ s and rdy _ s signals are transmitted to each other and data is transmitted through the data channel.

The vld _ s signal is an identification signal indicating whether data sent by the sending end is valid data. For example, when the vld _ s signal is 1, it indicates that the data transmitted by the transmitting end is valid data. When the vld _ s signal is 0, it indicates that the data transmitted by the transmitting end is invalid data.

The rdy _ s signal is an identification signal of whether the receiving end can receive the transmitted data. For example, when the rdy _ s signal is 1, it indicates that the receiving end can receive the transmitted data. When the rdy _ s signal is 0, it indicates that the receiving end cannot receive the transmitted data.

And the data channel is used for transmitting data. That is, the data to be transmitted is transmitted to other components through this data channel.

The last _ s signal may also be passed in the vld/rdy handshake protocol. The last _ s signal is the last data indication identification signal of one transmission. Since one transmission can send a plurality of data, the last data is identified by the signal, the receiving device can be informed that the data carrying the last _ s signal is the last data, and the transmission of the data is completed. Thus, the internal states of the sending device and the receiving device can be synchronized by inter-chip interconnection, and the stability of transmission is provided.

It should be noted that this last _ s signal is an optional signal, and there may be no last _ s signal in the vld/rdy handshake protocol, so that the occupied transmit pins may be reduced.

It should be noted that, the transmission of the vld _ s signal, rdy _ s signal, and last _ s signal in the vld/rdy handshake protocol needs to be sent using a different transmission pin than the transmission data. Thus, if the transmitting devices interconnected between chips need to transmit transmission data using the m-bit transmit pins, three additional transmit pins are required to transmit the vld _ s signal, the rdy _ s signal, and the last _ s signal.

At this time, the parallel-serial data conversion circuit is used for acquiring n-bit parallel data from the data transmission processor according to the vld/rdy handshake protocol. That is, before receiving the n-bit parallel data sent by the data sending processor, the parallel-to-serial data converting circuit 11 first receives a vld _ s signal that indicates that the data sent by the sending end is valid data and is sent by the data sending processor to the parallel-to-serial data converting circuit 11, and at this time, after receiving the vld _ s signal, the parallel-to-serial data converting circuit 11 can know that the data sent by the data sending processor is valid data according to the vld _ s signal. At this time, if the parallel-serial data conversion circuit 11 can receive the valid data transmitted by the data transmission processor, the parallel-serial data conversion circuit 11 transmits a rdy _ s signal indicating that the reception end can receive the transmitted data to the data transmission processor. After the data sending processor receives the rdy _ s signal sent by the parallel-to-serial data conversion circuit 11, it can know that the parallel-to-serial data conversion circuit 11 can receive the transmitted data according to the rdy _ s signal, and at this time, the data sending processor can send the n-bit parallel data to the parallel-to-serial data conversion circuit 11 through the data channel. After the parallel-serial data conversion circuit 11 receives the n-bit parallel data, the rdy _ s signal indicating that the receiving end can receive the transmitted data, which is transmitted to the data transmission processor, is changed to the rdy _ s signal indicating that the receiving end cannot receive the transmitted data, and is transmitted to the data transmission processor. At this time, the data transmission processor recognizes from the received rdy _ s signal that the parallel-to-serial data conversion circuit 11 cannot receive the parallel data, and at this time, the data transmission processor no longer transmits data to the parallel-to-serial data conversion circuit 11. After the parallel-serial data conversion circuit 11 receives n-bit parallel data as transmission data, the n-bit parallel data may be divided into k groups of m bits each.

The parallel-serial data conversion circuit 11 transmits the m-bit transmission data to the receiving devices interconnected between chips through m transmitting pins 12 according to the vld/rdy handshake protocol. That is, before the parallel-serial data conversion circuit 11 sends the m bits of transmission data to the inter-chip interconnected receiving devices through the m sending pins, a vld _ s signal indicating that the data sent by the sending end is valid data to the inter-chip interconnected receiving devices through one sending pin is sent first, and at this time, after the inter-chip interconnected receiving devices receive the vld _ s signal, the data sent to the inter-chip interconnected receiving devices by the parallel-serial data conversion circuit 11 can be known as valid data according to the vld _ s signal. At this time, if the receiving device to the inter-chip interconnection can receive the valid data transmitted from the parallel-serial data conversion circuit 11, the parallel-serial data conversion circuit 11 transmits a rdy _ s signal indicating that the receiving end can receive the transmitted data. When rdy to the inter-chip interconnected receiving device indicates that it can receive the transmitted data, the parallel-serial data conversion circuit 11 transmits a set of transmission data to the inter-chip interconnected receiving device until k sets of transmission data are all transmitted to the inter-chip interconnected receiving device.

Further, the parallel-serial data converting circuit 11 may generate a last signal when transmitting the last group of transmission data, so as to characterize the data as the last transmission data, and transmit the last group of transmission data together to the receiving device of the inter-chip interconnection. At this time, m sending pins are needed to send m bits of transmission data, and another sending pin is needed to send a last signal.

After the parallel-serial data conversion circuit 11 sends the k sets of transmission data to the inter-chip interconnected receiving devices through the m sending pins, the rdy _ s signal which indicates that the receiving end cannot receive the transmitted data and is sent to the data sending processor can be changed into the rdy _ s signal which indicates that the receiving end can receive the transmitted data, and the rdy _ s signal is sent to the data sending processor.

Illustratively, when the vld _ s signal is a high signal indicating that the data sent by the sending end is valid data, the vld _ s signal received by the parallel-to-serial data conversion circuit 11 is a high signal. When the rdy _ s signal is high indicating that the receiver can receive the transmitted data, then the rdy _ s signal received by the data transmit processor is high.

It should be noted that the vld _ s signal may also indicate that the data sent by the sending end is valid data through other signals, for example, a low level signal, which is not limited in the present invention. Similarly, the rdy _ s signal may also indicate that the receiving end can receive the transmitted data through other signals, such as a low signal, which is not limited by the invention.

It should be noted that the vld _ s signal indicating that the data sent by the sending end is valid data may be the same signal as the rdy _ s signal indicating that the receiving end can receive the transmitted data, or may be different signals, for example, the vld _ s signal indicates that the data sent by the sending end is valid data through a low level signal, and the rdy _ s signal indicates that the receiving end can receive the transmitted data through a high level signal. The invention is not limited in this regard.

It should be noted that, when the data sending processor sends the vld _ s signal indicating that the data sent by the sending end is invalid data to the parallel-serial data converting circuit 11, at this time, the parallel-serial data converting circuit 11 can know that the data to be sent by the data sending processor is invalid data according to the received vld _ s signal, so the parallel-serial data converting circuit 11 does not process the data sent by the data sending processor.

If the parallel-serial data conversion circuit 11 transmits the rdy _ s signal indicating that the reception end cannot receive the transmitted data to the data transmission processor, the data transmission processor can know from the received rdy _ s signal that the parallel-serial data conversion circuit 11 cannot receive the transmitted data at this time, so the data transmission processor no longer transmits the parallel data to the parallel-serial data conversion circuit 11.

Note that n is predetermined in the n-bit parallel data. Which is related to the on-chip bus used.

For example, the on-chip bus is AXI, and the width n of the parallel data may be determined as the sum of the width of the control data, the width of the address data, and the width of the data to be processed, assuming 128 bits, that is, n is 128. Next, the width of the transmission data may be determined according to the number of transmission pins that can be used by the inter-chip interconnected transmission device and the number of reception pins that can be used by the inter-chip interconnected reception device. If only 6 pins of the sending device and 8 pins of the receiving device are available, 2 pins of the sending device and the receiving device may be respectively used as a sending pin for sending the vld _ s signal, a receiving pin for receiving the rdy _ s signal, and the other 4 pins may be used as sending pins for sending transmission data, where m is 4. Thus, the transmitting device of the inter-chip interconnection can use the 128 to 4 parallel-serial data conversion circuit 11 to convert the 128-bit parallel data into 4-bit transmission data through the parallel-serial data conversion circuit 11, and transmit the transmission data to the receiving device of the inter-chip interconnection through 4 transmission pins. The receiving device connected to the inter-chip may use one pin as a receiving pin for receiving the vld _ s signal, and receive the vld _ s signal transmitted by the transmitting device connected to the inter-chip through the receiving pin. The other pin is used as a transmit pin for transmitting rdy _ s signals, and the rdy _ s signals are transmitted to the transmitting devices interconnected between chips through the transmit pin. Of the remaining 6 pins, 4 pins are selected as reception pins for receiving transmission data.

Further, as shown in fig. 3, the sending apparatus for inter-chip interconnection further includes: an asynchronous FIFO (First Input First output) processor 13.

The input terminal of the parallel-serial data conversion circuit 11 is connected to the data transmission processor, and includes: an input terminal of the asynchronous FIFO processor 13 is connected to the data transmission processor, and an output terminal of the asynchronous FIFO processor 13 is connected to an input terminal of the parallel-serial data conversion circuit 11.

At this time, the asynchronous FIFO processor 13 is used to acquire and store n bits of parallel data from the data transmission processor.

And the parallel-serial data conversion circuit 11 is specifically used for acquiring n bits of parallel data from the asynchronous FIFO processor 13 according to the vld/rdy handshake protocol.

Specifically, the asynchronous FIFO processor 13 is provided between the data transmission processor and the parallel-serial data conversion 12, and the data transmission processor can transmit the n-bit parallel data generated by the data transmission processor to the asynchronous FIFO processor 13 for storage by the asynchronous FIFO processor 13. And, the parallel-serial data conversion 12 acquires n-bit parallel data to be converted from the asynchronous FIFO processor 13. In this way, by the asynchronous FIFO processor 13 spacing the data transmission processor from the parallel-to-serial data conversion circuit 12, the operating clock frequencies of the data transmission processor and the parallel-to-serial data conversion circuit 11 can be different. That is, the data transmission rates of the data sending processor and the parallel-serial data conversion circuit 11 may be different, so that the data transmission rates of the parallel-serial data conversion circuit 11 and the subsequent processor thereof can be increased, and the data transmission efficiency is further increased; meanwhile, the data sending processor and the running clock frequency of the parallel-serial data conversion circuit 11 are asynchronous, the running clock frequency of the parallel-serial data conversion circuit 11 can be dynamically adjusted according to the frequency actually supported by the sending pin, and the flexibility and the reliability are improved.

Further, the parallel-serial data conversion circuit 11 acquires n bits of parallel data according to the vld/rdy handshake protocol means that the parallel-serial data conversion circuit 11 acquires n bits of parallel data from the asynchronous FIFO processor 13 according to the vld/rdy handshake protocol. That is to say, before the asynchronous FIFO processor 13 sends n bits of parallel data to the parallel-to-serial data conversion circuit 11, it sends a vld _ s signal indicating that the data sent by the sending end is valid data to the parallel-to-serial data conversion circuit 11, and at this time, after the parallel-to-serial data conversion circuit 11 receives the vld _ s signal, it can know that the data sent to it by the asynchronous FIFO processor 13 is valid data according to the vld _ s signal. At this time, if the parallel-serial data conversion circuit 11 can receive the valid data transmitted from the asynchronous FIFO processor 13, the parallel-serial data conversion circuit 11 transmits a rdy _ s signal indicating that the receiving side can receive the transmitted data to the asynchronous FIFO processor 13. After the asynchronous FIFO processor 13 receives the rdy _ s signal sent by the parallel-serial data conversion circuit 11, it can be known that the parallel-serial data conversion circuit 11 can receive the transmitted data according to the rdy _ s signal, at this time, the asynchronous FIFO processor 13 can send the n-bit parallel data to the parallel-serial data conversion circuit 11 through the data channel, so that the parallel-serial data conversion circuit 11 obtains the n-bit parallel data to be converted from the asynchronous FIFO processor 13.

Further, when the asynchronous FIFO processor 13 obtains n bits of parallel data from the data sending processor, it can also obtain the data according to the vld/rdy handshake protocol. Before the data sending processor sends n-bit parallel data to the asynchronous FIFO processor 13, a vld _ s signal indicating that the data sent by the sending end is valid data is sent to the asynchronous FIFO processor 13, and at this time, after the asynchronous FIFO processor 13 receives the vld _ s signal, it can know that the data sent by the data sending processor to the asynchronous FIFO processor is valid data according to the vld _ s signal. At this time, if the asynchronous FIFO processor 13 can receive valid data transmitted by the data transmission processor, the asynchronous FIFO processor 13 transmits a rdy _ s signal indicating that the reception side can receive the transmitted data to the data transmission processor. After the data transmission processor receives the rdy _ s signal transmitted from the asynchronous FIFO processor 13, n-bit parallel data is transmitted to the asynchronous FIFO processor 13 through the data channel.

It should be noted that the data sending processor in the embodiment of the present invention may be a processor integrated in the sending apparatus interconnected between chips, or may be a processor independent from the sending apparatus interconnected between chips, which is not limited in the present invention.

Further, the sending transpose of the inter-slice interconnection, as shown in fig. 4, further includes: a synchronous FIFO processor 14.

The connection of the output terminal of the parallel-serial data conversion circuit 11 to at least one transmission pin 12 includes:

an input terminal of the synchronous FIFO processor 14 is connected to an output terminal of the parallel-to-serial data conversion circuit 11, and an output terminal of the synchronous FIFO processor 14 is connected to at least one of the transmission pins 12.

And the parallel-serial data conversion circuit 11 is specifically configured to send the m bits of transmission data to the synchronous FIFO processor 14 according to the vld/rdy handshake protocol.

And the synchronous FIFO processor 14 is used for receiving and storing the m bits of transmission data and sending the m bits of transmission data to the receiving devices interconnected among the slices through the m sending pins 12 according to the vld/rdy handshake protocol.

Specifically, the synchronous FIFO processor 14 is disposed between the parallel-serial data conversion circuit 11 and the transmission pin 12, and the parallel-serial data conversion circuit 11 may transmit the converted m bits of transmission data to the synchronous FIFO processor 14 for storage by the synchronous FIFO processor 14. And when the transmission data can be transmitted through the transmission pins 12, the synchronous FIFO processor 14 transmits the m-bit transmission data stored therein to the receiving devices of the inter-chip interconnection through the m transmission pins 12. In this way, by spacing the parallel-to-serial data conversion circuit 11 from the transmission pin 12 by the synchronization FIFO processor 14, the data transfer rate can be improved.

The synchronous FIFO processor 14 sends the m bits of transmission data to the inter-chip interconnected receiving devices through the m sending pins 12 according to the vld/rdy handshake protocol, that is, before the synchronous FIFO processor 14 sends the m bits of transmission data to the inter-chip interconnected receiving devices, a vld _ s signal indicating that the data sent by the sending end is valid data is sent to the inter-chip interconnected receiving devices, and after receiving the vld _ s signal, the inter-chip interconnected receiving devices can know that the data sent to the synchronous FIFO processor 14 is valid data according to the vld _ s signal. At this time, if the receiving device of the inter-slice interconnect can receive valid data sent by the synchronization FIFO processor 14, the receiving device of the inter-slice interconnect sends a rdy _ s signal to the synchronization FIFO processor 14 indicating that the receiving end can receive the transmitted data. After the rdy _ s signal sent by the receiving device of the chip interconnection is received by the synchronous FIFO processor 14, it can be known that the receiving device of the chip interconnection can receive the transmitted data according to the rdy _ s signal, and at this time, the synchronous FIFO processor 14 can send the m bits of transmitted data to the receiving device of the chip interconnection through the m sending pins 12.

Further, without the synchronization FIFO 14, the rdy _ s signal used by the receiver devices of the chip interconnection is directly transmitted to the parallel-to-serial data conversion circuit 11. Therefore, the delay time of the rdy _ s signal from the receiving device interconnected among the chips to the parallel-serial data conversion circuit 11 is longer, the operation clock frequency is lower, namely the rdy _ s signal in one period can reach the parallel-serial data conversion circuit 11 only when the operation clock period is longer, and the data transmission rate is lower. With the addition of the synchronous FIFO processor 14, the delay time for the rdy _ s signal to be transmitted directly from the receiving device of the chip interconnection to the synchronous FIFO processor 14 is reduced relative to the delay time for the rdy _ s signal to be transmitted from the receiving device of the chip interconnection to the parallel-serial data conversion circuit 11; meanwhile, the synchronous FIFO processor 14 may regenerate the rdy _ s signal to the parallel-to-serial data conversion circuit 11, and the delay time from the synchronous FIFO processor 14 to the parallel-to-serial data conversion circuit 11 is also reduced with respect to the delay time of the rdy _ s signal from the inter-chip interconnected receiving device to the parallel-to-serial data conversion circuit 11, so that the operation clock frequency at this time is increased with respect to the operation clock frequency of the rdy _ s signal from the inter-chip interconnected receiving device to the parallel-to-serial data conversion circuit 11, i.e., the operation clock period is reduced, thereby increasing the data transmission rate through the synchronous FIFO processor 14.

Further, when the parallel-serial data conversion circuit 11 sends the m bits of transmission data converted by the parallel-serial data conversion circuit to the synchronous FIFO processor 14, a vld _ s signal indicating that the data sent by the sending end is valid data is sent to the synchronous FIFO processor 14 first according to a vld/rdy handshake protocol, that is, before the parallel-serial data conversion circuit 11 sends the m bits of transmission data to the synchronous FIFO processor 14, at this time, after the synchronous FIFO processor 14 receives the vld _ s signal, it can know that the data sent by the parallel-serial data conversion circuit 11 is valid data according to the vld _ s signal. At this time, if the synchronous FIFO processor 14 can receive the valid data transmitted from the parallel-to-serial data conversion circuit 11, the synchronous FIFO processor 14 transmits a rdy _ s signal indicating that the receiving end can receive the transmitted data to the parallel-to-serial data conversion circuit 11. After the parallel-serial data conversion circuit 11 receives the rdy _ s signal sent by the synchronous FIFO processor 14, it can know that the synchronous FIFO processor 14 can receive the transmitted data according to the rdy _ s signal, and at this time, the parallel-serial data conversion circuit 11 can send the m bits of transmission data to the synchronous FIFO processor 14 through the data channel.

Further, as shown in fig. 5, the sending apparatus for inter-chip interconnection further includes: IOP (I/O Processor) 15.

Wherein, the connection of the output end of the synchronous FIFO processor 14 with the at least one transmission pin 12 comprises: the output of the isochronous FIFO processor 14 is connected to an input of IOP15, and the output of IOP15 is connected to at least one transmit pin 12.

The synchronous FIFO processor 14 is specifically configured to send m bits of transmission data to the IOP15 according to the vld/rdy handshake protocol.

The IOP15 is configured to receive the m bits of transmission data and send the m bits of transmission data to the receiving devices interconnected between chips by using the m sending pins 12.

Specifically, the IOP15 is disposed between the isochronous FIFO processor 14 and at least one of the transmit pins 12 such that the IOP15 can fetch m bits of transfer data from the isochronous FIFO processor 14 and transmit the transfer data to an inter-chip interconnect receiving device through the m transmit pins 12 when the inter-chip interconnect receiving device can receive the transfer data. When the synchronous FIFO processor 14 sends the m-bit transmission data to the m sending pins 12, since the synchronous FIFO processor 14 needs to perform relevant logic processing in its interior and then transmit the m-bit transmission data to the m sending pins 12, the delay time for the synchronous FIFO processor 14 to send the m-bit transmission data to the m sending pins 12 is long, the operating clock frequency is small, that is, the operating clock period is long, it can be ensured that the m-bit transmission data is transmitted to the m sending pins 12 in one period, and thus the data transmission rate is low. With the IOP15 disposed between the isochronous FIFO processor 14 and the at least one transmit pin 12, the latency time that the isochronous FIFO processor 14 may transmit m bits of transfer data first to the IOP15 is reduced relative to the latency time that the isochronous FIFO processor 14 transmits m bits of transfer data to the m transmit pins 12. Meanwhile, the delay time for transmitting the m-bit transmission data to the m sending pins 12 by the IOP15 is also reduced relative to the delay time for transmitting the m-bit transmission data to the m sending pins 12 by the synchronous FIFO processor 14, so that the operating clock frequency at this time is increased relative to the operating clock frequency for transmitting the m-bit transmission data to the m sending pins 12 by the synchronous FIFO processor 14, that is, the operating clock period is reduced, and thus the data transmission rate is improved by the synchronous IOP 15.

When the FIFO 14 sends the m-bit transmission data converted by the FIFO 14 to the IOP15, a vld/rdy handshake protocol is required, that is, before the FIFO 14 sends the m-bit transmission data to the IOP15, a vld _ s signal indicating that the data sent by the sending end is valid data is sent to the IOP15, and at this time, after the IOP15 receives the vld _ s signal, it can know that the data sent by the FIFO 14 is valid data according to the vld _ s signal. At this time, if the IOP15 can receive valid data sent by the Sync FIFO processor 14, the IOP15 sends the Sync FIFO processor 14 a rdy _ s signal indicating that the receiving end can receive the transferred data. After the synchronization FIFO processor 14 receives the rdy _ s signal sent by IOP15, it is known from this rdy _ s signal that IOP15 can receive the transferred data, at which point the synchronization FIFO processor 14 can send the m bits of transferred data to IOP15 over the data channel.

When the IOP15 sends the converted m-bit transmission data to the inter-chip interconnected receiving devices through the m sending pins 12, the vld/rdy handshake protocol is also used, that is, before the IOP15 sends the m-bit transmission data to the inter-chip interconnected receiving devices, a vld _ s signal indicating that the data sent by the sending end is valid data is sent to the inter-chip interconnected receiving devices, and after the inter-chip interconnected receiving devices receive the vld _ s signal, the data sent by the IOP15 to the inter-chip interconnected receiving devices can be known to be valid data according to the vld _ s signal. At this time, if the inter-chip interconnect receiving device can receive valid data transmitted from the IOP15, the inter-chip interconnect receiving device transmits a rdy _ s signal to the IOP15 indicating that the sink can receive the transmitted data. After the IOP15 receives the rdy _ s signal sent by the receiving device of the inter-chip interconnection, it can be known that the receiving device of the inter-chip interconnection can receive the transmitted data according to the rdy _ s signal, at this time, the IOP15 can send the m bits of transmitted data to the receiving device of the inter-chip interconnection through the m sending pins 12.

It should be noted that, if the receiving device of the inter-chip interconnection must transmit the rdy _ s signal to the transmitting device of the inter-chip interconnection when the vld _ s signal transmitted by the transmitting device of the inter-chip interconnection is a signal indicating that the data transmitted by the transmitting device of the inter-chip interconnection is valid data, and the inter-chip interconnect transmitting device must receive the rdy _ s signal transmitted by the inter-chip interconnect receiving device as a signal indicating that the receiving end can receive the transmitted data, can to the inter-slice interconnect receiving device, the inter-slice interconnect receiving device waits for the vld _ s signal of the inter-slice interconnect transmitting device indicating that the data transmitted by the transmitting end is valid data, while the sending device of the inter-chip interconnection waits for the rdy _ s signal of the receiving device of the inter-chip interconnection indicating that the receiving end can receive the transmitted data, which causes the transmission data to be never sent, and thus deadlock occurs.

To avoid deadlock between the sending device and the receiving device of the inter-chip interconnect, when the IOP15 receives that the rdy _ s signal sent to the receiving device of the inter-chip interconnect is data indicating that it cannot receive a transmission, the IOP15 still sends the vld _ s signal indicating that the data sent by the sending end is valid data and m bits of transmission data. And at this point the m bits of transfer data sent by the IOP15 are unchanged until the IOP15 receives the rdy _ s signal sent by the inter-chip interconnect receiving device as indicating that it can receive the transferred data.

It should be noted that inter-chip interconnection refers to interconnection between chips or interconnection between FPGAs.

The embodiment of the invention provides a sending device for inter-chip interconnection, which comprises: a parallel-serial data conversion circuit, at least one transmission pin; the output end of the parallel-serial data conversion circuit is connected with at least one sending pin. And the parallel-serial data conversion circuit is used for acquiring n-bit parallel data according to the vld/rdy handshake protocol, converting the n-bit parallel data into m-bit transmission data, and sending the m-bit transmission data to the inter-chip interconnected receiving devices through m sending pins according to the vld/rdy handshake protocol. Therefore, the sending device of the inter-chip interconnection can convert n-bit parallel data needing to be sent into m-bit transmission data through the parallel-serial data conversion circuit, and then can send the m-bit transmission data to the receiving device of the inter-chip interconnection by only using m sending pins. Compared with the prior art that a sending device for inter-chip interconnection needs n sending pins to send n-bit parallel data to a receiving device for inter-chip interconnection, the sending device for inter-chip interconnection can send data only through m sending pins, reduces the number of used pins when the inter-chip interconnection is realized, and further reduces the complexity of routing of signal lines connected between at least two FPGAs, thereby reducing the complexity of inter-chip interconnection. And the sending device of the inter-chip interconnection can obtain n-bit parallel data according to the vld/rdy handshake protocol, and after the n-bit parallel data is converted into m-bit transmission data, the m-bit transmission data is sent to the receiving device of the inter-chip interconnection through m sending pins according to the vld/rdy handshake protocol, so that the sending device of the inter-chip interconnection can be compatible with the total number protocol on the chip, and the compatibility of the sending device of the inter-chip interconnection is improved.

An embodiment of the present invention provides an inter-chip interconnection receiving apparatus, as shown in fig. 6, including: at least one receiving pin 21, a serial-to-parallel data conversion circuit 22. The serial-to-parallel data conversion circuit 22 has an input connected to at least one of the receiving pins 21 and an output connected to the data processor.

And the serial-parallel data conversion circuit 22 is used for acquiring m bits of transmission data sent by sending devices interconnected among chips through m receiving pins 21 according to a vld/rdy handshake protocol, converting the m bits of transmission data into n bits of parallel data, and sending the n bits of parallel data to the data processor according to the vld/rdy handshake protocol.

Wherein m is an integer greater than 0. n is an integer greater than m.

Specifically, after the inter-chip interconnected transmitting device transmits m bits of transmission data to the inter-chip interconnected receiving device, if the parallel-serial data conversion circuit 22 of the inter-chip interconnected receiving device can receive the m bits of transmission data through the m receiving pins 21 connected to the inter-chip interconnected transmitting device. After receiving the m-bit transmission data, the parallel-serial data conversion circuit 22 temporarily stores the m-bit transmission data until receiving the n-bit data, thereby realizing conversion of the m-bit transmission data into n-bit parallel data. After being converted into n-bit parallel data, the n-bit parallel data can be sent to a data processor, so that the data processor performs corresponding processing on the n-bit parallel data.

It should be noted that, the data processor in the embodiment of the present invention may be one processor in the inter-chip interconnection receiving apparatus, and may be a processor independent from the inter-chip interconnection receiving apparatus, which is not limited in this respect.

The n-bit parallel data includes not only data to be processed that needs to be used, but also control data, address data, and the like related to the data to be processed.

It should be noted that, in the embodiment of the present invention, n of the n-bit parallel data is predetermined. Which is related to the on-chip bus used.

Further, in the receiving apparatus for implementing interconnection between chips, the components are usually connected by an on-chip bus, that is, the receiving pin 21 is connected to the parallel-serial data conversion circuit 22 by the on-chip bus. In order to be compatible with the on-chip Bus protocol, such as AXI (Advanced extensible Bus) protocol, APB (Advanced Peripheral Bus) protocol, etc., in the present invention, different elements may transmit data according to the vld/rdy handshake protocol.

Specifically, the serial-to-parallel data conversion circuit 22 is configured to obtain m bits of transmission data sent by the sending apparatus interconnected between chips through m receiving pins 21 according to a vld/rdy handshake protocol, that is, before sending the m bits of transmission data to the receiving apparatus interconnected between chips, the sending apparatus interconnected between chips sends a vld _ s signal indicating that data sent by the sending end is valid data to the receiving apparatus interconnected between chips, and at this time, the serial-to-parallel data conversion circuit 22 may receive the vld _ s signal through the receiving pins 21, and can obtain that the data sent to the sending apparatus interconnected between chips is valid data according to the vld _ s signal. At this time, if the serial-to-parallel data conversion circuit 22 can receive valid data transmitted by the inter-chip interconnected transmitting device, the serial-to-parallel data conversion circuit 22 indicates to the inter-chip interconnected transmitting device the rdy _ s signal that the receiving end can receive the transmitted data. In this way, the serial-to-parallel data conversion circuit 22 can receive the m bits of transmission data transmitted by the inter-chip interconnected transmission apparatus through the m reception pins 21.

The serial-parallel data conversion circuit 22 sends the n-bit parallel data to the data processor according to the vld/rdy handshake protocol, that is, after the serial-parallel data conversion circuit 22 converts the m-bit transmission data into the n-bit parallel data, before sending the n-bit parallel data to the data processor, a vld _ s signal indicating that the data sent by the sending end is valid data is sent to the data processor, and at this time, after receiving the vld _ s signal, the data processor can know that the data sent by the serial-parallel data conversion circuit 22 is valid data according to the vld _ s signal. At this time, if the data processor can receive valid data transmitted from the serial-to-parallel data conversion circuit 22, the data processor transmits a rdy _ s signal indicating that the reception end can receive the transmitted data to the serial-to-parallel data conversion circuit 22. After the serial-parallel data conversion circuit 22 receives the rdy _ s signal sent by the data processor, it can know that the data processor can receive the transmitted data according to the rdy _ s signal, and at this time, the serial-parallel data conversion circuit 22 can send the n-bit parallel data to the data processor through the data channel.

It should be noted that, when the serial-parallel data conversion circuit 22 sends the vld _ s signal indicating that the data sent by the sending end is invalid data to the data processor, at this time, the data processor can know that the data to be sent by the serial-parallel data conversion circuit 22 is invalid data according to the received vld _ s signal, so the data processor does not process the data sent by the serial-parallel data conversion circuit 22.

If the rdy _ s signal received by the serial-parallel data conversion circuit 22 and sent by the data processor is the rdy _ s signal indicating that the receiving end cannot receive the transmitted data, the serial-parallel data conversion circuit 22 can know that the data processor cannot receive the transmitted data according to the received rdy _ s signal, so the serial-parallel data conversion circuit 22 does not send parallel data to the data processor any more.

Further, as shown in fig. 7, the receiving device for interconnection between sheets further includes: an asynchronous FIFO processor 23.

The output terminal of the serial-to-parallel data conversion circuit 22 is connected to the data processor, and comprises: an output terminal of the serial-to-parallel data conversion circuit 22 is connected to an input terminal of the asynchronous FIFO processor 23. An output of the asynchronous FIFO processor 23 is connected to the data processor.

And the serial-parallel data conversion circuit 22 is specifically used for sending the n-bit parallel data to the asynchronous FIFO processor 23 according to the vld/rdy handshake protocol.

The asynchronous FIFO processor 23 is further configured to receive and store n bits of parallel data, and send the n bits of parallel data to the data processor according to the vld/rdy handshake protocol.

Specifically, the asynchronous FIFO processor 23 is disposed between the serial-parallel data conversion circuit 22 and the data processor, the serial-parallel data conversion circuit 22 sends the n-bit parallel data converted by the serial-parallel data conversion circuit to the asynchronous FIFO processor 23, the asynchronous FIFO processor 23 stores the n-bit parallel data, and the data processor can obtain the n-bit parallel data from the asynchronous FIFO processor 23, so that when the data processor cannot receive the n-bit parallel data, the serial-parallel data conversion circuit 22 can cache the n-bit parallel data converted by the serial-parallel data conversion circuit into the asynchronous FIFO processor 23, and further, normal data transmission by a transmitting device interconnected between chips can be ensured. Also, by spacing the serial-to-parallel data conversion circuit 22 from the data processor by the asynchronous FIFO processor 23, the operating clock frequencies of the serial-to-parallel data conversion circuit 22 and the data processor may be different. That is, the data transmission rates of the serial-parallel data conversion circuit 22 and the data processor may be different, so that the data transmission rate of the serial-parallel data conversion circuit 22 may be increased, and the data transmission efficiency may be further increased.

When the serial-parallel data conversion circuit 22 sends the n bits of parallel data converted by the serial-parallel data conversion circuit to the asynchronous FIFO processor 23, a vld _ s signal indicating that the data sent by the sending end is valid data is sent to the asynchronous FIFO processor 23 according to a vld/rdy handshake protocol, that is, before the serial-parallel data conversion circuit 22 sends the n bits of parallel data to the asynchronous FIFO processor 23, at this time, after the asynchronous FIFO processor 23 receives the vld _ s signal, the data sent by the serial-parallel data conversion circuit 22 to the asynchronous FIFO processor 23 can be known as valid data according to the vld _ s signal. At this time, if the asynchronous FIFO processor 23 can receive the valid data sent from the serial-to-parallel data conversion circuit 22, the asynchronous FIFO processor 23 sends a rdy _ s signal indicating that the receiving end can receive the transmitted data to the serial-to-parallel data conversion circuit 22. After the serial-parallel data conversion circuit 22 receives the rdy _ s signal sent by the asynchronous FIFO processor 23, it can know that the asynchronous FIFO processor 23 can receive the transmitted data according to the rdy _ s signal, and at this time, the serial-parallel data conversion circuit 22 can send the n-bit parallel data to the asynchronous FIFO processor 23 through the data channel.

When the asynchronous FIFO processor 23 sends the n-bit parallel data to the data processor, it may also send, according to a vld/rdy handshake protocol, that is, before the asynchronous FIFO processor 23 sends the n-bit parallel data to the data processor, a vld _ s signal indicating that the data sent by the sending end is valid data to the data processor, and at this time, after receiving the vld _ s signal, the data processor may know that the data sent by the asynchronous FIFO processor 23 to the data processor is valid data according to the vld _ s signal. At this time, if the data processor can receive valid data sent by the asynchronous FIFO processor 23, the data processor sends a rdy _ s signal to the asynchronous FIFO processor 23 indicating that the receiving end can receive the transferred data. After the rdy _ s signal sent by the data processor is received by the asynchronous FIFO processor 23, it can be known that the data processor can receive the transmitted data according to the rdy _ s signal, at this time, the asynchronous FIFO processor 23 can send the n-bit parallel data to the data processor through the data channel, so that the data processor can obtain the n-bit parallel data to be converted from the asynchronous FIFO processor 13.

Further, as shown in fig. 8, the receiving device for interconnection between sheets further includes: a synchronization FIFO processor 24.

The input terminal of the serial-to-parallel data conversion circuit 22 is connected to at least one receiving pin 21, and includes:

an input of the serial-to-parallel data conversion circuit 22 is connected to an output of the synchronization FIFO processor 24, and an input of the synchronization FIFO processor 24 is connected to the at least one reception pin 21.

And the synchronous FIFO processor 24 is used for receiving the m bits of transmission data sent by the sending devices interconnected among the chips through the m receiving pins 21 according to the vld/rdy handshake protocol and storing the m bits of transmission data.

The serial-to-parallel data conversion circuit 21 is specifically configured to obtain m bits of transmission data sent by the sending device interconnected between the slices from the synchronous FIFO processor 24 according to the vld/rdy handshake protocol.

Specifically, the synchronous FIFO processor 24 is disposed between the serial-to-parallel data conversion circuit 22 and the receiving pins 21, after the sending device of the inter-chip interconnection sends the m bits of transmission data to the receiving device of the inter-chip interconnection, the m receiving pins 21 of the receiving device of the inter-chip interconnection transmit the received data to the synchronous FIFO processor 24, and the synchronous FIFO processor 24 stores the received m bits of transmission data. The serial-to-parallel data conversion circuit 22 can acquire and convert the m bits of transmission data in the synchronization FIFO processor 24. In this way, when the serial-to-parallel data conversion circuit 22 is temporarily unable to convert data, the synchronization FIFO processor 24 can buffer the transmission data transmitted by the inter-chip interconnected transmission device first, thereby ensuring normal transmission by the inter-chip interconnected transmission device.

Before transmitting m bits of transmission data to the inter-chip interconnected receiving devices, the inter-chip interconnected transmitting devices transmit vld _ s signals indicating that the data transmitted by the transmitting end is valid data to the inter-chip interconnected receiving devices, and at this time, the synchronous FIFO processor 24 may receive the vld _ s signals through the receiving pin 21, and may know that the data transmitted by the inter-chip interconnected transmitting devices is valid data according to the vld _ s signals. At this point, if the synchronization FIFO processor 24 can receive valid data sent by the sending device of the inter-slice interconnect, the synchronization FIFO processor 24 indicates to the sending device of the inter-slice interconnect the rdy _ s signal that the receiving end can receive the transmitted data. Thus, the synchronization FIFO processor 24 can receive m bits of transmission data transmitted from the transmitting device of the inter-chip interconnection through the m reception pins 21.

The serial-to-parallel data conversion circuit 22 obtains m bits of transmission data sent by the sending device interconnected between chips from the synchronous FIFO processor 24 according to the vld/rdy handshake protocol, that is: after acquiring the m bits of transmission data, the synchronous FIFO processor 24 may send a vld _ s signal indicating that the data sent by the sending end is valid data to the serial-to-parallel data conversion circuit 22, and at this time, after receiving the vld _ s signal, the serial-to-parallel data conversion circuit 22 may know that the data sent by the synchronous FIFO processor 24 is valid data according to the vld _ s signal. At this time, if the serial-to-parallel data conversion circuit 22 can receive valid data sent from the synchronization FIFO processor 24, the serial-to-parallel data conversion circuit 22 sends a rdy _ s signal to the synchronization FIFO processor 24 indicating that the receiving end can receive the transmitted data. After the rdy _ s signal is received by the synchronization FIFO processor 24, it can be known from the rdy _ s signal that the serial-to-parallel data conversion circuit 22 can receive the transmitted data, and at this time, the synchronization FIFO processor 24 can send the m-bit transmission data to the serial-to-parallel data conversion circuit 22 through the data channel.

The embodiment of the invention provides a receiving device for inter-chip interconnection, which comprises: at least one receiving pin and a serial-parallel data conversion circuit. The input end of the serial-parallel data conversion circuit is connected with at least one receiving pin, and the output end of the serial-parallel data conversion circuit is connected with the data processor. And the serial-parallel data conversion circuit is used for acquiring m-bit transmission data sent by sending devices interconnected among chips through m receiving pins according to a vld/rdy handshake protocol, converting the m-bit transmission data into n-bit parallel data and sending the n-bit parallel data to the data processor according to the vld/rdy handshake protocol. Thus, when the sending device of the inter-chip interconnection converts the n-bit parallel data into the m-bit transmission data and sends the m-bit transmission data to the receiving device of the inter-chip interconnection through the m sending pins, the receiving device can receive the m-bit transmission data through the m receiving pins. And reconverts it into n-bit parallel data. Compared with the prior art that a sending device for chip-to-chip interconnection needs n sending pins to send n-bit parallel data to a receiving device for chip-to-chip interconnection, the sending device can send data only through m sending pins and m receiving pins, reduces the number of used pins when chip-to-chip interconnection is realized, and further reduces the complexity of routing of signal lines connected between at least two FPGAs, thereby reducing the complexity of chip-to-chip interconnection.

An embodiment of the present invention provides a method for sending inter-chip interconnection, as shown in fig. 9, including:

101. and the sending device interconnected among the chips acquires n-bit parallel data according to the vld/rdy handshake protocol.

Wherein n is an integer greater than 1.

Specifically, the sending device of the inter-slice interconnection may obtain n bits of parallel data to be sent to the receiving device of the inter-slice interconnection from the data sending processor.

Further, after acquiring the n-bit parallel data to be transmitted to the inter-chip interconnected receiving device, the inter-chip interconnected transmitting device may cache the n-bit parallel data first.

102. The parallel data of n bits is converted into transmission data of m bits.

Wherein m is an integer greater than 0 and less than n.

Specifically, after acquiring n bits of parallel data, the sending device interconnected between chips may convert the n bits of parallel data into m bits of transmission data according to the number of sending pins that can be actually used.

Furthermore, the sending device of the inter-chip interconnection converts the buffered n-bit parallel data into m-bit transmission data according to the number of sending pins which can be actually used. And after being converted into the m-bit transmission data, the m-bit transmission data may be buffered first.

103. And transmitting the m bits of transmission data to receiving devices interconnected among the chips through m transmitting pins according to a vld/rdy handshake protocol.

Specifically, after converting n-bit parallel data into m-bit transmission data, the sending device interconnected among the slices sends the m-bit transmission data to the receiving device interconnected among the slices through m sending pins according to the vld/rdy handshake protocol.

Further, the sending device of the inter-chip interconnection sends the buffered m bits of transmission data to the receiving device of the inter-chip interconnection through m sending pins according to the vld/rdy handshake protocol.

The embodiment of the invention provides a sending method for inter-chip interconnection, which is applied to a sending device for inter-chip interconnection. And the sending device interconnected among the chips acquires n-bit parallel data according to the vld/rdy handshake protocol and converts the n-bit parallel data into m-bit transmission data. And transmitting the m bits of transmission data to receiving devices interconnected among the chips through m transmitting pins according to a vld/rdy handshake protocol. Therefore, the sending device of the inter-chip interconnection can convert n-bit parallel data needing to be sent into m-bit transmission data through the parallel-serial data conversion circuit, and then can send the m-bit transmission data to the receiving device of the inter-chip interconnection by only using m sending pins. Compared with the prior art that a sending device for inter-chip interconnection needs n sending pins to send n-bit parallel data to a receiving device for inter-chip interconnection, the sending device for inter-chip interconnection can send data only through m sending pins, reduces the number of used pins when the inter-chip interconnection is realized, and further reduces the complexity of routing of signal lines connected between at least two FPGAs, thereby reducing the complexity of inter-chip interconnection.

An embodiment of the present invention provides a method for receiving inter-chip interconnection, as shown in fig. 10, including:

201. and the receiving devices interconnected among the chips acquire m bits of transmission data sent by the sending devices interconnected among the chips through m receiving pins according to the vld/rdy handshake protocol.

Wherein m is an integer greater than 0.

Specifically, after the sending devices interconnected between the chips send m bits of transmission data through m sending pins, the receiving devices interconnected between the chips can obtain the m bits of transmission data sent by the sending devices interconnected between the chips by using m receiving pins corresponding to the m sending pins of the sending devices interconnected between the chips according to the vld/rdy handshake protocol.

Furthermore, after receiving the m bits of transmission data, the inter-chip interconnect receiving device may first buffer the m bits of transmission data.

202. And converting the m-bit transmission data into n-bit parallel data, and sending the n-bit parallel data to the data processor according to the vld/rdy handshake protocol so that the data processor processes the n-bit parallel data.

Wherein n is an integer greater than m.

Specifically, after receiving m bits of transmission data according to the vld/rdy handshake protocol, the sending devices interconnected between the chips convert the m bits of transmission data into n bits of parallel data. And sends the n bits of parallel data to the data processor according to the vld/rdy handshake protocol. In this way, the data processor can process the parallel data of n bits accordingly.

Further, the sending devices interconnected between the chips can convert the buffered m-bit transmission data into n-bit parallel data according to the vld/rdy handshake protocol. And caching the converted n-bit parallel data, and sending the cached n-bit parallel data to a data processor.

The embodiment of the invention provides a receiving method for interconnection among chips. And converting the m-bit transmission data into n-bit parallel data, and sending the n-bit parallel data to a data processor according to the vld/rdy handshake protocol. Thus, when the sending device of the inter-chip interconnection converts the n-bit parallel data into the m-bit transmission data and sends the m-bit transmission data to the receiving device of the inter-chip interconnection through the m sending pins, the receiving device can receive the m-bit transmission data through the m receiving pins. And reconverts it into n-bit parallel data. Compared with the prior art that a sending device for chip-to-chip interconnection needs n sending pins to send n-bit parallel data to a receiving device for chip-to-chip interconnection, the sending device can send data only through m sending pins and m receiving pins, reduces the number of used pins when chip-to-chip interconnection is realized, and further reduces the complexity of routing of signal lines connected between at least two FPGAs, thereby reducing the complexity of chip-to-chip interconnection.

An embodiment of the present invention provides an inter-chip interconnection system, as shown in fig. 11, including: a transmitting means 31 of the inter-chip interconnection, and a receiving means 32 of the inter-chip interconnection.

The inter-slice interconnection transmitting device 31 is the inter-slice interconnection transmitting device described in the above embodiment.

The receiving means 32 for inter-chip interconnection is the receiving means for inter-chip interconnection described in the above embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be physically included alone, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. An inter-chip interconnect transmission apparatus, comprising: a parallel-serial data conversion circuit, at least one transmission pin; the output end of the parallel-serial data conversion circuit is connected with the at least one sending pin; the input end of the parallel-serial data conversion circuit is connected with the data sending processor;

the parallel-serial data conversion circuit is used for acquiring n-bit parallel data from the data sending processor according to a vld/rdy handshake protocol, converting the n-bit parallel data into m-bit transmission data, and sending the m-bit transmission data to an inter-chip interconnected receiving device through m sending pins according to the vld/rdy handshake protocol; n is an integer greater than 1, and m is an integer greater than 0 and less than n.

2. The transmission apparatus according to claim 1, further comprising: an asynchronous first-in first-out FIFO processor;

the input end of the parallel-serial data conversion circuit is connected with the data sending processor, and the parallel-serial data conversion circuit comprises: the input end of the asynchronous FIFO processor is connected with the data sending processor; the output end of the asynchronous FIFO processor is connected with the input end of the parallel-serial data conversion circuit;

the asynchronous FIFO processor is used for acquiring and storing the n-bit parallel data from the data sending processor;

the parallel-serial data conversion circuit is specifically used for acquiring the n-bit parallel data from the asynchronous FIFO processor according to a vld/rdy handshake protocol.

3. The transmission apparatus according to claim 1 or 2, characterized by further comprising: a synchronous FIFO processor;

the output end of the parallel-serial data conversion circuit is connected with the at least one sending pin, and the parallel-serial data conversion circuit comprises:

the input end of the synchronous FIFO processor is connected with the output end of the parallel-serial data conversion circuit, and the output end of the synchronous FIFO processor is connected with the at least one sending pin;

the parallel-serial data conversion circuit is specifically used for sending the m bits of transmission data to the synchronous FIFO processor according to the vld/rdy handshake protocol;

and the synchronous FIFO processor is used for receiving and storing the m bits of transmission data and sending the m bits of transmission data to the receiving devices interconnected among the chips through the m sending pins according to the vld/rdy handshake protocol.

4. The transmission apparatus according to claim 3, characterized by further comprising: input-output processor IOP;

the connection of the output of the synchronous FIFO processor to the at least one transmit pin comprises: the output end of the synchronous FIFO processor is connected with the input end of the IOP, and the output end of the IOP is connected with the at least one sending pin;

the synchronous FIFO processor is specifically used for sending the m bits of transmission data to the IOP according to a vld/rdy handshake protocol;

the IOP is used for receiving the m bits of transmission data and sending the m bits of transmission data to the receiving device interconnected among the chips by using the m sending pins.

5. An inter-chip interconnect receiver, comprising: at least one receiving pin, a serial-to-parallel data conversion circuit; the input end of the serial-parallel data conversion circuit is connected with the at least one receiving pin, and the output end of the serial-parallel data conversion circuit is connected with the data processor;

the serial-parallel data conversion circuit is used for acquiring m bits of transmission data sent by sending devices which are interconnected among chips through m receiving pins according to a vld/rdy handshake protocol, converting the m bits of transmission data into n bits of parallel data, and sending the n bits of parallel data to the data processor according to the vld/rdy handshake protocol; m is an integer greater than 0; and n is an integer greater than m.

6. The receiving device of claim 5, further comprising: an asynchronous first-in first-out FIFO processor;

the output end of the serial-parallel data conversion circuit is connected with the data processor and comprises:

the output end of the serial-parallel data conversion circuit is connected with the input end of the asynchronous FIFO processor;

the serial-parallel data conversion circuit is specifically used for sending the n-bit parallel data to the asynchronous FIFO processor according to a vld/rdy handshake protocol;

and the asynchronous FIFO processor is also used for receiving and storing the n-bit parallel data and sending the n-bit parallel data to the data processor according to the vld/rdy handshake protocol.

7. The receiving device of claim 6, further comprising: a synchronous FIFO processor;

the input end of the serial-parallel data conversion circuit is connected with the at least one receiving pin, and the serial-parallel data conversion circuit comprises:

the input end of the serial-parallel data conversion circuit is connected with the output end of the synchronous FIFO processor, and the input end of the synchronous FIFO processor is connected with the at least one receiving pin;

the synchronous FIFO processor is used for receiving m bits of transmission data sent by sending devices which are interconnected among the chips through m receiving pins according to the vld/rdy handshake protocol and storing the m bits of transmission data;

and the serial-parallel data conversion circuit is specifically used for acquiring m bits of transmission data sent by sending devices interconnected among chips from the synchronous FIFO processor according to the vld/rdy handshake protocol.

8. A method for sending interconnection between chips is characterized by comprising the following steps:

the sending device interconnected among the chips acquires n-bit parallel data according to a vld/rdy handshake protocol; n is an integer greater than 1;

converting the n-bit parallel data into m-bit transmission data; m is an integer which is more than 0 and less than n;

and sending the m bits of transmission data to receiving devices interconnected among the chips through m sending pins according to the vld/rdy handshake protocol.

9. An inter-chip interconnection receiving method, comprising:

the inter-chip interconnected receiving device acquires m bits of transmission data sent by the inter-chip interconnected sending device through m receiving pins according to a vld/rdy handshake protocol; m is an integer greater than 0;

converting the m bits of transmission data into n bits of parallel data, and sending the n bits of parallel data to a data processor according to the vld/rdy handshake protocol, so that the data processor processes the n bits of parallel data; and n is an integer greater than m.

10. An inter-chip interconnection system, comprising: a transmitting device for inter-chip interconnection, and a receiving device for inter-chip interconnection; wherein,

the sending device of the inter-chip interconnection is the sending device of the inter-chip interconnection of any one of claims 1 to 4;

the receiving means for inter-chip interconnection as claimed in any one of claims 5 to 7.