CN104979205A - Formation method of transistor - Google Patents
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- CN104979205A CN104979205A CN201410135925.7A CN201410135925A CN104979205A CN 104979205 A CN104979205 A CN 104979205A CN 201410135925 A CN201410135925 A CN 201410135925A CN 104979205 A CN104979205 A CN 104979205A
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Abstract
The present invention provides a formation method of a transistor. In a gate last technology of the transistor, a protection layer is formed on the surface of an etching barrier layer above a source-drain region, the etching barrier layer is etched, and the etching barrier layer on the grid structures is thinned. After the etching barrier layer on the grid structures is thinned, the separation distance between the grid structures is increased, so that an interlayer dielectric layer can be filled between the grid structures more easily. During the process of thinning the etching barrier layer on the grid structures, the protection layer protects the etching barrier layer above the source-drain region from being influenced by etching, so that the thickness of the etching barrier layer above the source-drain region does not change basically after the etching barrier layer on the grid structures is thinned, and the effective protection can be provided for the source-drain region.
Description
Technical field
The present invention relates to semiconductor applications, be specifically related to a kind of formation method of transistor.
Background technology
Along with the transistor density on integrated circuit improves constantly, size and the spacing of grid also constantly reduce, the spacing of respective gates structure also constantly reduces, fill between multiple grid structure in the process of interlayer dielectric layer, interlayer dielectric layer is difficult to be filled in spacing narrow between multiple grid structure, the interlayer dielectric layer pattern out-of-flatness of such formation, and be easy to produce space or crack in interlayer dielectric layer.
As indicated with 1, show the cutaway view of a kind of transistor forming process of prior art, form grid structure 04 having on fleet plough groove isolation structure 03, in the substrate 01 that described grid structure 04 exposes, form source-drain area 02, described grid structure 04 and source-drain area 02 form interlayer dielectric layer (not shown).After forming interlayer dielectric layer, also need to etch described interlayer dielectric layer, formed in interlayer dielectric layer and expose described source-drain area 02 through hole, to form electric conducting material in through-holes, realize source-drain area 02 and periphery circuit electrical connection.
In order to avoid in the etching interlayer dielectric layer process of subsequent technique, source-drain area 02 sustains damage, before formation interlayer dielectric layer, first at source-drain area 02 and grid structure 04 surface coverage one deck etching barrier layer 05.
As shown in Fig. 1 centre circle, in the process covering etching barrier layer 05, the etching barrier layer 05 that the drift angle place of grid structure 04 covers is more compared with other regions, easy generation is as the bulge of irising out in Fig. 1, make the spacing between grid structure less, thus increase the difficulty of filling interlayer dielectric layer between grid structure, and the quality of etching barrier layer 05 can have influence on the quality of source-drain area 02.
Therefore, how, to ensure the quality of etching barrier layer above source-drain area, to become those skilled in the art's problem demanding prompt solution while filling effect at raising interlayer dielectric layer between pseudo-grid structure.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of transistor, while filling capacity, ensures the quality of etching barrier layer above source-drain area at raising interlayer dielectric layer between pseudo-grid structure.
For solving the problem, the invention provides a kind of formation method of transistor, comprising:
Substrate is provided;
Form grid structure over the substrate;
Source-drain area is formed in the substrate that described grid structure exposes;
At described grid structure and source-drain area surface coverage etching barrier layer;
Etching barrier layer surface above described source-drain area forms protective layer;
Described etching barrier layer is etched, the etching barrier layer on thinning grid structure;
Remove described protective layer;
Etching barrier layer after etching forms interlayer dielectric layer.
Optionally, described etching barrier layer is silicon nitride.
Optionally, after described grid structure and source-drain area surface coverage etching barrier layer, before forming protective layer, described formation method also comprises: carry out silicon doping to described etching barrier layer.
Optionally, the etching barrier layer above source-drain area at the patterned mask layer of described etching barrier layer surface coverage, is exposed before forming protective layer in the etching barrier layer surface above described source-drain area.
Optionally, described patterned mask layer is patterned photoresist.
Optionally; after the mask layer of cover graphics, adopt liquid phase deposition, the etching barrier layer surface above the source-drain area that described patterned mask layer exposes forms protective layer; before described etching barrier layer is etched, remove described patterned mask layer.
Optionally, described substrate is silicon substrate, and the material of described protective layer is silica.
Optionally, the step that liquid phase deposition forms protective layer comprises: pass into silicate fluoride solution and water on etching barrier layer surface, and reaction generates silica.
Optionally, hydrofluoric acid is adopted to remove described protective layer.
Optionally, described grid structure is the pseudo-grid structure comprising pseudo-grid, and described formation method also comprises: after formation interlayer dielectric layer, remove described pseudo-grid;
Metal gates is formed at pseudo-grid original position.
Optionally, described transistor is fin formula field effect transistor, after formation provides substrate, before forming grid structure, comprising: on substrate, form fin;
The step of described formation grid structure comprises: on described fin, form the grid structure across described fin;
The step forming source-drain area in the substrate that described grid structure exposes comprises: in the fin that described grid structure exposes, form source region and drain region.
Compared with prior art, technical scheme of the present invention has the following advantages:
Etching barrier layer surface above source-drain area forms protective layer; etching barrier layer is etched; etching barrier layer on thinning grid structure; after etching barrier layer on thinning grid structure; spacing between grid structure increases, and makes more easily to fill interlayer dielectric layer between grid structure.In the process of the etching barrier layer on thinning grid structure; protective layer plays the effect of the etching barrier layer above protection source-drain area from etching impact; after making the etching barrier layer on thinning grid structure; the thickness of the etching barrier layer above source-drain area does not change substantially; effective protection can be provided for source-drain area; etching barrier layer simultaneously on thinning grid structure can provide space for filling between grid structure interlayer dielectric layer, is conducive to the filling effect improving interlayer dielectric layer..
Further, at the patterned mask layer of described etching barrier layer surface coverage, expose the etching barrier layer of active region, described patterned mask layer is patterned photoresist, adopt liquid phase deposition, protective layer is formed on the etching barrier layer surface of described active region, described etching barrier layer is silicon nitride, the material of described protective layer is silica, the silica that liquid phase deposition is formed easily is deposited on material surface, and be difficult to deposition on a photoresist, therefore, formed in the process of protective layer at liquid phase deposition, protective layer is substantially only deposited on the etching barrier layer surface that patterned photoresist exposes, only deposition on a small quantity or substantially not Deposition of protective layer on a photoresist, directly can remove the photoresist that unprotect layer blocks like this, in addition, the etching barrier layer that protective layer can also be made only to be deposited on more accurately above source-drain area is surperficial, reduces because protective layer is formed at problem grid structure hindering thinning etching barrier layer.
Accompanying drawing explanation
Fig. 1 is the cutaway view of a kind of Transistor forming method of prior art;
Fig. 2 to Fig. 8 is the cutaway view of each step in Transistor forming method one embodiment of the present invention.
Embodiment
In the formation method of prior art transistor, the etching barrier layer being covered in source region and drain region easily too much forms bulge in the drift angle place of grid structure deposition, described bulge makes the spacing between grid structure less, increases the difficulty of filling interlayer dielectric layer between grid structure.In addition, easily to the etching barrier layer on source region and surface, drain region, poly-injury was produced to the process that described bulge is removed, and have impact on the protective effect of etching barrier layer to source region and drain region.
In order to solve the problems of the technologies described above, the invention provides a kind of formation method of transistor.Described formation method comprises: provide substrate; Grid structure is formed at described substrate surface; Source-drain area is formed in the substrate that described grid structure exposes; At described grid structure and source-drain area surface coverage etching barrier layer; Etching barrier layer surface above described source-drain area forms protective layer; Described etching barrier layer is etched, the etching barrier layer on thinning grid structure; Remove described protective layer; Etching barrier layer after etching forms interlayer dielectric layer.
The present invention forms protective layer by the etching barrier layer surface above described source-drain area; make etching etching barrier layer; with in the process of the etching barrier layer bulge on thinning grid structure; protective layer plays the effect of protection etching barrier layer from etching impact; after making the etching barrier layer bulge on thinning grid structure; the thickness of the etching barrier layer above source-drain area does not change substantially, for source-drain area provides effective protection.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Referring to figs. 2 to the cutaway view that Fig. 8 is each step in Transistor forming method one embodiment of the present invention.It should be noted that, in the present embodiment, described transistor is CMOS, but therefore should not limit the transistor types that Transistor forming method of the present invention formed, in other embodiments, Transistor forming method of the present invention can also for the formation of fin formula field effect transistor.
With reference to figure 2, provide substrate 100, in substrate 100, form isolation structure 101.
In the present embodiment, described substrate 100 is silicon substrate, and described substrate 100 can also be other Semiconductor substrate such as germanium silicon substrate or silicon-on-insulator substrate, does not do any restriction to this present invention.
Particularly, after substrate 100 is provided, also in substrate 100, form isolation structure 101, substrate 100 is divided into multiple part, to form the transistor being isolated structure 101 and keeping apart in different parts.
In the present embodiment, described isolation structure 101 is fleet plough groove isolation structure, and in other embodiments, described isolation structure can also be carrying out local oxide isolation.In other embodiments, described isolation structure 101 can not also be formed.
Continue with reference to figure 2, described substrate 100 forms multiple grid structure 103, in the substrate 100 that grid structure 103 exposes, forms multiple source-drain area 102, at substrate 100 and grid structure 103 surface coverage etching barrier layer 104.
Metal gate process after adopting in the present embodiment, grid structure 103 comprises pseudo-grid 103A and gate dielectric layer 103B.
Wherein, the material of pseudo-grid 103A is polysilicon, and in follow-up technique, pseudo-grid 103A is removed, and metal material will be filled to form metal gates in pseudo-grid 103A position.But the concrete material of the present invention to pseudo-grid 103A does not limit.
The material of gate dielectric layer 103B is silica, and the effect of gate dielectric layer 103B is as the dielectric layer between metal gates and substrate 100, but the concrete material of the present invention to gate dielectric layer 103B does not limit.
In addition, side wall (not shown) is also formed at pseudo-grid 103A sidewall, to protect pseudo-grid 103A.
In the present embodiment, multiple source-drain area 102 is formed in the substrate 100 exposed at described grid structure 103.The concrete grammar forming multiple source-drain area 102 is this area conventional techniques, and the present invention does not repeat them here.
In the present embodiment, after formation source-drain area 102, at described substrate 100 and grid structure 103 surface coverage etching barrier layer 104.The effect of described etching barrier layer 104 is, avoid in follow-up etching technics, source-drain area 102 sustains damage by etching affects.
Particularly, the material of described etching barrier layer 104 is silicon nitride, but the concrete material of the present invention to etching barrier layer 104 does not limit, and in other embodiments, described etching barrier layer 104 can also be other materials.
It should be noted that, the etching barrier layer 104 covered at the drift angle place of grid structure 103 is more compared with other regions, the bulge of easy generation as shown in circle, make the spacing between grid structure 103 narrower, between grid structure 103, fill interlayer dielectric layer more difficult.
Also it should be noted that, in the present embodiment, after described substrate 100 and grid structure 103 surface coverage etching barrier layer 104, silicon doping is carried out to the etching barrier layer 104 taking silicon nitride as material, such benefit is, silicon nitride after silicon doping is firmer and anti-etching ability is stronger, and make in the etching of follow-up thinning etching barrier layer 104, the speed of etching is slower, enhance the controllability of etching, reduce and that be damaged to as the etching barrier layers 104 such as pseudo-grid 103A beyond other structures probability too high due to etch rate.
With reference to figure 3, at the patterned mask layer 105 of described etching barrier layer 104 surface coverage, expose the etching barrier layer 104 above source-drain area 102.
In the present embodiment, described patterned mask layer 105 is patterned photoresist.Patterned mask layer 105 exposes the etching barrier layer 104 above source-drain area 102, and follow-up protective layer can be made only to be formed at above source-drain area 102.
With reference to figure 4, etching barrier layer 104 surface above described source-drain area 102 forms protective layer 106.
The benefit that etching barrier layer 104 surface above described source-drain area 102 forms protective layer 106 is; etch etching barrier layer 104 in the process of the etching barrier layer 104 above with thinning grid structure 103 follow-up, the etching barrier layer 104 above source-drain area 102 is subject to the protection of described protective layer 106.Etching barrier layer 104 above such source-drain area 102 can preferably for source-drain area 102 provides protection in the process of follow-up formation metal gates.
In the present embodiment; employing liquid phase deposition deposition materials is the protective layer 106 of silica; particularly; silicate fluoride solution and water is passed at etching barrier layer 104 and photoresist surface; react with the etching barrier layer 104 taking silicon nitride as material and generate silica, the silica of deposition forms described protective layer 106.
The benefit of liquid phase deposition Deposition of protective layer 106 is adopted to be; the silica that liquid phase deposition is formed easily is deposited on the surface of material; and be difficult to deposition on a photoresist; therefore; formed in the process of protective layer 106 at liquid phase deposition; protective layer 106 is substantially only deposited on etching barrier layer 104 surface that patterned photoresist exposes, on a photoresist only deposition on a small quantity or substantially not Deposition of protective layer 106, so that the photoresist that follow-up direct removal unprotect layer covers.
In addition; the protective layer 106 of such deposition is only positioned at etching barrier layer 104 surface above source-drain area 102; etching barrier layer 104 is etched in the process of the etching barrier layer 104 above with thinning grid structure 103 follow-up; etching barrier layer 104 only above source-drain area 102 is protected, and makes etching barrier layer 104 on grid structure 103 expose thus can be thinned.
Further; adopt and first form patterned photoresist; again through the step of liquid phase deposition Deposition of protective layer 106; the etching barrier layer 104 that protective layer 106 can be made to be deposited on more accurately above source-drain area 102 is surperficial; reduce to be formed on grid structure 103 due to protective layer 106, thinning etching barrier layer 104 is caused to the probability of obstruction.
But the concrete material of the present invention to protective layer 106 does not limit, the material of described protective layer 106 can also for being different from the other materials of etching barrier layer 104 material.
The formation method of the present invention to protective layer 106 does not also limit; in other embodiments; described protective layer 106 can also adopt following generation type: first form the rete covering etching barrier layer 104 with chemical vapour deposition technique; again photoetching is carried out to described rete; remove the described rete of part, the rete on the etching barrier layer 104 above the source-drain area 102 of reservation forms protective layer 106.
With reference to figure 5, remove described patterned photoresist, particularly, in the present embodiment, adopt cineration technics to remove described patterned photoresist.Because liquid phase deposition is formed in the process of protective layer 106; silica is easily deposited on the surface of material; and be difficult to deposition on a photoresist; therefore only deposition on a small quantity or substantially not Deposition of protective layer 106 on a photoresist; therefore, be not easy to produce when adopting cineration technics to remove described patterned photoresist and remain.
With reference to figure 6, described etching barrier layer 104 is etched, with the etching barrier layer 104 on thinning grid structure 103.While etching barrier layer 104 above thinning grid structure 103, the bulge of the drift angle place etching barrier layer 104 of grid structure 103 is also removed or part is removed, spacing between grid structure 103 is increased, between grid structure 103, more easily fills interlayer dielectric layer.
Particularly, the material of described etching barrier layer 104 is silicon nitride, SiCoNi method is adopted to etch described etching barrier layer 104, such benefit is, the etching intensity of SiCoNi method less and be easier to control, in the process that etching barrier layer 104 is etched, by adjustment etch period and intensity, easily the bulge of etching barrier layer 104 on grid structure 103 drift angle can be removed, and the etching barrier layer 104 of grid structure 103 upper surface and sidewall is thinned, etching barrier layer 104 under protective layer 106 covers does not remain by the impact of SiCoNi method.
But the concrete lithographic method of the present invention to the described etching barrier layer 104 of etching does not limit, and in other embodiments, can also adopt the etching barrier layer 104 on dry etching or the thinning grid structure 103 of wet etching.
Etching barrier layer 104 on thinning grid structure 103, after removing the bulge of etching barrier layer 104, etching barrier layer 104 thickness on grid structure 103 surface is homogeneous, pattern is smooth, space like this between grid structure 103 can not be occupied by bulge, makes follow-uply to fill interlayer dielectric layer relatively easily between grid structure 103.
With reference to figure 7, remove described protective layer 106.
In the present embodiment, the material due to protective layer 106 is silica, so adopt hydrofluoric acid to remove described protective layer 106.What adopt hydrofluoric acid silica can be removed is comparatively clean, and less to other structure influences such as etching barrier layer 104 grade.But the present invention does not limit the etching agent that the described protective layer 106 of removal adopts.
With reference to figure 8, after the described protective layer 106 of removal, between described substrate 100 surface and grid structure 103, form interlayer dielectric layer 107.
Particularly, in the present embodiment, adopt chemical vapour deposition technique, interlayer dielectric layer 107 is filled between described substrate 100 surface and grid structure 103, and make interlayer dielectric layer 107 higher than grid structure 103, the material of described interlayer dielectric layer 107 is silica, but the material of the present invention to interlayer dielectric layer 107 does not limit.
Due in step before, while the etching barrier layer 104 above thinning grid structure 103, the bulge of the drift angle place etching barrier layer 104 of grid structure 103 is also removed, spacing between grid structure 103 is increased, more easily interlayer dielectric layer 107 is filled between grid structure 103, interlayer dielectric layer 107 better quality formed between grid structure 103, is not easy to produce the defects such as space.
Chemical vapour deposition technique is adopted to be formed in the process of silica, silica can be made finer and close by the method reducing deposition rate, thus improve the anti-etching ability of interlayer dielectric layer 107, make in the technique of follow-up formation metal gates, interlayer dielectric layer 107 can keep good pattern.
After formation interlayer dielectric layer 107, cmp is carried out to expose the surface of pseudo-grid 103A to interlayer dielectric layer 107.
Pseudo-grid 103A in following removal grid structure 103, after removing pseudo-grid 103A, forms metal gates at pseudo-grid 103A original position.The method removing pseudo-grid 103A and formation metal gates is this area conventional techniques, and the present invention is not restricted this.
It should be noted that, the formation method of transistor of the present invention is not limited to adopt rear grid technique to form the embodiment of metal gate transistor, can also form the transistor with polysilicon gate, correspondingly, without the need to removing pseudo-grid.
After formation interlayer dielectric layer, carry out interlayer dielectric layer etching the through hole being formed and expose source region and drain region, in the process forming through hole, etching barrier layer plays the effect in the described source region of protection and drain region, thus improves the performance of transistor.
It should be noted that, the formation method of transistor of the present invention for the formation of fin formula field effect transistor, can also be with above-described embodiment difference, after formation provides substrate, before forming grid structure, comprising: on substrate, form fin.Particularly, substrate (such as silicon substrate) is etched, form fin (Fin).
The step of described formation grid structure comprises: on described fin, form the grid structure across described fin.
The step forming source-drain area in the substrate that described grid structure exposes comprises: formed to source region and drain region in the fin that described grid structure is exposed.The etching barrier layer formed afterwards covers the surface of the fin that described grid structure and described grid structure expose.
Subsequent step is identical with the formation method of CMOS, does not repeat them here, and in the present embodiment, by the etching barrier layer at thinning grid structure drift angle place, improves the filling capacity of interlayer dielectric layer; Meanwhile, in etching process, also protecting the etching barrier layer on fin surface by arranging protective layer, to improve the protective capability of etching barrier layer to fin, and then improve the performance of fin formula field effect transistor.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (11)
1. a formation method for transistor, is characterized in that, comprising:
Substrate is provided;
Form grid structure over the substrate;
Source-drain area is formed in the substrate that described grid structure exposes;
At described grid structure and source-drain area surface coverage etching barrier layer;
Etching barrier layer surface above described source-drain area forms protective layer;
Described etching barrier layer is etched, the etching barrier layer on thinning grid structure;
Remove described protective layer;
Etching barrier layer after etching forms interlayer dielectric layer.
2. form method as claimed in claim 1, it is characterized in that, described etching barrier layer is silicon nitride.
3. form method as claimed in claim 2, it is characterized in that, after described grid structure and source-drain area surface coverage etching barrier layer, before forming protective layer, described formation method also comprises: carry out silicon doping to described etching barrier layer.
4. form method as claimed in claim 1, it is characterized in that, the etching barrier layer above source-drain area at the patterned mask layer of described etching barrier layer surface coverage, is exposed before forming protective layer in the etching barrier layer surface above described source-drain area.
5. form method as claimed in claim 4, it is characterized in that, described patterned mask layer is patterned photoresist.
6. form method as claimed in claim 5; it is characterized in that; after the mask layer of cover graphics; adopt liquid phase deposition; etching barrier layer surface above the source-drain area that described patterned mask layer exposes forms protective layer; before described etching barrier layer is etched, remove described patterned mask layer.
7. form method as claimed in claim 6, it is characterized in that, described substrate is silicon substrate, and the material of described protective layer is silica.
8. form method as claimed in claim 7, it is characterized in that, the step that liquid phase deposition forms protective layer comprises: pass into silicate fluoride solution and water on etching barrier layer surface, and reaction generates silica.
9. form method as claimed in claim 7, it is characterized in that, adopt hydrofluoric acid to remove described protective layer.
10. form method as claimed in claim 1, it is characterized in that, described grid structure is the pseudo-grid structure comprising pseudo-grid, and described formation method also comprises: after formation interlayer dielectric layer, remove described pseudo-grid; Metal gates is formed at pseudo-grid original position.
11. form method as claimed in claim 1, it is characterized in that, described transistor is fin formula field effect transistor, after formation provides substrate, before forming grid structure, comprising: on substrate, form fin; The step of described formation grid structure comprises: on described fin, form the grid structure across described fin; The step forming source-drain area in the substrate that described grid structure exposes comprises: in the fin that described grid structure exposes, form source region and drain region.
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| CN117276202A (en) * | 2023-11-16 | 2023-12-22 | 合肥晶合集成电路股份有限公司 | Forming method of contact hole and semiconductor structure |
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| US20050142784A1 (en) * | 2003-12-30 | 2005-06-30 | Kim Dae K. | Methods of fabricating semiconductor devices |
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