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CN104978447B - The modeling of the accurate table lookup model of transistor and estimation method - Google Patents

The modeling of the accurate table lookup model of transistor and estimation method Download PDF

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CN104978447B
CN104978447B CN201410146475.1A CN201410146475A CN104978447B CN 104978447 B CN104978447 B CN 104978447B CN 201410146475 A CN201410146475 A CN 201410146475A CN 104978447 B CN104978447 B CN 104978447B
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CN104978447A (en
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曾璇
王胜国
杨帆
李潇
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Fudan University
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Abstract

This method belongs to integrated circuit fields, is related to a kind of the transistor accurately modeling of approximate table lookup model and estimation method.By establishing the non-uniform grid Table Model of transistor in nonlinear circuit, by the quick valuation searched and its correspond to physical parameter for waiting estimating in the look-up tables'implementation simulation process of simple Hash mapping and auxiliary a little.This method inherits the advantage adaptively divided based on tree shaped model approximation method, and it is slow to solve the problems, such as to be currently based on unit search speed in the non-uniform grid model of tree.The continuity and flatness for ensureing that Table Model calculates by carrying out Hermite spline interpolations three times on non-uniform grid, overcome the problem of derivative discontinuously leads to convergence difficulties in the prior art, this method can substantially speed up transistor model calculating process in simulation process, effectively shortened in circuit simulation with acceptable memory requirements and the time of transient analysis and obtain higher precision.

Description

The modeling of the accurate table lookup model of transistor and estimation method
Technical field
This method belongs to integrated circuit fields, and in particular to a kind of transistor (MOSFET) essence for integrated circuit simulating The modeling of true table lookup model and estimation method.
Technical background
With the raising of super large-scale integration (ULSI) complexity, high-speed simulation and verification become in design cycle It becomes more and more important.The traditional fast crystal pipe grade emulation (fast-spice) of studies have shown that is often obtained using sacrificing precision as cost Significant gain on simulation velocity, and be widely used in large scale digital circuit verification and Digital Analog Hybrid Circuits function it is imitative Very.But as technology feature size strongly reduces, in order to accurately portray the deep-submicron characteristic of transistor, modem transistors grade is imitative True device often uses complicated transistor analytic modell analytical model, and such as BSIM and EKV, this makes traditional rapid simulation method be difficult to be applicable in In the emulation of required precision higher analog circuit, standard cell lib and IP kernel.
Table Model technology is usually built by the limited device operating point obtained from transistor analytic modell analytical model a series of Multi-dimensional spreadsheet is special (including mainly I-V and Q-V characteristics) come the input and output for portraying device.The fineness of appropriate selection structure table And combine rational interpolation method, Table Model can in approximate emulation transistor behavioral trait, and be successfully applied to pair In the high memory yield analysis (8) of required precision and transistor leakage analysis.
Prior art discloses in transistor-level simulation, the main process of transient analysis is one given point in time of estimation The voltage and current value of upper all nodes of circuit, and the value of upper circuit node of next time point of extrapolating.Modem transistors grade emulates Device generally uses circuit on Newton method (Newton-Raphson method) iterative solution current point in time implicitly or explicitly to accumulate Divide equation to obtain upper circuit node voltage current value of next time point, recursion repeats this process until emulation terminates.By In the intrinsic high non-linearity feature of modern crystals tube device, Newton iteration generally requires multistep and could receive on each time point It holds back, and Newton iteration will all call transistor model to the valuation of device operating point each time, therefore to height in transient analysis Complicated transistor model valuation is a more time-consuming process.It points out for highly complex circuit, it is close in transient analysis The valuation that the time of 60%-80% is used for transistor analytic modell analytical model calculates, therefore is simplified using rational Table Model approximation The valuation of transistor physics parameter, which calculates, can effectively shorten the simulation time of circuit.
The acceleration of simulation process and acceptable simulation accuracy can be obtained simultaneously based on above 2 Table Model technologies, In practice, realize that the difficult point of Table Model technology is how between model accuracy, table scale and efficient interpolation calculation It obtains and balances and ensure (the main monotonicity for including interpolation of the compatibility between valuation calculating and Newton iteration solving circuit equation And continuity).
The Table Model of the early stage of the prior art is as a result of uniform grid so that model accuracy is often limited to huge Demand of the table scale (especially three-dimensional grid) to storage and needing obtained and enough estimate using complicated interpolation method It is worth precision.With dramatically increasing for transistor size in circuit simulation and physical model complexity, table is built by non-uniform grid The mode of lattice is widely adopted, and by placing more mesh points in the non-linear stronger region of transistor, it can be with opposite Transistor physics nonlinearity in parameters behavior is more accurately portrayed in smaller storage demand.Compared to in the prior art it is related with Division rule is established to semiempirical according to the working region of transistor and builds structured grid (structured grid) Method has and has researched and proposed a kind of method that can adaptively build table according to preset error requirement, wherein adopting With the unstructured grid (unstructured grid) based on tree to further reduce storage overhead, e.g., This method is used to build Table Model for SOI;The development above method is further improved to ensure the monotonicity of interpolation;But phase Than in structured grid, unstructured grid needs to ensure the monotonicity and continuously of Table Model interpolation using complicated algorithm Property cause to establish the increase of table time overhead before emulation, this method another disadvantage is that in tree grid cell (Cell) search speed (time complexity of O (log N)) is relatively slow, and it is deeper that especially required grid cell corresponds to node depth When, ratio shared by search time will dramatically increase during valuation calculates, it is related be respectively adopted in the prior art it is greedy search for and The method of path compression shortens search time, due in non-linear stronger region, valuation calculate needed for grid cell often The deeper leafy node of depth in tree is corresponded to, spatially the adjacent corresponding node of two grid cells has very big probability to be located at Binary space is divided in two deeper subtrees of different depth of (BSP) tree, so that method therein is to search speed Improve it is limited, or because be directed to iteration carry out data structure between transfer zone carry out overhead.
In conclusion the method for building non-uniform grid in the Table Model technology of the prior art is difficult to ensure to build simultaneously The versatility of table and being simple and efficient property.
The prior art related to the present invention has following bibliography:
⑴Rewieński,"A perspective on fast-SPICE simulation technology." Simulation and Verification of Electronic and Biological Systems.Springer Netherlands,2011.23-42.
⑵Y.S.Chauhan,S.Venugopalan,M.A.Karim,S.Khandelwal,N.Paydavosi, P.Thakur,A.M.Niknejad and C.C.Hu,“BSIM–industry standard compact MOSFET models”,IEEE European Solid-State Device Research Conference,Bordeaux,France, Sept.2012.
⑶Bucher M,Enz C,Krummenacher F,et al.The EKV 3.0 compact MOS transistor model:accounting for deep-submicron aspects[C]//Proc.MSM Int.Conf.,Nanotech 2002.2002:670-673.
⑷Nadezhin D,Gavrilov S,Glebov A,et al.SOI transistor model for fast transient simulation[C]//Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design.IEEE Computer Society,2003:120.
⑸Yang B,McGaughy B.An essentially non-oscillatory(ENO)high-order accurate adaptive table model for device modeling[C]//Proceedings of the 41st annual Design Automation Conference.ACM,2004:864-867.
⑹Bourenkov V,McCarthy K G,Mathewson A.MOS table models for circuit simulation[J].Computer-Aided Design of Integrated Circuits and Systems,IEEE Transactions on,2005,24(3):352-362.
⑺Caddemi A,Crupi G,et al..Analytical Construction of Nonlinear Lookup Table Model for Advanced Microwave Transistors[C]//Telecommunications in Modern Satellite,Cable and Broadcasting Services,2007.TELSIKS 2007.8th International Conference on.IEEE,2007:261-270.
⑻Kanj R,Li T,Joshi R,et al.Accelerated statistical simulation via on-demand Hermite spline interpolations[C]//Computer-Aided Design(ICCAD),2011 IEEE/ACM International Conference on.IEEE,2011:353-360.
⑼Emrah Acar,Damir Jamsek,et al.Blended model interpolation: U.S.Patent 8,151,230[P].2012-4-3.
⑽Gang Peter Fang,et al.Method for generating and evaluating a table model for circuit simulation:U.S.Patent 8,341,566[P].2012-12-25.
⑾Shima T,Sugawara T,Moriyama S,et al.Three-dimensional table look-up MOSFET model for precise circuit simulation[J].Solid-State Circuits,IEEE Journal of,1982,17(3):449-454.
⑿Jiying X,Tao L,Zhiping Y.Accurate and fast table look-up models for leakage current analysis in 65 nm CMOS technology[J].Journal of Semiconductors,2009,30(2):024004.
⒀Fang G P,Yeh D C,et al.Fast,accurate MOS table model for circuit simulation using an unstructured grid and preserving monotonicity[C]// Proceedings of the 2005 Asia and South Pacific Design Automation Conference.ACM,2005:1102-1106.
⒁Kiran Kumar Gullapalli,et al.Circuit Simulation acceleration using model caching:U.S.Patent 2013/0054217[P].2013-2-28.
⒂Subramaniam P.Modeling MOS VLSI circuits for transient analysis[J] .Solid-State Circuits,IEEE Journal of,1986,21(2):276-285.
(16)Lewis D M.Device model approximation using 2N trees[J].Computer- Aided Design of Integrated Circuits and Systems,IEEE Transactions on,1990,9 (1):30-38.
⒄Gondro E,Kowarik O,Knoblinger G,et al.When do we need non- quasistatic CMOS RF-models[C]//Custom Integrated Circuits,2001,IEEE Conference on.IEEE,2001:377-380.
⒅Ng A F L,Ko P K,Chan M.Determining the onset frequency of nonquasistatic effects of the MOSFET in AC simulation[J].Electron Device Letters,IEEE,2002,23(1):37-39.
⒆Schrom G,Stach A,Selberherr S.An interpolation based MOSFET model for low-voltage applications[J].Microelectronics journal,1998,29(8):529-534
Invention content
Present invention aim to address the non-homogeneous nets for being currently based on " tree-shaped " structural model approximation method (TBMA) structure The slow problem of grid cell search speed in lattice Table Model provides a kind of transistor (MOSFET) for integrated circuit simulating The modeling of accurate table lookup model and estimation method.The present invention can realize in non-uniform grid model not by the scale of division limit The quick form lookup method of system and the advantage that TBMA is adaptively divided is inherited, while ensureing established transistor Table Model The monotonicity for the continuity and interpolation that valuation calculates, it is proposed that corresponding Table Model is established and estimation method.
In order to achieve the above object, technology contents of the invention are:
This method is reflected by establishing the non-uniform grid Table Model of transistor in nonlinear circuit by simple Hash Wait estimating the quick valuation searched and its correspond to physical parameter a little in the look-up tables'implementation simulation process penetrated and assisted.
Transistor physics are adaptively built according to preset required precision by binary space cut tree in the present invention The non-uniform grid model of parameter (electric current, charge), refinement, which divides, converts tree-shaped grid cell storage organization to multidimensional number The grid cell storage organization of group, the non-uniform grid refined is to ensure the continuity and list of Table Model valuation calculating Tonality;
It is non-homogeneous to the key idea that grid cell is searched needed for physical parameter valuation in non-uniform grid By the look-up table of uniform scale structure auxiliary in each dimension of grid;List item will be searched and be mapped as the grid list in respective dimensions First subscript can lead to and wait estimating a little that the simple Hash mapping of coordinate components determines under its grid in the dimension in the dimension Mark;Compared to TBMA, this method can significantly improve the search speed of grid cell in non-uniform grid Table Model, treat and estimate a little The time complexity of lookup falls to O (C) by O (logN), and its search speed is unrelated with grid scale, so as to not Under the premise of sacrificing search speed, the granularity of division of non-uniform grid is improved to obtain the higher Table Model of precision.
The approximation that can be used for arbitrary N-dimensional (N >=2) analytic modell analytical model on theoretical method proposed by the present invention, in addition to the present invention Two and three dimensions Table Model in the BSIM3 of realization can also be other devices (such as three-dimension device, bipolar transistor etc.) The Table Model of dimension needed for establishing.
Specifically, modeling and the estimation method of the accurate table lookup model of transistor of the present invention are it is characterized in that, it is wrapped Include step:
Step 1:The N-dimensional closing of a given device physics parameter function defines domain space, the structure on this definition domain space Binary space cut tree (BSPtree) is built, it is fixed to N-dimensional according to preset error threshold and the physical parameter functional value of parsing Adopted domain space is divided and records the division points in each dimension;
Step 2:The division space that refinement step one obtains, if the number of division points is respectively n in N number of dimension1, n2..., nN, it is (n by the division points structure scale of step 1 record1-1)×(n2- 1) N-dimensional non-uniform grid (non- Uniform grid), each unit (Cell) of grid represents the division space after fining;
Step 3:N number of look-up table (one-dimension array) is built respectively for subscript of the N-dimensional non-uniform grid in N number of dimension, often It is (spaced far long less than minimum boundary of all grid cells in the dimension that one look-up table corresponds to an evenly spaced scale Degree), it searches entry number and is determined by preset granularity;
Step 4:When defining the progress valuation of a coordinate points in domain space to N-dimensional, first by the coordinate in N number of dimension On component be mapped in N number of look-up table of step 3 structure, obtain the division space comprising the coordinate points in N number of dimension Grid subscript, then corresponding grid unit is accessed by grid subscript, it is finally treated in the grid cell and coordinate points is asked to carry out three Secondary interpolation obtains its functional value and its approximate partial differential value in N number of dimension.
In the present invention, step 1, each node (BSP node) in the cut tree of binary space defines domain space with N-dimensional In each divide region (convex space) and correspond, this data structure is used to store the corresponding related top for dividing region The approximate partial differential value (finite-difference approximation) of analytical function value, boundary and a chimb midpoint.
In step 2 of the present invention, the unit of N-dimensional grid and the node data structure having the same of binary space cut tree; Grid cell corresponding to the constant division region in boundary before and after fining can be replicated directly corresponding in binary segmentation tree Node, if boundary changes, the data member needs in grid cell recalculate.
In step 3 of the present invention, for grid cell boundary is no in each dimension and it corresponds to what scale " scale " was aligned Place, removable net boundary are aligned scale to ensure that correct lookup near net boundary accesses.
In step 4 of the present invention, the subscript of look-up table is the Hash mapping of coordinate components, and the hash function is by rod interval Simple to determine, look-up table subscript can be obtained by bringing given coordinate components into the hash function, the corresponding look-up table of the subscript The value of item is the grid subscript in respective dimensions.
It, can be with fixed function when given N-dimensional physical parameter function changes slower in some dimension in the present invention Coordinate components in the dimension, first by the non-uniform grid of above-mentioned step one, two structure N-1 dimensions, then in the dimension Taken on degree sparse and uniform coordinate interval withDimension table lattice be template build N-dimensional table, search and estimation method and The subsequent step of above-mentioned steps is identical.
This method can reduce the storage overhead of table, and improve search speed of the table in the dimension.
For the simplicity of elaboration, method proposed by the invention, higher will be further described based on two-dimensional table below The table construction method of dimension similar can be deduced.
The modeling of the accurate Table Model of transistor proposed by the present invention and estimation method flow can indicate with Fig. 1, with For binary function f (x0,x1) indicate physical parameter structure table for (two dimension divide space in grid cell such as Fig. 2 institutes Show), its step are as follows:
Step 1:BSP tree is spatially built in the binary function domain, according to preset error threshold and parsing The physical parameter functional value obtained in model to two dimension definition domain space divide and records x respectively0、x1Drawing in dimension Branch;
The adaptive division rule for continuing to use binary space cut tree in TBMA (indicates entire domain from the root node of tree Space) start, the partition dimension that the judgment of error criterion of grid cell determines is corresponded to according to it, it is recursively that tree node is corresponding Space chimb midpoint in the dimension is divided into two sub-spaces and corresponds to two newly-generated child nodes respectively, when grid cell When granularity meets error criterion and need not be divided, the corresponding node of the grid cell becomes leaf node;
The judgment of error criterion of two-dimensional grid unit is:
1. calculating separately grid cell x by formula (1) (2)0、x1The value and parsing that dimension chimb midpoint linear interpolation obtains Average value diffx of the value absolute value of the difference obtained in model in respective dimensions dimension0、diffx1Respectively as x0、x1Dimension On error measure value,
2. as max (diffx0,diffx1) > error (xi) (i ∈ { 0,1 }) set up when stop divide, otherwise along xiPlace Dimension divides the grid, xiIt is the dimension corresponding to worst error measurement value, error_tol (xi) indicated by following formula.
Based on this criteria for classifying, the non-linear stronger region of function will be approximate by the smaller division space of granularity, and for The linear region of approximation to function, the larger division space of granularity are just sufficient for required precision;
Step 2:The division space that refinement step 1 obtains, if x0、x1The number of division points is respectively n in dimension1、n2, The division points structure scale recorded by step 1 is (n1-1)×(n2- 1) two-dimentional non-uniform grid;
In the present invention, fining mesh generation space is to ensure the monotonicity and continuity of interpolation, the two attributes There is vital influence on the convergence of Newton method and robustness;
In the present invention, Fig. 3 gives one and typically refines the division sky that BSP tree is established in two-dimensional function domain Between process, fining divide before, function in point (0.5,0.5) interpolation its result will by used grid cell (A or B influence), if using grid cell A, function interpolationTo be:
And grid cell B is used, function interpolationTo be:
If the function interpolation obtained by formula (4) (5)It is different, function will be caused in grid cell A, B boundaries on either side The discontinuity of interpolation, and refine after grid (as shown in the lower half portion of Fig. 3) due to got through boundary intersection (0.5, 0.5) so that boundary having the same between adjacent grid cell, the interpolation result at (0.5,0.5)Always meet (6) formula, It can thus ensure the continuity in boundaries on either side table interpolation;With document the difference is that newly generated grid cell (B, D, E, F) vertex (0.75,0.5) use f (0.75,0.5) and non-linear interpolationAs its functional value, It can naturally ensure table linear interpolation and binary function f (x0,x1) monotonicity having the same;
Step 3:It is two-dimentional non-uniform grid in x0、x1Subscript in dimension builds 2 assisted lookup table array_ respectively 1d, array_2d, each look-up table correspond to an interval (gapiI=0,1) uniform scale searches entry number by advance The granularity of setting determines;
In the present invention, Fig. 4 is the example that assisted lookup table is established for grid in Fig. 3, for larger grid, Scale may have and scale cannot can be aligned with mobile grid elementary boundary, as long as rod interval is sufficient with the position of boundary alignment Enough small, the movement on boundary will be very small, and the influence to dividing space can be ignored;
Step 4:If two dimension defines domain space in x0、x1Lower boundary in dimension is b0、b1, to defining in domain space One coordinate points (x0,x1) carry out valuation when, first by the coordinate in x0、x1Component in dimension is mapped as above-mentioned by formula (7) Subscript in two assisted lookup tables that step 3 is built obtains the division space comprising the coordinate points in x0、x1Net in dimension Lattice subscript (indexiI=0,1), then by (array_1d[index0],array_2d[index1]) corresponding grid list is accessed Member, finally treated in the grid cell ask coordinate points by formula (8) carry out bicubic interpolation obtain its functional value and its in x0、 x1Approximate partial differential value in dimension,
indexi=(xi-bi)/gapiI=0,1 (7)
t≡(x0-x00)/(x01-x00),u≡(x1-x10)/(x11-x10)
Coefficient c in bicubic interpolationijPass through functional value, first derivative values and the second order mixing on fitted mesh difference scheme unit vertex Derivative is worth to, these derivative values can be provided by finite-difference approximation, and calculated interpolation coefficient is then stored in grid list In member;
In the present invention, the finite-difference approximation on non-uniform grid cannot use simple centered difference mode, and should adopt Three point approximations provided with formula (9), wherein xi、xi-1、xi+1Non-uniform grid respectively in given dimension three it is adjacent Point, the calculating for second order mixed derivative then need nine consecutive points (as shown in Figure 5) on 2 × 2 two-dimensional grids, first in x1 In dimension by formula (8) find out respectively a little 1., 2., 3. first derivative values in the dimension, then these three first derivative values are made For x0Three functional values in dimension bring the second order mixed derivative value that formula (8) finds out interpolation point into,
h1≡xi-xi-1,h2≡xi+1-xi
Though refining the continuity that the interpolation in tree model can guarantee functional value in document, it can not ensure derivative The continuity of value;And convert tree to non-uniform grid in the present invention and cubic interpolation is made to become feasible, cubic interpolation It can ensure the continuity of derivative interpolation and the flatness of functional value, thus, this method makes Newton iteration solve non-linear side The robustness of journey is improved.
Compared with the prior art, contribution of the invention is:
The present invention is realized non-homogeneous to the fining built based on BSP tree using assisted lookup table and simple Hash mapping Grid is not by the constant time complexity lookup mode for dividing size limit.Present invention employs Hermite spline interpolations three times Method, can not only ensure electric current, charge first derivative continuity, and the precision of its interpolation is higher, flatness is good, reaches Table scale needed for same precision than using the method for linear interpolation small in same tableau format, thus can offset by Tree is converted to the extra storage expense that lengths are come, and compared with cubic natural spline interpolation, Hermite spline interpolations need The derivative value information being additionally provided on mesh point, interpolation precision is influenced by the precision of the derivative value provided, and function interpolation Flatness is then unrelated with derivative value precision, simultaneously because it only needs the function information near grid cell where providing point to be inserted, Hermite spline interpolations are the interpolation methods of a part;This property has when it being made to be generalized to interpolation in hyperspace Higher computational efficiency.If precalculated interpolation coefficient, and quick grid cell lookup method above is combined, Interpolation is only constant time complexity and unrelated with grid scale in arbitrary hyperspace.And natural spline interpolation is global interpolation Method, the complexity for solving interpolation coefficient are higher.The upper natural spline interpolation that carries out then needs M+1 times one in the two-dimensional grid of M × N Natural spline interpolation is tieed up, computation complexity is excessively high.
This method inherits the advantage adaptively divided based on tree shaped model approximation method, solves and is currently based on tree-shaped knot The slow problem of unit (Cell) search speed in the non-uniform grid model of structure.Through the experimental results showed that this method can be substantially speeded up Transistor model calculating process in simulation process, with acceptable memory requirements effectively shorten transient analysis in circuit simulation when Between and obtain higher precision.
Description of the drawings
Fig. 1 is modeling and the estimation method flow chart of the accurate table lookup model of transistor.
Fig. 2 is binary function f (x0,x1) two dimension divide space in grid cell schematic diagram.
Fig. 3 is a process that the division space that BSP tree is established typically is refined in two-dimensional function domain.
Fig. 4 is to divide the schematic diagram that the non-uniform grid in space establishes assisted lookup table for two dimension.
Fig. 5 is the approximate schemes of the second order mixed derivative on the non-uniform grid during two dimension divides space.
Fig. 6 and Fig. 7 is drain-source conductance plots and transconductance curve respectively.
Specific implementation mode
Embodiment 1
Based on the method for the present invention, the present embodiment is that BSIM3 constructs approximate Table Model, respectively DC current Ids、 IsubThree-dimensional table is built to portray the I-V characteristic of transistor;For intrinsic charge QG、QB、QDThree-dimensional table is built to portray crystal Pipe Q-V characteristics (build charge model, bibliography (17) (18) shows QSA foots in the present invention using quasistatic approximation (QSA) To meet the needs of in most of practical applications), model rest part include source-and-drain junction diode current, capacitance, charge and Extrinsic charge is directly calculated by analytic formula, and the parasitic diode model of parsing is used only to need as dimensioning in circuit Very little different transistor builds independent Table Model, without building additional table because of the difference of source and drain junction area and perimeter Lattice can effectively reduce the table number built in circuit simulation (especially circuit post-simulation);
Due to drain-source current IdsIndex behavior in subthreshold region, need for it build three-dimensional table scale usually compared with Greatly, it is therefore necessary to further compress its storage overhead, IdsValue depend on the differences of four ports of transistor, i.e. gate source voltage Vgs, drain-source voltage Vds, Substrate bias voltage Vbs, wherein substrate bias mainly influences the threshold voltage V of transistorth, and notice IdsMainly by Vgs-VthInfluence rather than two separate influences of variable here, bibliography (11) is pointed out can be by Ids (Vgst,Vds,Vbs) replace Ids(Vgs,Vds,Vbs) build three-dimensional table, wherein Vgst=Vgs-Vth(Vbs,Vds), and prove at this The lower I of kind conversiondsIn VbsVariation in dimension is much smaller than other two dimensions, based on the considerations of to search speed and interpolation efficiency, Different from the method that documents (11) build multiple two-dimensional tables, the present invention is primarily based on Ids(Vgst,Vds,Vbs=0) by Fig. 1 Shown in Step 1: the two two-dimensional non-uniform grids of structure, then in VbsTake uniform interval true with the two-dimensional grid in dimension Vertical granularity of division is that template builds three-dimensional table Ids(Vgs,Vds,Vbs), according to aforementioned principles, in VbsNeeded in dimension Grid dimension can more other two dimensions it is sparse, in addition also need structure one to threshold voltage carry out valuation aided two-dimensional table Lattice Vth(Vbs,Vds), the storage size of this table usually can accurately estimate threshold voltage in tens mesh points or so Value, thus it is based on this mode, three-dimensional grid I can be effectively reduceddsStorage overhead.This table scale compression mode It is equally applicable to the simplification of charge table;
It, can be in grid cell where point to be inserted by twice double three in sparse three-dimensional table when interpolation in the present embodiment Secondary interpolation (corresponds respectively to grid cell VbsBiasing corresponding to dimension up-and-down boundary) combine VbsOnce linear in dimension is inserted Value or the one-dimensional spline interpolations of Hermite three times obtain required electric current or charge value;
In order to assess various interpolation methods, Can Kaowenxian [19]In give one kind can be very good characterization drain-source The analytical function of electric current feature in each working region, shown in the function such as formula (10), to verify the correct of the method for the present invention Property is simultaneously compared with tree model method, is built two-dimensional table approximate model as test function using it, is taken Vth =0.5V, λ=1/100V, and choose 0≤VDS≤5V、0≤VGS≤ 5V defines domain space as two-dimensional function,
Table 1 gives at voltage scanning step-length 5mV, using tree model (using linear interpolation) and side of the present invention Method (using bicubic interpolation) builds the scale and interpolation precision of table approximate model, the statistics of storage overhead for test function Rule is to need 4 floating number storage vertex function values based on each unit in tree model, and each unit of this method is then Need 16 floating numbers to store interpolation coefficients, in addition they all also need 4 floating number stored boundary information, shown in table 1 the results show that Interpolation precision mutually instantly, the storage overhead of this method table is about twice smaller than the tree model method of the prior art.
1 approximate model scale of table and accuracy comparison
In the present embodiment, in order to observe the interpolation situation of first derivative, drain-source conductance is had recorded respectively under different voltages With the approximate model interpolation calculation value and parsing calculated value of mutual conductance, curve as shown in Figure 6 and Figure 7 is drawn, which show lines Property the obtained first derivative of interpolation it is stepped, be discontinuous, and the first derivative that bicubic interpolation obtains it is not only continuous and Interpolation smoothing is preferable, this is because bicubic interpolation can ensure the continuity of first derivative and second order mixed derivative simultaneously, And whether the continuity and flatness of interpolation can restrain Newton iteration, convergence rate has an important influence on.
In the present embodiment, the table approximate model for being based further on BSIM3 realizations has been carried out in circuit emulator, Table is built before emulation starts each time, precomputes the interpolation coefficient in grid cell, and the table before emulation starts is established Time can usually complete in a few seconds, can ignore compared to circuit entirety simulation time, for comprising 468 transistors The memory overhead of phase-locked loop circuit, average each crystal is about 580KB, it can be seen that this method for complicated analog circuit its Memory consumption is acceptable;The present invention has carried out emulation to verify this method to multiple technical grade circuits (Level49) Simulation efficiency and precision, to transistor current, the calculating process of charge, there are about the acceleration of 3x~4x, and to circuit transient analysis Acceleration efficiency then depends on time loss that transistor model calculates ratio shared in entire emulation;Table 2 gives three kinds The simulation accuracy and transient analysis acceleration efficiency of typical circuit are simultaneously compared with the FineSim softwares of Synopsys companies, The relative error of wherein phaselocked loop refers respectively to the error of burning voltage and locking frequency, and other two circuits are then to be based on wave The relative error of shape;Wherein the simulation result of FineSim be under spice1 simulation accuracies using Model 3 (analytic modell analytical model) and Two kinds of transistor models of Model 2 (approximate model) obtain.
2 Transient results contrast of table

Claims (7)

1. modeling and the estimation method of a kind of accurate table lookup model of transistor, which is characterized in that it includes step:
Step 1:The N-dimensional closing of a given device physics parameter function defines domain space, and two are built on this definition domain space First space cut tree (BSPtree), according to preset error threshold and the physical parameter functional value of parsing to N-dimensional domain Space is divided and records the division points in each dimension;
Step 2:The division space that refinement step one obtains, if the number of division points is respectively n in N number of dimension1, n2..., nN, it is (n by the division points structure scale of step 1 record1-1)×(n2-1)×…×(nN- 1) N-dimensional non-uniform grid (non-uniform grid), each unit (Cell) of grid represent the division space after fining;
Step 3:N number of look-up table is built respectively for subscript of the N-dimensional non-uniform grid in N number of dimension, each look-up table corresponds to One evenly spaced scale is searched entry number and is determined by preset granularity;
Step 4:When defining the progress valuation of a coordinate points in domain space to N-dimensional, first by the coordinate in N number of dimension Component is mapped in N number of look-up table of step 3 structure, obtains grid of the division space comprising the coordinate points in N number of dimension Subscript, then corresponding grid unit is accessed by grid subscript, it is finally treated in the grid cell and coordinate points is asked to be inserted three times It is worth to its functional value and its approximate partial differential value in N number of dimension.
2. method as described in claim 1, which is characterized in that each in the cut tree of binary space in the step one A node (BSP node) defines each division region in domain space with N-dimensional and corresponds.
3. method as described in claim 1, which is characterized in that in the step two, unit and the binary space of N-dimensional grid The node data structure having the same of cut tree;For the grid list divided corresponding to region that boundary before and after fining is constant Member can directly replicate the corresponding node in binary segmentation tree, if boundary changes, the data member in grid cell needs It recalculates.
4. method as described in claim 1, which is characterized in that in the step three, for the grid cell in each dimension Boundary is aligned scale to ensure in Grid Edge without corresponding to the place that scale " scale " is aligned with it by mobile grid boundary Correct lookup near boundary accesses.
5. method as described in claim 1, which is characterized in that in the step three, the look-up table is one-dimension array; Each described look-up table corresponds to its interval of evenly spaced scale and is much smaller than all grid cells in the dimension Minimum boundary length.
6. method as described in claim 1, which is characterized in that in the step four, the grid subscript in look-up table is to sit The Hash mapping of component is marked, which is simply determined by rod interval, brings given coordinate components into the Hash mapping It can obtain the grid subscript in respective dimensions.
7. method as described in claim 1, which is characterized in that when given N-dimensional physical parameter function is in some dimension When variation is slower, coordinate components of the fixed function in the dimension, in remaining N|1 dimension structure non-uniform grid comprising:It is first First by the step one in claim 1, two structure N|The non-uniform grid of 1 dimension, then takes in the slower dimension of the variation sparse And uniform coordinate interval, with remaining N|1 dimension table lattice are that template builds N-dimensional table, are then searched and valuation side in the dimension Method is identical as the subsequent step in claim 1.
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