CN104978447B - The modeling of the accurate table lookup model of transistor and estimation method - Google Patents

Abstract

This method belongs to integrated circuit fields, is related to a kind of the transistor accurately modeling of approximate table lookup model and estimation method.By establishing the non-uniform grid Table Model of transistor in nonlinear circuit, by the quick valuation searched and its correspond to physical parameter for waiting estimating in the look-up tables'implementation simulation process of simple Hash mapping and auxiliary a little.This method inherits the advantage adaptively divided based on tree shaped model approximation method, and it is slow to solve the problems, such as to be currently based on unit search speed in the non-uniform grid model of tree.The continuity and flatness for ensureing that Table Model calculates by carrying out Hermite spline interpolations three times on non-uniform grid, overcome the problem of derivative discontinuously leads to convergence difficulties in the prior art, this method can substantially speed up transistor model calculating process in simulation process, effectively shortened in circuit simulation with acceptable memory requirements and the time of transient analysis and obtain higher precision.

Description

Modeling and Estimation Methods for Exact Table Lookup Models of Transistors

technical field

The method belongs to the field of integrated circuits, and in particular relates to a method for modeling and estimating an accurate table lookup model of a transistor (MOSFET) used for integrated circuit simulation.

technical background

As the complexity of Ultra Large Scale Integration (ULSI) increases, fast simulation and verification becomes increasingly important in the design flow. Studies have shown that traditional fast transistor-level simulation (fast-spice) often gains significant gains in simulation speed at the expense of accuracy, and is widely used in the verification of large-scale digital circuits and the functional simulation of digital-analog hybrid circuits. However, with the sharp reduction of process feature size, in order to accurately describe the deep submicron characteristics of transistors, modern transistor-level simulators often use complex transistor analysis models, such as BSIM and EKV, which makes it difficult for traditional fast simulation methods to meet the accuracy requirements Simulation of higher analog circuits, standard cell libraries and IP cores.

Table model technology usually describes the input and output characteristics of the device (mainly including I-V and Q-V characteristics) by constructing a series of multi-dimensional tables from the finite device operating points obtained from the transistor analytical model. Properly selecting the fineness of the table construction and combining with a reasonable interpolation method, the table model can approximate the behavior characteristics of the transistor in the simulation, and has been successfully applied to the memory yield analysis (8) and transistor leakage analysis that require high precision.

The prior art discloses that in transistor-level simulation, the main process of transient analysis is to estimate the voltage and current values of all nodes of the circuit at a given time point, and extrapolate the values of the circuit nodes at the next time point. Modern transistor-level simulators generally use the Newton-Raphson method to iteratively solve the implicit or explicit integral equations of the circuit at the current time point to obtain the voltage and current values of the circuit nodes at the next time point, and repeat this process recursively until the simulation ends. Due to the inherent high nonlinear characteristics of modern transistor devices, Newton iteration generally needs multiple steps to converge at each time point, and each Newton iteration will call the transistor model to estimate the operating point of the device, so in the transient analysis Valuation of highly complex transistor models is a time-consuming process. It is pointed out that for highly complex circuits, nearly 60%-80% of the time in transient analysis is used for the estimation calculation of the transistor analytical model, so using a reasonable tabular model to approximate and simplify the estimation calculation of the physical parameters of the transistor can effectively shorten the simulation of the circuit time.

Based on the above two points, the tabular model technology can simultaneously obtain the acceleration of the simulation process and acceptable simulation accuracy. In practice, the difficulty in implementing the tabular model technology lies in how to strike a balance between model accuracy, tabular scale, and efficient interpolation calculations and ensure that the estimated Compatibility between value calculation and Newton iterative solution of circuit equations (mainly including monotonicity and continuity of interpolation).

Due to the use of a uniform grid in the early form models of the prior art, the accuracy of the model is often limited by the storage requirements of the huge form size (especially the 3D grid) and requires the use of complex interpolation methods to obtain sufficient estimates precision. With the significant increase in the transistor scale and the complexity of the physical model in circuit simulation, the method of constructing tables by non-uniform grids is widely used. By placing more grid points in the region where the transistor nonlinearity is strong, it can be relatively Smaller memory requirements more accurately characterize the nonlinear behavior of transistor physical parameters. Compared with the method in the prior art that semi-empirically establishes division rules and constructs a structured grid based on the working area of the transistor, some studies have proposed a method that can automatically A method for adaptively constructing tables, wherein an unstructured grid based on a tree structure is used to further reduce storage overhead, such as, adopting this method to construct a table model for SOI; further improving and developing the above method to ensure The monotonicity of interpolation; however, compared with the structured grid, the unstructured grid needs to use complex algorithms to ensure the monotonicity and continuity of the interpolation of the tabular model, which leads to an increase in the time spent on building the table before simulation. One disadvantage is that the search speed (time complexity of O(log N)) of the grid unit (Cell) in the tree structure is relatively slow, especially when the depth of the corresponding node of the required grid unit is relatively deep, in the estimation calculation The proportion of search time will increase significantly. In the prior art, greedy search and path compression methods are used to shorten the search time. Because in areas with strong nonlinearity, the grid cells required for estimation calculation often correspond to For the deeper leaf nodes in the tree, the nodes corresponding to the two spatially adjacent grid units have a high probability of being located in two different deeper subtrees of the binary space partitioning (BSP) tree, thus The method therein has limited improvement in search speed, or brings additional overhead due to iterative conversion between data structures.

To sum up, it is difficult for the method of constructing non-uniform grids in the prior art table model technology to ensure the versatility, simplicity and efficiency of constructing tables at the same time.

The prior art relevant to the present invention has following references:

(1) Rewieński, "A perspective on fast-SPICE simulation technology."Simulation and Verification of Electronic and Biological Systems. SpringerNetherlands, 2011.23-42.

(2) Y.S.Chauhan, S.Venugopalan, M.A.Karim, S.Khandelwal, N.Paydavosi, P.Thakur, A.M.Niknejad and C.C.Hu, “BSIM–industry standard compact MOSFETmodels”, IEEE European Solid-State Device Research Conference, Bordeaux , France, Sept.2012.

⑶Bucher M, Enz C, Krummenacher F, et al. The EKV 3.0 compact MOStransistor model: accounting for deep-submicron aspects[C]//Proc.MSMInt.Conf., Nanotech 2002.2002:670-673.

⑷Nadezhin D, Gavrilov S, Glebov A, et al.SOI transistor model for fasttransient simulation[C]//Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design.IEEE Computer Society,2003:120.

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⑺Caddemi A, Crupi G, et al..Analytical Construction of Nonlinear Lookup Table Model for Advanced Microwave Transistors[C]//Telecommunications in Modern Satellite,Cable and Broadcasting Services,2007.TELSIKS 2007.8thInternational Conference on.IEEE,2007:261-270.

⑻Kanj R, Li T, Joshi R, et al.Accelerated statistical simulation viaon-demand Hermite spline interpolations[C]//Computer-Aided Design(ICCAD),2011IEEE/ACM International Conference on.IEEE,2011:353-360.

⑼Emrah Acar, Damir Jamsek, et al. Blended model interpolation: U.S. Patent 8,151,230[P].2012-4-3.

⑽Gang Peter Fang, et al.Method for generating and evaluating a tablemodel for circuit simulation: U.S.Patent 8,341,566[P].2012-12-25.

⑾Shima T, Sugawara T, Moriyama S, et al.Three-dimensional table look-upMOSFET model for precise circuit simulation[J].Solid-State Circuits,IEEEJournal of,1982,17(3):449-454.

⑿Jiying X,Tao L,Zhiping Y.Accurate and fast table look-up models for leakage current analysis in 65 nm CMOS technology[J].Journal of Semiconductors,2009,30(2):024004.

⒀Fang G P, Yeh D C, et al. Fast, accurate MOS table model for circuits simulation using an unstructured grid and preserving monotonicity[C]//Proceedings of the 2005 Asia and South Pacific Design Automation Conference. ACM,2005:1102-1106.

⒁Kiran Kumar Gullapalli, et al. Circuit Simulation acceleration using model caching: U.S. Patent 2013/0054217[P].2013-2-28.

⒂Subramaniam P.Modeling MOS VLSI circuits for transient analysis[J].Solid-State Circuits,IEEE Journal of,1986,21(2):276-285.

(16) Lewis D M. Device model approximation using 2 ^N trees [J]. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 1990, 9(1): 30-38.

⒄Gondro E, Kowarik O, Knoblinger G, et al. When do we need non-quasistatic CMOS RF-models? [C]//Custom Integrated Circuits, 2001, IEEE Conference on. IEEE, 2001:377-380.

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⒆Schrom G, Stach A, Selberherr S.An interpolation based MOSFET model for low-voltage applications[J].Microelectronics journal,1998,29(8):529-534

Contents of the invention

The purpose of the present invention is to solve the problem that the grid unit search speed is slow in the non-uniform grid table model built based on the "tree-like" structure model approximation method (TBMA), and to provide a transistor (MOSFET) for integrated circuit simulation Modeling and Valuation Methods for Exact Table Lookup Models. The invention can realize the fast table lookup method not limited by the division scale in the non-uniform grid model and inherits the advantages of TBMA self-adaptive division, and at the same time ensures the continuity of the evaluation calculation of the established transistor table model and the monotonicity of the interpolation, The corresponding tabular model building and valuation methods are proposed.

In order to achieve the above object, technical content of the present invention is:

This method establishes a non-uniform grid table model of transistors in a nonlinear circuit, and realizes the rapid search of the points to be estimated and the estimation of the corresponding physical parameters in the simulation process by means of a simple hash map and an auxiliary look-up table.

In the present invention, the non-uniform grid model of transistor physical parameters (current, charge) is adaptively constructed by the binary space segmentation tree according to the preset precision requirements, and the tree-like grid unit storage structure is converted into multi-dimensional by adding fine division Array grid unit storage structure, to obtain a refined non-uniform grid to ensure the continuity and monotonicity of the tabular model estimation calculation;

The key idea of looking up the grid cells required for the estimation of physical parameters in the non-uniform grid is to construct an auxiliary look-up table with a uniform scale on each dimension of the non-uniform grid; map the look-up table items to the corresponding dimensions The grid unit subscript of a point to be estimated can be determined by a simple hash map of the coordinate components in this dimension; compared with TBMA, this method can significantly improve the efficiency of non-uniform grids. The search speed of the grid unit in the tabular model, the time complexity of the search point to be estimated is reduced from O(logN) to O(C), and its search speed has nothing to do with the grid size, so that it can be obtained without sacrificing the search speed , improve the division granularity of the non-uniform grid to obtain a tabular model with higher accuracy.

The method that the present invention proposes can be used for the approximation of any N-dimensional (N≥2) analytical model in theory, except the two-dimensional and three-dimensional form model in the BSIM3 that the present invention realizes, can also be other devices (as three-dimensional device, bipolar type transistors, etc.) to create a tabular model of the required dimensions.

Specifically, the modeling and estimating method of the transistor accurate table lookup model of the present invention is characterized in that it includes the steps of:

Step 1: Given an N-dimensional closed domain space of the device physical parameter function, construct a binary space partition tree (BSPtree) on the domain space, and pair N Divide the dimension domain space and record the division points on each dimension;

Step 2: refine the division space obtained in step 1, set the number of division points in N dimensions as n ₁ , n ₂ ,..., n _N , and the scale of division points recorded in step 1 is (n ₁ -1) ×(n ₂ -1) N-dimensional non-uniform grid (non-uniform grid), each cell (Cell) of the grid represents the refined division space;

Step 3: Construct N lookup tables (one-dimensional arrays) for the subscripts of N-dimensional non-uniform grids in N dimensions, and each lookup table corresponds to a uniformly spaced scale (the interval is much smaller than that of all grid cells in this The minimum boundary length on the dimension), the number of lookup table items is determined by the preset granularity value;

Step 4: When evaluating a coordinate point in the N-dimensional domain space, first map the components of the coordinate in N dimensions to the N lookup tables constructed in Step 3, and obtain the divided space containing the coordinate point The grid subscripts in N dimensions, and then access the corresponding grid unit by the grid subscripts, and finally perform cubic interpolation on the coordinate point in the grid unit to obtain its function value and its approximate deviation in N dimensions differential value.

In the present invention, in step 1, each node (BSP node) in the binary space partition tree is in one-to-one correspondence with each division area (convex space) in the N-dimensional domain space, and this data structure is used to store the corresponding division The values of the analytic functions for the associated vertices of the region, the boundaries, and the approximate partial differential values for the midpoints of the convex edges (finite difference approximation).

In the second step of the present invention, the unit of the N-dimensional grid has the same data structure as the node of the binary space segmentation tree; the binary segmentation tree can be directly copied for the grid unit corresponding to the division area whose boundary remains unchanged before and after refinement For the corresponding nodes in , if the boundaries change, the data members in the grid cells need to be recalculated.

In Step 3 of the present invention, for places where the grid unit boundary is not aligned with its corresponding scale "scale" in each dimension, the grid boundary can be moved to align the scale to ensure correct search and access near the grid boundary.

In step 4 of the present invention, the subscript of the lookup table is the hash map of the coordinate components, the hash function is simply determined by the scale interval, and the given coordinate component is brought into the hash function to obtain the lookup table subscript, the The value of the lookup table item corresponding to the subscript is the grid subscript on the corresponding dimension.

In the present invention, when the given N-dimensional physical parameter function changes slowly on a certain dimension, the coordinate component of the function on this dimension can be fixed, and the N-1-dimensional non- Uniform grid, and then take sparse and uniform coordinate intervals in this dimension to Dimensional tables are used as templates to construct N-dimensional tables, and the search and evaluation methods are the same as the subsequent steps of the above steps.

This method can reduce the storage overhead of the table and increase the search speed of the table in this dimension.

For simplicity of explanation, the method proposed by the present invention will be further described below based on a two-dimensional table, and a higher-dimensional table construction method can be deduced similarly.

The flow chart of the modeling and estimation method for the precise tabular model of transistors proposed by the present invention can be represented by Fig. 1, and the physical parameters represented by the binary function f(x ₀ , x ₁ ) are used as an example to construct a table (in two-dimensionally divided space Grid unit shown in Figure 2), the steps are as follows:

Step 1: Build a BSP tree on the binary function domain space, divide the two-dimensional domain space according to the preset error threshold and the physical parameter function values obtained in the analytical model, and record x ₀ and x ₁ respectively The dividing point on the dimension;

Following the self-adaptive division rules of the binary space segmentation tree in TBMA, starting from the root node of the tree (representing the entire definition domain space), according to the division dimension determined by the error evaluation criterion of the corresponding grid unit, recursively divide the tree nodes The corresponding space is equally divided into two subspaces along the midpoint of the convex edge on this dimension, corresponding to the two newly generated child nodes. When the granularity of the grid unit meets the error criterion and no division is required, the node corresponding to the grid unit becomes leaf node;

The error evaluation criteria for two-dimensional grid cells are:

①Use the formula (1)(2) to calculate the average value diffx ₀ of the absolute value of the difference between the value obtained by the linear interpolation of the midpoint of the convex edge of the grid unit x ₀ and x ₁ and the value obtained in the analytical model in the corresponding dimension , diffx ₁ are used as the error measurement values on the dimensions x ₀ and x ₁ respectively,

②When max(diffx ₀ ,diffx ₁ )＞error( _xi )(i∈{0,1}) is established, stop dividing, otherwise divide the grid along the dimension where _xi is located, and _xi is the value corresponding to the maximum error measurement The dimension of error_tol( _xi ) is expressed by the following formula.

Based on this division criterion, the region with stronger nonlinear function will be approximated by the smaller granularity partition space, while for the function approximate linear region, the larger granularity partition space is sufficient to meet the accuracy requirements;

Step 2: Refining the division space obtained in step 1, assuming that the number of division points on dimensions x ₀ and x ₁ are n ₁ and n ₂ respectively, the construction scale of division points recorded in step 1 is (n ₁ -1)×( n ₂ -1) two-dimensional non-uniform grid;

In the present invention, the fine grid division space is to ensure the monotonicity and continuity of the interpolation, and these two properties have a crucial influence on the convergence and robustness of the Newton method;

In the present invention, Fig. 3 has provided a typical process of dividing the space established by refining the BSP tree on the two-dimensional function domain. Before the refining division, the result of the function will be affected by the interpolation at point (0.5,0.5). The effect of using grid unit (A or B), if grid unit A is used, the function interpolates will be:

Instead, using grid cell B, the function interpolates will be:

If the function interpolation obtained by formula (4) (5) are different, which will lead to the discontinuity of interpolation of the function on both sides of the boundary of grid cells A and B, and the refined grid (as shown in the lower part of Fig. 3) has opened up the boundary intersection (0.5, 0.5), so that adjacent grid cells have the same boundary, interpolation results at (0.5,0.5) Formula (6) is always satisfied, so the continuity of table interpolation on both sides of the boundary can be guaranteed; the difference from the literature is that the vertices (0.75, 0.5) of the newly generated grid cells (B, D, E, F) use f(0.75,0.5) instead of linear interpolation As its function value, it can naturally guarantee that the linear interpolation of the table and the binary function f(x ₀ ,x ₁ ) have the same monotonicity;

Step 3: Construct two auxiliary lookup tables array_1d and array_2d respectively for the subscripts of the two-dimensional non-uniform grid on the x ₀ and x ₁ dimensions, and each lookup table corresponds to a uniform interval (gap _i i=0,1) Scale, the number of lookup table items is determined by the preset granularity value;

In the present invention, Fig. 4 is an example of setting up an auxiliary look-up table for the grid in Fig. 3. For larger grids, the scale may have a position that cannot be aligned with the boundary, and the grid cell boundary can be moved to align the scale. If the scale interval is small enough, the movement of the boundary will be very small, and the impact on the division space will be negligible;

Step 4: Let the lower boundaries of the two-dimensional domain space on the dimensions x ₀ and x ₁ be b ₀ and b ₁ , when evaluating a coordinate point (x ₀ , x ₁ ) in the domain space, first Map the components of the coordinates in the x ₀ and x ₁ dimensions from the formula (7) to the subscripts in the two auxiliary lookup tables constructed in the above step 3, and obtain the division space containing the coordinate point in the x ₀ and x ₁ dimensions The grid subscript on (index _i i=0,1), and then access the corresponding grid unit by (array_1d[index ₀ ], array_2d[index ₁ ]), and finally the coordinate point in the grid unit is obtained by the formula (8) Perform bicubic interpolation to obtain its function value and its approximate partial differential value on the x ₀ and x ₁ dimensions,

index _i ＝(x _i -b _i )/gap _i i＝0,1 (7)

t≡(x ₀ -x ₀₀ )/(x ₀₁ -x ₀₀ ), u≡(x ₁ -x ₁₀ )/(x ₁₁ -x ₁₀ )

The coefficient c _ij in bicubic interpolation is obtained by fitting the function value on the vertices of the grid unit, the first order derivative value and the second order mixed derivative value. These derivative values can be approximated by finite differences, and then the calculated interpolation coefficients are stored in in the grid unit;

In the present invention, the finite difference approximation on the non-uniform grid cannot use the simple central difference method, but the three-point approximation method given by formula (9) should be used, where x _i , x _i-1 , and x _i+1 are respectively is the three adjacent points on the given dimension of the non-uniform grid, and for the calculation of the second-order mixed derivative, nine adjacent points on the 2×2 two-dimensional grid are required (as shown in Figure 5), first in Calculate the first-order derivative values of points ①, ②, and ③ on the dimension x ₁ by formula (8), and then bring these three first-order derivative values into the formula as the three function values on the x ₀ dimension (8) Calculate the second-order mixed derivative value of the point to be interpolated,

h ₁ ≡x _i -x _i-1 , h ₂ ≡x _i+1 -x _i

Although the interpolation in the refined tree structure model in the literature can guarantee the continuity of the function value, it cannot guarantee the continuity of the derivative value; and in the present invention, the transformation of the tree structure into a non-uniform grid makes the cubic interpolation feasible, The cubic interpolation can guarantee the continuity of the derivative interpolation and the smoothness of the function value. Therefore, this method improves the robustness of Newton's iterative solution to nonlinear equations.

Compared with prior art, the contribution of the present invention is:

The invention adopts an auxiliary lookup table and a simple hash map to realize a constant time complexity lookup mode that is not limited by the division scale for the refined non-uniform grid constructed based on the BSP tree. The present invention adopts the three-time Hermite spline interpolation method, which not only can ensure the continuity of the current and the first-order derivative of the charge, but also has high interpolation precision and good smoothness, and the scale of the table required to achieve the same precision is larger than that of the same table structure The method of using linear interpolation in the method is small, so it can offset the additional storage overhead brought by the conversion from tree structure to grid. Compared with cubic natural spline interpolation, Hermite spline interpolation needs to provide additional derivative value information on grid points , the interpolation accuracy is affected by the accuracy of the derivative value provided, while the smoothness of function interpolation has nothing to do with the accuracy of the derivative value. At the same time, because it only needs to provide the function information near the grid cell where the point to be interpolated is located, Hermite spline interpolation is a local The interpolation method; this property makes it more computationally efficient when it is extended to interpolation in multi-dimensional space. If the interpolation coefficients are pre-calculated and combined with the above fast grid cell search method, the interpolation in any multi-dimensional space has only constant time complexity and has nothing to do with the grid size. Natural spline interpolation is a global interpolation method, and the complexity of solving interpolation coefficients is relatively high. To perform natural spline interpolation on an M×N two-dimensional grid requires M+1 times of one-dimensional natural spline interpolation, and the computational complexity is too high.

This method inherits the advantages of self-adaptive division based on the tree-like model approximation method, and solves the problem of slow cell (Cell) search speed in the current tree-like structure-based non-uniform grid model. The experimental results show that this method can significantly accelerate the calculation process of the transistor model in the simulation process, effectively shorten the time of transient analysis in circuit simulation with acceptable memory requirements, and obtain higher accuracy.

Description of drawings

Figure 1 is a flow chart of the modeling and estimation method for the exact table lookup model of transistors.

Fig. 2 is a schematic diagram of a grid unit of a binary function f(x ₀ , x ₁ ) in a two-dimensional partition space.

Figure 3 is a typical process of refining the partition space established by the BSP tree on the two-dimensional function domain.

Fig. 4 is a schematic diagram of establishing an auxiliary look-up table for a non-uniform grid in a two-dimensional partition space.

Figure 5 is an approximation scheme for second-order mixed derivatives on a non-uniform grid in a two-dimensional partitioned space.

Figure 6 and Figure 7 are the drain-source conductance curve and transconductance curve respectively.

Detailed ways

Example 1

Based on the method of the present invention, this embodiment constructs an approximate table model for BSIM3, respectively constructing three-dimensional tables for DC current I _ds and I _sub to describe the IV characteristics of transistors; constructing three-dimensional tables for intrinsic charges Q _G , Q _B , and Q _D The table describes the transistor QV characteristics (the quasi-static approximation (QSA) is used to construct the charge model in the present invention, and references (17) (18) show that QSA is sufficient to meet the needs of most practical applications), and the rest of the model includes the source-drain junction Diode current, capacitance, charge, and extrinsic charge are all directly calculated by analytical formulas. Using the analytical parasitic diode model makes it only necessary to build an independent tabular model for transistors with different geometric sizes in the circuit, without the need for source-drain junction area and circumference. The construction of additional tables can effectively reduce the number of tables constructed in circuit simulation (especially post-circuit simulation);

Due to the exponential behavior of the drain-source current I _ds in the subthreshold region, the size of the three-dimensional table that needs to be constructed for it is usually large, so it is necessary to further compress its storage overhead. The value of I _ds depends on the difference between the four ports of the transistor, That is, the gate-source voltage V _gs , the drain-source voltage V _ds , and the substrate bias voltage V _bs , where the substrate bias mainly affects the threshold voltage V _th of the transistor, and it is noted that I _ds is mainly affected by V _gs -V _th In addition to the independent influence of the two variables here, reference (11) pointed out that I _ds (V _gst , V _ds , V _bs ) can be used instead of I _ds (V _gs , V _ds , V _bs ) to construct a three-dimensional table, where V _gst =V _gs -V _th (V _bs , V _ds ), and prove that under this conversion, the change of I _ds in the V _bs dimension is much smaller than the other two dimensions, based on the consideration of search speed and interpolation efficiency, it is different from the comparison Document (11) constructs the method for a plurality of two-dimensional tables, and the present invention is first based on I _ds (V _gst , V _ds , V _bs =0) by steps one and two shown in Figure 1 to construct a two-dimensional non-uniform grid, Then take a uniform interval on the V _bs dimension and use the division granularity established by the two-dimensional grid as a template to construct a three-dimensional table I _ds (V _gs , V _ds , V _bs ). According to the aforementioned principles, it _requires The number of grid points can be sparser than the other two dimensions. In addition, it is necessary to construct an auxiliary two-dimensional table V _th (V _bs , V _ds ) for estimating the threshold voltage. The storage scale of this table is usually dozens of grids The threshold voltage can be accurately estimated by a point or so, so based on this method, the storage overhead of the three-dimensional grid I _ds can be effectively reduced. This table size compression method is also applicable to the simplification of the charge table;

In this embodiment, when interpolating in a sparse three-dimensional table, two bicubic interpolations (corresponding to the offsets corresponding to the upper and lower boundaries of the dimension of the grid unit V _bs respectively) can be combined with V _bs in the grid unit where the point to be interpolated is located. One-dimensional linear interpolation or one-dimensional cubic Hermite spline interpolation to obtain the required current or charge value;

In order to evaluate various interpolation methods, an analytical function that can well characterize the characteristics of the drain-source current in each working area is given in reference [19]. The correctness of the method of the present invention is compared with the tree structure model method, and it is used as a test function to construct a two-dimensional table approximation model, V _th =0.5V, λ=1/100V, and 0≤V _DS ≤5V , 0≤V _GS ≤5V as the two-dimensional function domain space,

Table 1 has provided under voltage scanning step-length 5mV, adopts tree structure model (adopts linear interpolation) and the present invention method (adopts bicubic interpolation) to be the scale and the interpolation precision of test function to build table approximation model, its memory cost The statistical rule is based on the fact that each unit in the tree structure model requires 4 floating-point numbers to store the vertex function value. In this method, each unit needs 16 floating-point numbers to store the interpolation coefficients. In addition, they all need 4 floating-point numbers to store boundary information. The results shown in Table 1 show that, with comparable interpolation accuracy, the table storage cost of this method is about two times smaller than that of the tree structure model method in the prior art.

Table 1 Approximate model scale and accuracy comparison

In this embodiment, in order to observe the interpolation of the first-order derivative, the approximate model interpolation calculation values and analytical calculation values of the drain-source conductance and transconductance were recorded at different voltages, and the curves shown in Figure 6 and Figure 7 were drawn , which shows that the first-order derivative obtained by linear interpolation is stepped and discontinuous, while the first-order derivative obtained by bicubic interpolation is not only continuous but also has better interpolation smoothness, because bicubic interpolation can guarantee the first-order derivative at the same time and the continuity of the second-order mixed derivative, and the continuity and smoothness of the interpolation will have an important impact on whether the Newton iteration converges and the convergence speed.

In this embodiment, the table approximation model further implemented based on BSIM3 has been implemented in the circuit simulator, and the table is constructed before each simulation starts, and the interpolation coefficients in the grid cells are pre-calculated, and the table establishment time before the simulation starts can usually be It can be completed in a few seconds. Compared with the overall simulation time of the circuit, it can be ignored. For a phase-locked loop circuit containing 468 transistors, the average memory overhead of each crystal is about 580KB. It can be seen that this method has a memory consumption for complex analog circuits. It is acceptable; the present invention has simulated a plurality of industrial grade circuits (Level49) to verify the simulation efficiency and precision of this method, and the calculation process of transistor current and charge has about 3x～4x acceleration, and the circuit transient The acceleration efficiency of the analysis depends on the proportion of the time consumption of the transistor model calculation in the entire simulation; Table 2 shows the simulation accuracy and transient analysis acceleration efficiency of three typical circuits and compares them with Synopsys' FineSim software , where the relative error of the phase-locked loop refers to the error of the stable voltage and locked frequency respectively, while the other two circuits are based on the relative error of the waveform; the simulation results of FineSim are based on the simulation accuracy of spice1 using Model 3 (analytic model) and Model 2 (approximate model) two transistor models are obtained.

Table 2 Comparison of transient simulation results

Claims (7)

1. modeling and the estimation method of a kind of accurate table lookup model of transistor, which is characterized in that it includes step：

Step 1：The N-dimensional closing of a given device physics parameter function defines domain space, and two are built on this definition domain space First space cut tree (BSPtree), according to preset error threshold and the physical parameter functional value of parsing to N-dimensional domain Space is divided and records the division points in each dimension；

Step 2：The division space that refinement step one obtains, if the number of division points is respectively n in N number of dimension₁, n₂..., n_N, it is (n by the division points structure scale of step 1 record₁-1)×(n₂-1)×…×(n_N- 1) N-dimensional non-uniform grid (non-uniform grid), each unit (Cell) of grid represent the division space after fining；

Step 3：N number of look-up table is built respectively for subscript of the N-dimensional non-uniform grid in N number of dimension, each look-up table corresponds to One evenly spaced scale is searched entry number and is determined by preset granularity；

Step 4：When defining the progress valuation of a coordinate points in domain space to N-dimensional, first by the coordinate in N number of dimension Component is mapped in N number of look-up table of step 3 structure, obtains grid of the division space comprising the coordinate points in N number of dimension Subscript, then corresponding grid unit is accessed by grid subscript, it is finally treated in the grid cell and coordinate points is asked to be inserted three times It is worth to its functional value and its approximate partial differential value in N number of dimension.

2. method as described in claim 1, which is characterized in that each in the cut tree of binary space in the step one A node (BSP node) defines each division region in domain space with N-dimensional and corresponds.

3. method as described in claim 1, which is characterized in that in the step two, unit and the binary space of N-dimensional grid The node data structure having the same of cut tree；For the grid list divided corresponding to region that boundary before and after fining is constant Member can directly replicate the corresponding node in binary segmentation tree, if boundary changes, the data member in grid cell needs It recalculates.

4. method as described in claim 1, which is characterized in that in the step three, for the grid cell in each dimension Boundary is aligned scale to ensure in Grid Edge without corresponding to the place that scale " scale " is aligned with it by mobile grid boundary Correct lookup near boundary accesses.

5. method as described in claim 1, which is characterized in that in the step three, the look-up table is one-dimension array； Each described look-up table corresponds to its interval of evenly spaced scale and is much smaller than all grid cells in the dimension Minimum boundary length.

6. method as described in claim 1, which is characterized in that in the step four, the grid subscript in look-up table is to sit The Hash mapping of component is marked, which is simply determined by rod interval, brings given coordinate components into the Hash mapping It can obtain the grid subscript in respective dimensions.

7. method as described in claim 1, which is characterized in that when given N-dimensional physical parameter function is in some dimension When variation is slower, coordinate components of the fixed function in the dimension, in remaining N|1 dimension structure non-uniform grid comprising：It is first First by the step one in claim 1, two structure N|The non-uniform grid of 1 dimension, then takes in the slower dimension of the variation sparse And uniform coordinate interval, with remaining N|1 dimension table lattice are that template builds N-dimensional table, are then searched and valuation side in the dimension Method is identical as the subsequent step in claim 1.