CN104916597B - Wafer scale is fanned out to the encapsulating method and structure of chip - Google Patents
Wafer scale is fanned out to the encapsulating method and structure of chip Download PDFInfo
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- CN104916597B CN104916597B CN201410097812.2A CN201410097812A CN104916597B CN 104916597 B CN104916597 B CN 104916597B CN 201410097812 A CN201410097812 A CN 201410097812A CN 104916597 B CN104916597 B CN 104916597B
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/732—Location after the connecting process
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- H01L2224/73267—Layer and HDI connectors
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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Abstract
The present invention provides the encapsulating method and structure that a kind of wafer scale is fanned out to chip.The method for packing that wafer scale provided by the invention is fanned out to chip includes：One carrier is provided, and multiple chips are configured on carrier；Multiple adhesion layers are formed on the active surface of corresponding chip；A conductive cover is covered, conductive cover is made to be binded by adhesion layer and chip, conductive cover simultaneously separates those chips in multiple encapsulated spaces respectively；Insulating materials is made to insert encapsulated space by multiple perforations of conductive cover and forms one first insulation system；And remove carrier.
Description
Technical field
Core is fanned out to the invention relates to the method for packing and structure of a kind of chip, and in particular to a kind of wafer scale
The encapsulating method and structure of piece.
Background technology
With the universalness of electronic product, portable and wearable electronic product are into the work of middle indispensability for people's lives
Tool.And developing has high-effect, small size, high arithmetic speed, high-quality and multi-functional electronic product and element, becoming must
The trend wanted.For appearance, light, thin, short, small electronic product becomes inevitable trend, and in order to coordinate the requirement of trend,
Wafer scale（Wafer Level Chip Scale Package, abbreviation WLCSP）One of the selection that necessitates of packaging technology.
Wafer-level packaging and traditional encapsulation technology major difference is that：The concept of wafer-level packaging is directly in wafer
The upper encapsulation for completing integrated circuit rather than it is packaged processing procedure for the other chip after cutting.By the encapsulation of wafer scale,
The size of chip after encapsulation is identical with the original size of crystal grain.And the size of such wafer-level packaging can limit cloth portable blower
Go out（Fan-Out）Scope.
The content of the invention
The present invention provides a kind of wafer scale and is fanned out to the encapsulating method and structure of chip, and it is an object of the present invention to provide a kind of encapsulation
At low cost, product encapsulation body thickness is thin, and mechanical support ability enhancement has great heat radiation effect, improves product service life
Wafer level is fanned out to chip package structure and method for packing.
The method for packing that the wafer scale of the present invention is fanned out to chip includes：One carrier is provided, and configures multiple chips in the load
On body；Multiple adhesion layers are formed on an active surface of those corresponding chips；A conductive cover is covered, conductive cover is made to pass through this
A little adhesion layers are binded with those chips, which separates those chips in multiple encapsulated spaces respectively；Lead to insulating materials
Multiple perforations in the conductive cover are crossed, those encapsulated spaces is inserted and forms the first insulation system；And remove the carrier.
The present invention separately proposes that a kind of wafer scale is fanned out to the encapsulating structure of chip, including conductive plate, a chip, the first insulation knot
Structure, the second insulation system and multiple weld pads.The conductive plate has supporting part and at least one protrusion, and chip is glutinous by one
Layer to stick together on the supporting part.First insulation system be centered around around the chip on supporting part.The second insulation knot
Structure is individually insulated multiple electrodes window.Those weld pads are arranged respectively in those electrode windows to form multiple electrodes.
Based on above-mentioned, of the invention method for packing by the way that in a manner of sucking (or inserting), insulating materials is completely wrapped
It covers around chip, the thickness of product packaging body can be reduced, improve the reliability of the chip after encapsulation.Also, pass through the present invention
Wafer scale method for packing, the chip after encapsulation can be tested by the tester table of wafer scale, and production is greatly reduced
The complexity and packaging cost of flow
It is to be understood that the above general description and the following detailed description are exemplary, and desirable to provide to as claimed
The present invention's is explained further.
Description of the drawings
Comprising attached drawing to provide a further understanding of the present invention, and attached drawing is incorporated in this specification and forms this specification
A part.The embodiment of the present invention is illustrated, and together with the description explaining the principle of the present invention.
Fig. 1 is the flow chart that the wafer scale of one embodiment of the invention is fanned out to the method for packing of chip；
Fig. 2A~Fig. 2 K are the implementation detail schematic diagram that the wafer scale of the embodiment of the present invention is fanned out to the method for packing of chip.
Fig. 3 A are that the wafer scale of one embodiment of the invention is fanned out to 300 stereogram of encapsulating structure of chip；
Fig. 3 B are the sectional view of 300 line segment B-B ' of encapsulating structure；
Fig. 3 C are the sectional view of the wafer scale fan-out chip packaging structure of another embodiment of the present invention；
Fig. 4 A~Fig. 4 C are the schematic diagram of the application of the encapsulating structure of the embodiment of the present invention.
Reference sign：
S110~S160：The step of method for packing；
210：Carrier；
211：Remove membrane adhesive tape；
221~222,321：Chip；
231、232：Adhesion layer；
240：Conductive cover；
241：Partition plate；
300、410、420：Encapsulating structure；
340：Conductive plate；
370：Adhesion coating；
400：Power-switching circuit；
T1、T2：Side；
H1、H2：Perforation；
Z1、Z2：Encapsulated space；
PM：First insulation system；
GP：Glass substrate；
PL：Second insulation system；
W1~WN：Electrode window；
PAD1~PADN：Weld pad；
BA1~BAN：Soldered ball；
A-A’、B-B’：Line segment；
3401：Supporting part；
3402：Protrusion；
M1~M5：Transistor；
DC：Drain electrode；
S1、S2：Source electrode；
G1、G2：Grid；
D1：Diode；
L1、L2：Inductance；
GND：Ground terminal；
C1：Capacitance.
Specific embodiment
With detailed reference to the preferred embodiment of the present invention, the example is illustrated in the accompanying drawings.Same reference numbers exist
Referring to same or similar part in attached drawing and description.
One embodiment of its manufacturing process and method refers to Fig. 1, and Fig. 1 is that the wafer scale of one embodiment of the invention is fanned out to core
The flow chart of the method for packing of piece.The encapsulation of chip is fanned out to referring to the wafer scale that Fig. 2A~Fig. 2 K are the embodiment of the present invention
The implementation detail schematic diagram of method.In Fig. 1 and Fig. 2A, a carrier 210, the covering of 210 surface of carrier are provided in step S110
Remove membrane adhesive tape 211.In the present embodiment, carrier 210 can be a round carrier consistent with wafer size, such as 6 English
Very little, 8 inches or 12 inches disks.And in terms of material, carrier 210 then can by such as metal, metal alloy, plastics or
It is made by the materials such as quartz glass.Carrier 210 can be that conductive or insulation material is formed.Remove membrane adhesive tape 211 then
It can be the adhesive tape of biadhesive.
Then, in the step s 120, then by the multiple chips cut down on wafer configuration on carrier 210.In this core
Piece is with the metal oxide semiconductor field effect transistor of vertical-type（Metal-Oxide-Semiconductor Field-Effect
Transistor, abbreviation MOSFET）Exemplified by, other are such as igbt (Insulated Gate Bipolar certainly
Transistor, abbreviation IGBT), bipolar junction transistor (Bipolar Junction Transistor, abbreviation BJT), diode
(Diode) etc. all it is possible application, the first active surface of chips can be designed including two source electrode, grid electrodes.Chip back,
I.e. the second active surface is configured as draining.Wherein, in fig. 2b, chip 221~222 is configured in carrier 210, also, chip
221~222 the first active surface is in contact to be binded with removing membrane adhesive tape 211.In step s 130, multiple stick together is formed
On 221~222 the second active surface of multiple chips of the layer on corresponding carrier 210.Such as adhesion layer 231 shown in Fig. 2 C and
232。
On the forming method of adhesion layer 231 and 232, dispensing or halftone coating method can be utilized, there will be conduction
The adhesion layer 231 and 232 of property, it is suitable to be individually positioned on the second active surface of chip 221~222.Adhesion layer 231 and 232
Can be the conduction materials such as elargol, tin cream or copper cream.
In step S140, then conductive cover 240 is covered in the top of chip 221~222 and carrier 210, conductive cover
240, by partition plate 241, chip 221~222 are separated respectively in multiple encapsulated space Z1 and Z2.Conductive cover 240 can pass through
Adhesion layer 231 and 232 generates electric connection with chip 221~222 respectively.Also, the first side T1 of conductive cover 240 has
Multiple partition plates 241.Above-mentioned conductive cover 240 can be circular metal frame, and can have electrical conductivity characteristic by copper, iron nickel etc.
Material formed.Conductive cover 240 can be according to Customer Requirement Design shape and size, and uses etching either punch die
Mode manufactures.Conductive cover 240 can coordinate the wafer of the chip to be encapsulated 221~222 and be made as 6 inches, 8 inches or
It is 12 inches of disk or tabular can be made as.For example, conductive cover 240 can be that the copper of 25um to 100um thickness closes
Made by gold plaque.
In addition, partition plate 241 can lead to overetched mode to be formed, partition plate 241 contacts flat with stripping membrane adhesive tape 211
Face, then can be with the second active surface copline of chip 221~222.Position that partition plate 241 is formed and thickness then can be according to
Corresponding adjustment is carried out according to position of the configuration of chip 221~222 on membrane adhesive tape 211 is removed.It is more in conductive cover 240
A partition plate 241 can be separated out the encapsulated space of multiple array arrangements with the webbed structure of shape.
In step S150, by insulating materials by multiple hole for injecting glue or perforation in conductive cover, encapsulated space is inserted
Left empty Z1, Z2 forms the first insulation system.Please be jointly with reference to Fig. 1 and Fig. 2 E, it can be right in conductive cover 240
The position of encapsulated space Z1 and Z2 is answered to be respectively formed perforation H1 and H2, then refer to Fig. 2 F, by providing liquid
Insulating materials, so that insulating materials PM is received in or is sucked into encapsulated space Z1 and Z2 by perforation H1 and H2, one
The insulating materials being inhaled into embodiment will fill up encapsulated space Z1 and Z2, to form the first insulation system PM.In addition,
After insulating materials fills up encapsulated space Z1 and Z2, and curing action is carried out to the first insulation system PM.
Insulating materials can be insulation moulding material, and can be any suitable thermoplastic or thermosets, such as ring
The resin of oxygroup material, silica gel or photoresist etc..Insulating materials after curing forms multiple moulding bodies, and to provide protection
The rigid structure of chip 221~222.For insulating materials is made to be fully filled with encapsulated space Z1 and Z2, the embodiment of the present invention can lead to
The action for crossing perforation H1 and H2 to be vacuumized, and encapsulated space Z1 and Z2 is made to form vacuum state, then apply liquid
Insulating materials above perforation H1 and H2, allow liquid insulating materials be effectively sucked into encapsulated space Z1 and
In Z2, and fill up encapsulated space Z1 and Z2.Thus, moulding bodies caused by insulating materials after curing will not be because of
It includes multiple holes and causes structure not firm, and promote the reliability of encapsulation.
Then, in step S160, then carrier 210 is removed（As shown in Figure 2 G）.Wherein, the removal of carrier 210 can pass through shifting
Reach except membrane adhesive tape 211 is removed.It is worth noting that, shown in Fig. 2 G, the plastic packaging disk completed by above-mentioned technique
Structure is smooth, without warpage or blocked up and excessive glue problem, without thinned and cleaning is carried out, effectively reduces answering for method for packing
Miscellaneous degree.
Then, after on encapsulation the electrode generation type of chip part, refer to Fig. 2 H~Fig. 2 J.In Fig. 2 H,
The conductive cover 240 of the plastic packaging disk of completion with glass substrate GP is combined, glass substrate GP is made to contact directly conductive cover 240
Second side T2.
And in chip 221~222, the first active surface applies a floor height molecular dielectric material to form an insulating layer, this insulation
Layer purpose be increase passivation layer (passivation) intensity, to chip formed to a certain extent be dielectrically separated from protection.So
Multiple electrodes window W1~WN is formed by part etching mode on the insulating layer afterwards, wherein electrode window W1~WN is as follow-up leakage
Pole, source electrode with gate contact window, and remaining insulation layer segment is formed at except the surface of electrode window W1~WN positions so that the
Two insulation system PL, which are respectively electrode window W1~WN, to be isolated.Electrode window W1~WN is formed at first active surface of chip 221~222
Part on on partition plate 241 part, the second insulation system PL also covers the part of first active surface of chip 221~222
With on partition plate 241 part.Electrode window W1~WN is used for the expose portion of the first active surface of 221~222 part of contact chip
And 241 expose portion of partition plate.On these surfaces exposed, that is, in electrode window W1~WN, then it can be respectively formed multiple welderings
PAD1~PADN is padded, this weld pad is known as convex block underlying metal UBM, as follow-up liner ball or the intermetallic connection of convex block operation
With.
In Fig. 2 I, then multiple soldered ball BA1~BAN are respectively formed on weld pad PAD1~PADN, and form multiple electrodes.
Wherein, soldered ball BA1 then can be used as transistor respectively as the drain electrode of the transistor in chip 221, soldered ball BA2 and BA3
Grid and source electrode.It completes after planting ball correlation operation, glass substrate GP is removed, such as Fig. 2 J.
By Fig. 2 J it is known that multiple chips 221~222 are completed to encapsulate in a manner of wafer scale, and will be to encapsulation working as
When 221~222 chip of chip afterwards is tested, the packaging body test machine that pass through wafer scale of the wafer scale of Fig. 2 J can be utilized
To complete to test.So (Chip Probing, abbreviation CP) is surveyed by the crystal grain on chip according to design using bare crystalline pin
Electrical standard specification, by pin survey in a manner of detect disposably to be tested, be greatly reduced testing cost and test needed for
Time.Can certainly well cutting, to separation complete component carry out finished product test.
The position of the final line segment A-A ' according to Fig. 2 J is cut, such as Fig. 2 K institutes of the encapsulating structure after being cut
Show.In Fig. 2 K, the first active surface and the conductive cover 240 of chip 221 are electrically connected, and pass through soldered ball BA1 to form chip
The drain electrode of transistor in 221, the second active surface of chip 221 are then electrically connected to soldered ball BA2 and BA3 and are respectively formed chip
The grid and source electrode of transistor in 221.
It below please the synchronous encapsulation that chip is fanned out to reference to the wafer scale that Fig. 3 A and Fig. 3 B, Fig. 3 A are one embodiment of the invention
The stereogram of structure 300, Fig. 3 B are the sectional view of 300 line segment B-B ' of encapsulating structure.Encapsulating structure 300 is Fig. 1 according to the present invention
Encapsulating structure caused by the method for packing of embodiment.Wherein, encapsulating structure 300 includes conductive plate 340, by conductive cover 240
Cut one of them multiple, chip 321, the first insulation system PM, the second insulation system PL and multiple soldered ball BA1~BA3.
Conductive plate 340 has supporting part 3401 and protrusion 3402 (corresponding 2H figures partition plate 241), supporting part 3401 and protrusion
3402 contact with each other.Wherein, supporting part 3401 is used for carrying chip 321, and protrusion 3402 is then used for forming soldered ball BA1.
Chip 321 is sticked together by adhesion layer 370 on supporting part 3401, and adhesion layer 370 sticks together material for electrically conductive material
Material, chip 321 are then connected by adhesion layer 370 with 340 electronics of conductive plate.First insulation system PM is then centered around chip 321
Around and cover upper surface of the supporting part 3401 not with chip 321 and contact.Second insulation system PL isolation multiple electrodes window (ginsengs
Examine W1~WN of 2H), and the second insulation system PL is covered on the active surface of segment chip 321 and partially electronically conductive plate 340
On protrusion 3402, as the first insulation system PM because electrodeless window exists, therefore the second insulation system PL can be completely covered
One insulation system PM.Multiple electrodes window touches chip 321.And equally there is multiple electrodes window on protrusion 3402.Above-mentioned electricity
Pole window is used for forming soldered ball BA1~BA3, wherein, in electrode window of the soldered ball BA1 configurations on protrusion 3402, soldered ball BA2, BA3
Then in electrode window of the configuration on chip 321.In the present embodiment, soldered ball BA1 can as the drain electrode of transistor in chip 321,
Soldered ball BA2 can then can be as the source electrode of transistor in chip 321 as the grid of transistor in chip 321, soldered ball BA3.
It is worth noting that, the first insulation system PM in the embodiment of the present invention is by being originally that liquid kenel injects it
In existing space, and cured action is performed to the insulating materials of liquid kenel.The first insulation system PM's after curing
Upper surface can form the upper surface of soldered ball BA1 on the same plane with the protrusion 3402 of conductive plate 340.Such one
Come, the first insulation system PM after curing can form firm structure in encapsulating structure 300, effectively reach protection chip 321
The effect of.
It corresponds to previously with regard in the embodiment of method for packing, the protrusion 3402 of the present embodiment is to be led in previous embodiment
Partition plate in electric cover.The conductive plate 340 of the present embodiment is then the conductive cover in previous embodiment or segmentation rear portion.And
First insulation system PM is the state after curing.
The present embodiment is connected to using metal in chip drain metal layer, in addition to mechanical strength is strengthened, can also be increased scattered
In addition thermal effect may be connected on printed circuit board (PCB) (Printed Circuit Board, abbreviation PCB), utilize printed circuit board (PCB)
On copper foil, further reduce thermal resistivity, improve product service life, also because drain electrode connection metal, can be suitble to thinner
Chip, such as 50um or smaller sizes.Fig. 3 C are cuing open for the wafer scale fan-out chip packaging structure of another embodiment of the present invention
Face figure.Therefore such as Fig. 3 C, this application can insert two identical or different size MOSFET.
On chip 321, the application for the encapsulating structure that Fig. 4 A~Fig. 4 C, Fig. 4 A~Fig. 4 C are the embodiment of the present invention can refer to
Schematic diagram.Wherein, in Figure 4 A, chip 321 can include one or more transistor M1 and M2.Wherein, transistor M1 and
The drain D C of M2 is connected with each other, and can form electrode by soldered ball BA1, and the source S 1 of transistor M1 and M2 and S2 can lead to respectively
It crosses different soldered ball BA3 and forms two mutually isolated source electrodes, and the grid G 1 of transistor M1 and M2 and G2 can be respectively by not
Same soldered ball BA1 forms two mutually isolated grids.
In figure 4b, encapsulating structure of the invention is also applicable in power-switching circuit.Wherein, the power supply in Fig. 4 B turns
Changing circuit 400 includes encapsulating structure 410.Chip in encapsulating structure 410 includes transistor M3 and diode D1.Transistor M3
Drain electrode and the anode of diode D1 can be mutually coupled by the conductive plate in encapsulating structure 410, and pass through corresponding soldered ball institute shape
Into electrode be connected to inductance L1, the source electrode of transistor M3 can be coupled to by the electrode that corresponding soldered ball is formed to be connect
Ground terminal GND, and the grid of transistor M3 can receive driving voltage by the electrode that corresponding soldered ball is formed, and be, for example, arteries and veins
The driving voltage of width modulation signal.In addition, the cathode of diode D1 can be also coupled to by the electrode that corresponding soldered ball is formed
To capacitance C1.
Fig. 4 C are circuit of the tool there are two the encapsulating structure 420 of transistor M4~M5.In figure 4 c, transistor M4~M5 is common
Drain electrode with coupling can be connected to inductance L2, the grid of transistor M4~M5 and source by the electrode on encapsulating structure 420
Pole can then receive required signal or voltage by corresponding electrode respectively, to meet the needs of circuit running.
In conclusion it is of the invention in a manner of sucking or insert, it being made to be coated on around chip insulating materials,
Use the reliability of the chip after improving encapsulation.Also, lower the complexity of production procedure by the method for packing of wafer scale
And be packaged into, effectively promote the competitiveness of product.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe is described in detail the present invention with reference to foregoing embodiments, it will be understood by those of ordinary skill in the art that：Its according to
Can so modify to the technical solution recorded in foregoing embodiments either to which part or all technical characteristic into
Row equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is not made to depart from various embodiments of the present invention technology
The scope of scheme.
Claims (3)
1. a kind of wafer scale is fanned out to the method for packing of chip, which is characterized in that including：
Carrier is provided；
Configure multiple chips on this carrier；
Multiple adhesion layers are formed on the active surface of those corresponding chips；
Conductive cover is covered, the conductive cover is made to be binded by those adhesion layers and those chips, the first side of the conductive cover
Side has multiple partition plates, to separate out multiple encapsulated spaces, and separates those chips respectively in those encapsulated spaces；
Make multiple perforations of the insulating materials by the conductive cover, insert those encapsulated spaces and form the first insulation system；
Remove the carrier；
Glass substrate is provided in the second side of the conductive cover；
Form multiple electrodes window, and be individually insulated with the second insulation system, wherein second insulation system cover part those
On chip with part those partition plates on；And
Multiple weld pads are formed in those electrode windows to form multiple electrodes.
2. method for packing according to claim 1, which is characterized in that the insulating materials is liquid, and makes the insulation
Material inserts those encapsulated spaces and forms first insulation system by those perforations.
3. method for packing according to claim 1, which is characterized in that form those adhesion layers on the surface of those chips
The step of include：
The mode being coated with using dispensing or halftone, forms those adhesion layers, and those are sticked together on the active surface of those chips
Layer is conductive.
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| CN201410097812.2A CN104916597B (en) | 2014-03-14 | 2014-03-14 | Wafer scale is fanned out to the encapsulating method and structure of chip |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1430791A (en) * | 2000-04-04 | 2003-07-16 | 国际整流器公司 | Chip scale surface mounted device and its process of manufacture |
| CN1685498A (en) * | 2002-09-30 | 2005-10-19 | 先进互连技术有限公司 | Thermal enhanced package for block mold assembly |
| CN101572239A (en) * | 2008-04-18 | 2009-11-04 | 英飞凌科技股份有限公司 | Semiconductor module |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7863730B2 (en) * | 2003-08-28 | 2011-01-04 | St Assembly Test Services Ltd. | Array-molded package heat spreader and fabrication method therefor |
| US8338936B2 (en) * | 2008-07-24 | 2012-12-25 | Infineon Technologies Ag | Semiconductor device and manufacturing method |
| US20130119538A1 (en) * | 2011-11-16 | 2013-05-16 | Texas Instruments Incorporated | Wafer level chip size package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1430791A (en) * | 2000-04-04 | 2003-07-16 | 国际整流器公司 | Chip scale surface mounted device and its process of manufacture |
| CN1685498A (en) * | 2002-09-30 | 2005-10-19 | 先进互连技术有限公司 | Thermal enhanced package for block mold assembly |
| CN101572239A (en) * | 2008-04-18 | 2009-11-04 | 英飞凌科技股份有限公司 | Semiconductor module |
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