CN104900704A - Longitudinal DMOS device - Google Patents
Longitudinal DMOS device Download PDFInfo
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- CN104900704A CN104900704A CN201510246431.0A CN201510246431A CN104900704A CN 104900704 A CN104900704 A CN 104900704A CN 201510246431 A CN201510246431 A CN 201510246431A CN 104900704 A CN104900704 A CN 104900704A
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- 239000012212 insulator Substances 0.000 claims description 32
- 239000002800 charge carrier Substances 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 210000000746 body region Anatomy 0.000 abstract 5
- 239000000969 carrier Substances 0.000 abstract 1
- 230000006698 induction Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/0865—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a longitudinal DMOS chip, and the chip comprises a longitudinal DMOS device. The longitudinal DMOS device comprises an A-type drain region, and a B-type drift region above the A-type drain region. The interior of the B-type drift region is provided with a longitudinal grid electrode, and a side wall and bottom of the longitudinal grid electrode are wrapped by a longitudinal grid electrode insulating layer. An outer side of the longitudinal grid electrode insulating layer is provided with a B-type body region, and a side, far from the longitudinal grid electrode insulating layer, of the B-type body region is provided with an A-type source region. The depth of the B-type body region is less than the depth of the longitudinal grid electrode. A lateral grid electrode insulating layer is located above the B-type body region, and a lateral grid electrode is disposed above the lateral grid electrode insulating layer. The doping density of the B-type drift region is lower than the doping density of the B-type body region. A type and B type are conductive types that carriers are hollow or electrons. The device remarkably improves the voltage endurance capability between source electrodes, and improves the current capability during conduction. A conductive trench comprises a lateral conduction direction and a longitudinal conduction direction, thereby improving the conduction breakdown voltage of the device.
Description
Technical field
The invention belongs to field of semiconductor devices, relate to a kind of VDMOSFET chip.
Background technology
DMOS and cmos device similar, be made up of parts such as source, leakage, grid, tagmas, DMOS also comprises the lower drift region of doping content, makes it possible to obtain higher puncture voltage at drain terminal.
DMOS mainly contains two types, vertical double-diffusion metal-oxide-semiconductor field effect transistor VDMOS(vertical double-diffused MOSFET) and lateral double diffusion metal oxide semiconductor field effect transistor LDMOS(lateral double-dif fused MOSFET).Wherein VDMOS is owing to adopting vertical stratification, can obtain larger current capacity and lower conducting resistance, and simultaneously due to the existence of drift region, the breakdown voltage value between source and drain is also higher.
DMOS device is made up of the DMOS unit of hundreds of single structure.The number of these unit is that the driving force required for a chip determines, the performance of DMOS directly determines driving force and the chip area of chip.For the LDMOS device that is made up of multiple basic cell structure, one of them topmost investigation parameter is conducting resistance, with R ds(on) represent.Conducting resistance refers to when devices function, from the resistance draining to source.Should reduce conducting resistance as far as possible for LDMOS device, when conducting resistance is very little, device can provide a good switching characteristic, because conducting resistance little between drain-source, has larger output current, thus can have stronger driving force.The key technical indexes of DMOS has: conducting resistance, threshold voltage, puncture voltage etc.
Give a kind of existing VDMOS structural representation as shown in Figure 1, source region and tagma is followed successively by from top to bottom inside grid, when grid is energized, tagma transoid forms raceway groove, high pressure is born by the drift region below tagma, conductive channel is formed between the drain electrode of charge carrier below source electrode and drift region, the grid oxygen part of this device is greater than side wall upper part in the bottom of gate trench and the thickness of lower sidewall, can inversion channel be obtained in tagma, although said structure achieves puncture voltage between higher drain-source, but be close between grid and source electrode and only isolated by thinner gate oxide, make withstand voltage deterioration between grid and source electrode, between grid source, breakdown voltage value significantly reduces.
Summary of the invention
Low in grid source place voltage withstand capability for overcoming existing VDMOSFET device, easily breakdown technological deficiency, the invention discloses a kind of VDMOSFET chip.
A kind of VDMOSFET chip of the present invention, comprise VDMOSFET device, described VDMOSFET device comprises A type drain region, is positioned at the Type B drift region above A type drain region, have longitudinal grid in described drift region, described longitudinal gate lateral wall and bottom are surrounded by longitudinal gate insulator;
Described longitudinal gate insulator arranged outside has Type B tagma, described Type B tagma is provided with A type source region away from the side of longitudinal gate insulator, the described Type B tagma degree of depth is shallower than longitudinal gate depth, be provided with horizontal gate insulator above tagma, above described horizontal gate insulator, be provided with horizontal grid;
Described drift doping concentration lower than tagma, the conduction type of described A type, Type B to be charge carrier be hole or electronics.
Preferably, described horizontal gate is greater than the longitudinal gate insulating layer thickness of longitudinal grid between tagma and longitudinal grid.
Preferably, described source region is consistent with the tagma degree of depth.
Preferably, the longitudinal gate insulating layer thickness be positioned at below longitudinal gate bottom and sidewall is greater than the longitudinal gate insulating layer thickness above sidewall, and the boundary line above described sidewall and below sidewall is bottom tagma.
Preferably, described longitudinal grid, longitudinal gate insulator, tagma, source region are concentric circles from inside to outside successively in the horizontal direction, and described horizontal grid and horizontal gate insulator are annular.
Preferably, described horizontal grid and longitudinal grid have separately independently electrode fairlead.
Preferably, the ratio of described tagma width and the degree of depth is 1:0.8-1.5, and described tagma width is from source region to longitudinal gate insulator distance in the horizontal direction.
Adopt VDMOSFET chip of the present invention, combine VDMOSFET device and lateral dmos device structure advantage, relatively existing VDMOSFET device significantly improves the device withstand voltage ability between grid source, adopt the tagma and source region that are arranged symmetrically with simultaneously, improve current capacity during break-over of device, conducting channel comprises horizontal and vertical two conducting directions, improves electric field distribution in channel, further increases the conducting puncture voltage of device.
Accompanying drawing explanation
Fig. 1 is existing a kind of VDMOSFET chip cross-section schematic diagram;
Fig. 2 illustrates a kind of embodiment structural representation of VDMOSFET chip of the present invention;
Fig. 3 illustrates a kind of embodiment schematic top plan view of VDMOSFET chip of the present invention;
In Fig. 2 and Fig. 3, Reference numeral name is called: the longitudinal gate insulator bottom the longitudinal gate lateral wall of the longitudinal grid 9-of longitudinal gate insulator 8-above the longitudinal gate lateral wall of the horizontal grid 7-of the horizontal gate insulator 6-of 4-drain region, 3-drift region, 2-tagma, 1-source region 5-and below sidewall, 10-fold-line-shaped raceway groove.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
A kind of VDMOSFET chip of the present invention, comprise VDMOSFET device, described VDMOSFET device comprises A type drain region 4, is positioned at the Type B drift region 3 above A type drain region, have longitudinal grid 8 in described drift region, described longitudinal gate lateral wall and bottom are surrounded by longitudinal gate insulator; Described longitudinal gate insulator arranged outside has Type B tagma 2, described Type B tagma is provided with A type source region away from the side of longitudinal gate insulator, the described Type B tagma degree of depth is shallower than longitudinal gate depth, be provided with horizontal gate insulator above tagma, above described horizontal gate insulator, be provided with horizontal grid; Described drift doping concentration lower than tagma, the conduction type of described A type, Type B to be charge carrier be hole or electronics.
The conduction type of described A type, Type B to be charge carrier be hole or electronics, such as, when A type is P type, Type B is N-type.
In a kind of embodiment of the present invention as shown in Figure 2, with A type for P type, Type B is N-type is example, and what be positioned at bottom is drain electrode, and drain implants type is N-type, usual doping content is larger, drain electrode top is P type drift region, in DMOS, and main withstand voltage region when drift region is conducting, doping content is lower, and resistance is larger.
In the present invention, the vertical direction in tagma 2 is provided with longitudinal grid 8, horizontal direction is provided with horizontal grid 6, longitudinal grid 4 and being isolated by longitudinal gate insulator and horizontal gate insulator 5 respectively between horizontal grid 6 and tagma 2, and gate insulator can be silicon dioxide.
In longitudinal grid and horizontal grid forward grid voltage all in addition, lateral channel is gone out by horizontal grid induction at tagma upper surface, tagma induces longitudinal channel near the side of longitudinal grid, lateral channel and longitudinal channel form fold-line-shaped raceway groove 10, and fold-line-shaped raceway groove 10 connects source region 1 and drift region 3 and forms conductive path.
In the past because longitudinal grid must take into account the induction transoid of tagma and longitudinal grid, thickness can not obtain too thick, cause longitudinal grid and source region insulating barrier limited, the present invention adopts said structure to design, longitudinal thickness of insulating layer is no longer limited between source region and grid, the lateral channel that source region and horizontal grid are formed realizes electricity and is connected, and the horizontal gate insulating layer thickness below horizontal grid freely can control according to withstand voltage needs, has increased substantially grid source puncture voltage.
Meanwhile, adopt horizontal and vertical two conducting channels composition fold-line-shaped raceway groove, improve the electric field distribution in channel in tagma, further increase the conducting puncture voltage of device.
Wherein, balanced for ensureing the current capacity of lateral channel and longitudinal channel, when horizontal grid is consistent with the grid voltage that longitudinal grid applies, the ratio of described tagma width and the degree of depth is preferably set to 1:0.8-1.5, the complete shaping of lateral channel and longitudinal channel can be ensured, and realizing the rounding off of inversion regime around the corner, the current capacity of same fold-line-shaped raceway groove is constantly roughly the same.Described tagma width is from source region to longitudinal gate insulator distance in the horizontal direction.
Preferred implementation is that horizontal gate is greater than the longitudinal gate insulating layer thickness of longitudinal grid between tagma and longitudinal grid, strengthens grid source withstand voltage, and ensure the transoid sensing capability of longitudinal grid to tagma in the mode increasing horizontal gate.
In prior art, longitudinal grid is parallel with source region is close to, and easily assembles electric charge and causes and puncture, and horizontal grid and tagma in the present invention are also non-close, further improve the Electric Field Distribution of grid source intersection, reduce the density of electric fluxline, improve device withstand voltage performance.
In integrated circuit fabrication process, horizontal grid can be connected by the upper strata metal be close to it with longitudinal grid, use public electrode, but horizontal grid and longitudinal grid also can distinguish connection metal as respective independently electrode fairlead, such as because longitudinal grid has resistance in the vertical direction, still need to possess induction transoid ability in comparatively depths, therefore longitudinal grid can apply the voltage higher than horizontal grid.
Source region is usually consistent with the tagma degree of depth, and convenient formation source electrode, to the current path in tagma, reduces conducting resistance and also facilitates technique to etch realization.
In embodiment shown in Fig. 2, longitudinal gate insulator 9 thickness be positioned at below longitudinal gate bottom and sidewall is greater than the thickness of the longitudinal gate insulator 7 above sidewall, boundary line above described sidewall and below sidewall is bottom tagma 2, be limited with bottom, bottom is above is above sidewall, and bottom is below sidewall below.
Longitudinal grid gos deep into below tagma, the induction of longitudinal grid to tagma can be improved, improve break-over of device electric current, but transoid can be responded in drift region, adopt with longitudinal gate bottom the insulation layer structure thickeied below sidewall, weaken the sensing capability of longitudinal grid for drift region, improve drift region voltage tolerance, further increase the voltage endurance capability of device.
In embodiment shown in Fig. 2, can centered by longitudinal grid, be arranged symmetrically with tagma, source region and horizontal grid, Fig. 3 provides a kind of schematic top plan view of embodiment,
As shown in Figure 3, described longitudinal grid, longitudinal gate insulator, tagma, source region are concentric circles from inside to outside successively in the horizontal direction, and described horizontal grid and horizontal gate insulator are annular.Adopt above-mentioned concentric circles, make full use of longitudinal grid omnidirectional's induction effect in the horizontal direction, extended device On current ability to greatest extent.
Previously described is each preferred embodiment of the present invention, preferred implementation in each preferred embodiment is if not obviously contradictory or premised on a certain preferred implementation, each preferred implementation can stack combinations use arbitrarily, design parameter in described embodiment and embodiment is only the invention proof procedure in order to clear statement inventor, and be not used to limit scope of patent protection of the present invention, scope of patent protection of the present invention is still as the criterion with its claims, the equivalent structure change that every utilization specification of the present invention and accompanying drawing content are done, in like manner all should be included in protection scope of the present invention.
Claims (7)
1. a VDMOSFET chip, comprises VDMOSFET device, and described VDMOSFET device comprises A type drain region, is positioned at the Type B drift region above A type drain region, has longitudinal grid in described drift region, and described longitudinal gate lateral wall and bottom are surrounded by longitudinal gate insulator;
It is characterized in that, described longitudinal gate insulator arranged outside has Type B tagma, described Type B tagma is provided with A type source region away from the side of longitudinal gate insulator, the described Type B tagma degree of depth is shallower than longitudinal gate depth, be provided with horizontal gate insulator above tagma, above described horizontal gate insulator, be provided with horizontal grid;
Described drift doping concentration lower than tagma, the conduction type of described A type, Type B to be charge carrier be hole or electronics.
2. VDMOSFET chip as claimed in claim 1, it is characterized in that, described horizontal gate is greater than the longitudinal gate insulating layer thickness of longitudinal grid between tagma and longitudinal grid.
3. VDMOSFET chip as claimed in claim 1, it is characterized in that, described source region is consistent with the tagma degree of depth.
4. VDMOSFET chip as claimed in claim 1, it is characterized in that, the longitudinal gate insulating layer thickness be positioned at below longitudinal gate bottom and sidewall is greater than the longitudinal gate insulating layer thickness above sidewall, and the boundary line above described sidewall and below sidewall is bottom tagma.
5. VDMOSFET chip as claimed in claim 1, is characterized in that, described longitudinal grid, longitudinal gate insulator, tagma, source region are concentric circles from inside to outside successively in the horizontal direction, and described horizontal grid and horizontal gate insulator are annular.
6. VDMOSFET chip as claimed in claim 1, is characterized in that, described horizontal grid and longitudinal grid have separately independently electrode fairlead.
7. VDMOSFET chip as claimed in claim 1, it is characterized in that, the ratio of described tagma width and the degree of depth is 1:0.8-1.5, and described tagma width is from source region to longitudinal gate insulator distance in the horizontal direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510246431.0A CN104900704A (en) | 2015-05-15 | 2015-05-15 | Longitudinal DMOS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510246431.0A CN104900704A (en) | 2015-05-15 | 2015-05-15 | Longitudinal DMOS device |
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| CN104900704A true CN104900704A (en) | 2015-09-09 |
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| CN201510246431.0A Pending CN104900704A (en) | 2015-05-15 | 2015-05-15 | Longitudinal DMOS device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109830527A (en) * | 2019-03-27 | 2019-05-31 | 北京燕东微电子科技有限公司 | Semiconductor structure and its manufacturing method and semiconductor devices |
| CN112614891A (en) * | 2020-03-04 | 2021-04-06 | 许曙明 | Mosfet with enhanced high frequency performance |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006127914A2 (en) * | 2005-05-26 | 2006-11-30 | Fairchild Semiconductor Corporation | Trench-gate field effect transistors and methods of forming the same |
| CN102130003A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Preparation method of vertical trench MOS (Metal Oxide Semiconductor) device |
| US20140167144A1 (en) * | 2012-12-19 | 2014-06-19 | Alpha And Omega Semiconductor Incorporated | Vertical dmos transistor |
-
2015
- 2015-05-15 CN CN201510246431.0A patent/CN104900704A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006127914A2 (en) * | 2005-05-26 | 2006-11-30 | Fairchild Semiconductor Corporation | Trench-gate field effect transistors and methods of forming the same |
| CN102130003A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Preparation method of vertical trench MOS (Metal Oxide Semiconductor) device |
| US20140167144A1 (en) * | 2012-12-19 | 2014-06-19 | Alpha And Omega Semiconductor Incorporated | Vertical dmos transistor |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109830527A (en) * | 2019-03-27 | 2019-05-31 | 北京燕东微电子科技有限公司 | Semiconductor structure and its manufacturing method and semiconductor devices |
| CN109830527B (en) * | 2019-03-27 | 2023-11-10 | 北京燕东微电子科技有限公司 | Semiconductor structure, manufacturing method thereof and semiconductor device |
| CN112614891A (en) * | 2020-03-04 | 2021-04-06 | 许曙明 | Mosfet with enhanced high frequency performance |
| US20210280680A1 (en) * | 2020-03-04 | 2021-09-09 | Shuming Xu | Metal-oxide-semiconductor field-effect transistor having enhanced high-frequency performance |
| TWI805991B (en) * | 2020-03-04 | 2023-06-21 | 大陸商上海晶豐明源半導體股份有限公司 | Metal-oxide-semiconductor field-effect transistor device |
| US11967625B2 (en) * | 2020-03-04 | 2024-04-23 | Shanghai Bright Power Semiconductor Co., Ltd. | Metal-oxide-semiconductor field-effect transistor having enhanced high-frequency performance |
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Application publication date: 20150909 |