CN104767959A - Method for converting single-pixel digital video signal into multi-pixel digital video signal - Google Patents

Abstract

The invention discloses a method for converting a single-pixel digital video signal into a multi-pixel digital video signal. The method comprises the following steps that 1, an RGB signal, a horizontal synchronizing signal, a field synchronizing signal and an enable signal in an input video stream are latched through a pixel clock, and are ranked according to a data ranking mode required by an LVDS receiver at the end of a liquid crystal display panel; 2, video data of each row are classified and then alternately written into N cache regions through the pixel clock of input video; 3, the video data in the N cache regions are synchronously read out through a frequency demultiplication clock and then sent to an LVDS sending IP, and are encoded into a multi-pixel video stream to be output. A single-pixel data stream can be converted into a multi-pixel data stream only by consuming few logic resources and chip pins, the liquid crystal display panel of an LVDS interface is driven, no additional LVDS sending circuit needs to be added, the complexity of PCB design can be lowered, devices can be saved, display quality can be improved, and electromagnetic interference can be lowered.

Description

A kind ofly realize the conversion method of single pixel to many pixels digital video signal

Technical field

Patent of the present invention belongs to field of video image processing, relates to video sampling/coding, pixel format conversion, caching technology.

Background technology

LVDS (Low Voltage Differential Signal) transmission technology has the feature of low noise and low-power consumption, and thus in liquid crystal panel, a large amount of LVDS interface that adopts carrys out transmission digital video signal.LVDS interface circuit comprises drive end LVDS output interface (LVDS transmitter) and display end LVDS input interface (LVDS receiver).Some airborne cockpit display system adopts the liquid crystal panel of LVDS interface, and this goes to drive liquid crystal display screen display with regard to needing that the digital video signal that figure module produces is converted to LVDS signal.In civilian passenger cabin synthetic display equipment, display terminal can verify the data received, once detect error code, and will automatic alarm close display screen.As can be seen here, civilian passenger cabin is combined the integrality of aobvious equipment to LVDS Signal transmissions and is had higher requirement.

FPGA is a kind of parallelization work, and interface level various (supporting LVDS interface), logical operation is flexible, the device that can repeatedly programme.Its inside also has abundant logical resource, meets the demand to certain data buffer storage, is particularly suitable for using in field of video processing.Consider that the transmission of video parallel digital signal has at a high speed, the feature of high bandwidth, between its link, there is crosstalk, when transmitting between plate and clock signal not easily align, easily cause respective pixel point sampling mistake, affect video display effect.A kind of corrective measure effectively converts the signal of single pixel to many picture element signal to transmit, and required clock signal frequency significantly reduces, and this will significantly improve signal receiving quality, promotes display quality.Such as adopt single pixel-wise to transmit the LVDS video of 1680x1050@60, the clock frequency that single pixel sends is 119MHz, as long as and adopt two pixel-wise 59.5MHz, adopt four pixels only to need 29.75MHz.Just because of this, the transmission means that aobvious equipment have employed many pixels is combined by some civil aviatons.

Conventional single pixel transitions becomes many pixels approach to be cross clock domain sampling.The low-speed clock that it utilizes phase-locked loop frequency division to obtain goes initial data at a high speed of sampling, and then sends along separate routes.But this process is easily powered by phase-locked loop and the impact of temperature drift, and cause sample error and then affect the correct transmission of original high resolution video, autgmentability is poor.

Summary of the invention

For the deficiencies in the prior art, goal of the invention of the present invention is that providing a kind of realizes the conversion method of single pixel to many pixels digital video signal.This conversion method has simplicity of design, favorable expandability, low delay, and resource consumption is few, the feature that cost is low.

Goal of the invention of the present invention is achieved through the following technical solutions:

Realize the conversion method of single pixel to many pixels digital video signal, comprise following steps:

Step 1), with pixel clock, the rgb signal in input video stream, line synchronizing signal, field sync signal and enable signal are latched, and according to liquid crystal panel end LVDS receiver require data array sort;

Step 2), with the pixel clock of input video, every row video data is alternately write after classifying in N number of buffer area;

Step 3), the video data frequency-dividing clock in N number of buffer area is synchronously read after send LVDS to send in IP, be encoded into many video pixel streams and export.

Wherein, N is more than or equal to 2.

Compared with prior art, beneficial effect of the present invention is:

Hardware resource cost of the present invention is little, do not need extra increase LVDS transtation mission circuit, autgmentability is strong, economical easy-to-use, efficiently solve high-resolution single pixel video and change the situation that in many pixel video process, pixel is lost, be easy to expand in the transmission of many pixels simultaneously and go, in the display system to data transportation requirements pin-point accuracy such as civil aviaton, there is significant market prospects and economic benefit.

Accompanying drawing explanation

Fig. 1 is for realizing hardware structure diagram of the present invention;

Fig. 2 is the internal logic theory diagram that in the embodiment of the present invention, single pixel transitions becomes two pixel video;

Fig. 3 is the form schematic diagram of video data sequence in the present invention;

Fig. 4 is the schematic diagram that in the embodiment of the present invention, single pixel video turns two pixel video;

Fig. 5 is the internal logic theory diagram that in the embodiment of the present invention, single pixel transitions becomes many pixel video.

Embodiment

The present invention devises a kind of in units of video data lines innovatively, classification is written in multiple buffer memory, then from each buffer memory, synchronously data are read, realize the conversion method of single picture element signal to many picture element signals, the processing method being converted to double image element LVDS video for single pixel video in certain civil aviaton's liquid crystal display screen below describes in detail.

The present embodiment for single pixel numeral Video Quality Metric for double image element LVDS video is described.The present invention adopts hardware circuit board as shown in Figure 1, and its internal logic as shown in Figure 2.Need the rgb signal of the 24bit of single picture element signal, line synchronizing signal (HSYNC), field sync signal (VSYNC), enable signal (DE) during transmission of video, the data array required according to liquid crystal panel end LVDS receiver sends signal, and (putting in order of different liquid crystal display screen manufacturers may be different, as shown in Figure 3, resolution is 1680x1052@60Hz to the liquid crystal display screen data array that the present embodiment uses).Carry out classification to the video data of often going to be stored in two buffer memorys, finally deliver to IP kernel and convert the signal into the transmission of LVDS form.

From description above, can find out, the present embodiment is mainly divided into 3 links, i.e. video signal data sequence, single pixel transitions double image element, LVDS send.

1st link, vision signal sorts, or is called coding.Contain rgb signal, row field clock signal and pixel clock in input video stream, with pixel clock, R [7:0], G [7:0], B [7:0], HSYNC, VSYNC, DE are total to 27bit latches data and sort according to the coded format shown in Fig. 3.Encoded radio under this pixel clock of latched value correspondence one-tenth of each 27bit, it contains complete RGB and time sequence information, by just reducing in receiving terminal decoding.

2nd link, with the pixel clock of input video, every row video data is counted, the pixel being arranged in odd positions after having sorted is deposited into " strange buffer memory ", and even pixel point is stored in " even buffer memory ", is written in two buffer memorys video data odd-even alternation.The read operation of odd even buffer memory is carried out simultaneously, owing to being that every 2 pixel clocks just write one group of odd and even data, therefore needs to use PCLK to read data in two buffer memorys simultaneously.The read-write clock of FIFO has synchronized relation, and time initial, FIFO is empty, in order to avoid read/write conflict, must wait for that FIFO could start read work after being written into several data, therefore many delays of several pixel clock.

Resolution is that single pixel video data of 1680x1050@60Hz illustrate as shown in Figure 4.

3rd link, directly send LVDS to send in IP after double image element video data ODD_DATA and EVEN_DATA frequency-dividing clock synchronously being read, and is encoded into two video pixel stream LVDS_DAT [7:0] and exports.

As shown in Figure 5, such as, if single pixel data is converted to many pixels to go transmission, three pixels, four pixels etc., same principle can be adopted to carry out expansion design.

Claims (1)

1. realize the conversion method of single pixel to many pixels digital video signal, comprise following steps:

Step 1), with pixel clock, the rgb signal in input video stream, line synchronizing signal, field sync signal and enable signal are latched, and according to liquid crystal panel end LVDS receiver require data array sort;

Step 2), with the pixel clock of input video, every row video data is alternately write after classifying in N number of buffer area;

Step 3), the video data frequency-dividing clock in N number of buffer area is synchronously read after send LVDS to send in IP, be encoded into many video pixel streams and export.

Wherein, N is more than or equal to 2.