CN104767506B - A kind of IGBT failures feedback and process circuit - Google Patents
A kind of IGBT failures feedback and process circuit Download PDFInfo
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Abstract
The invention provides a kind of IGBT failures feedback and process circuit and method, realize that beneficial effects of the present invention are by failure sequence generation unit and failure sequence processing unit：Setting timing circuit and counting circuit to cooperate can avoid the mistake of fault-signal from protecting and recover by mistake, improve the reliability of IGBT work；Because secondary chip uses dual power supply, failure narrow pulse sequence only can be produced with a lower trombone slide, simplify circuit.
Description
Technical field
The present invention relates to a kind of failure feedback and process circuit and method, more particularly to a kind of raising IGBT error protections can
By property and the failure feedback of antijamming capability and process circuit and method.
Background technology
There is isolated-gate field effect transistor (IGFET) (Insulated Gate Bipolar Transistor, IGBT) input to hinder
Anti- height, small driving power, high pressure resistant high current, the advantages of switching speed is fast, saturation voltage drop is small, thus in being widely used in, it is big
In power switch power source.In practical work process, IGBT is frequently encountered all kinds of failures, such as short trouble, over current fault, drive
Dynamic failure, VCE over-voltage faults etc..Damage in order to avoid above-mentioned failure to IGBT device, coordinates drive circuit to also need to pin
To the protection circuit of different faults form.Protection circuit takes the protections such as drop grid voltage, soft switching, hiccup shut-off according to failure mode
Measure, while needing isolator to feed back to fault-signal in control chip, control signal is masked.When failture evacuation also
Need reset signal feeding back to control chip, recover the output of control signal.
, can be with random interference spike in Switching Power Supply due to stray capacitance, the presence of inductance.When fault-signal and again
Interference is run into the signal regeneration processes of position, then is likely to result in IGBT mistake protection or recovers by mistake, influence IGBT normal work.It is existing
Have in technology, can be using the method for setting blind area, such as Publication No. in order to avoid the interference of voltage or current spike
CN102263544 China has the right patent；Or Dual Failures signal is used, still have after first fault-signal constant time lag
Failure then transmits second failure signal, and control signal is shielded, such as Publication No. CN103199832 Chinese patent Shen
Please.These circuits all there is failure feedback complexity, it is necessary to which extra feedback path, anti-interference is with protecting instantaneity to conflict not
Foot.
The content of the invention
The present invention first purpose be：A kind of IGBT failures feedback and processing method are provided.This method can be carried significantly
The reliability of high failed transmission, it is to avoid the mistake to IGBT is protected and recovered by mistake.
First purpose of the present invention is achieved through the following technical solutions：A kind of IGBT failures feedback and processing side
Method, is realized by failure sequence generation unit and failure sequence processing unit；When an error occurs, failure sequence generation unit root
Failure narrow pulse sequence is produced according to failsafe state, and described failure narrow pulse sequence is sent to by coupling transformer
The failure sequence processing unit of main side control chip；Failure sequence processing unit in main side control chip the time of setting it
If interior detect two or more failure narrow pulse sequences, produce shielded signal and mask control signal；Failure
After exclusion, failure sequence generation unit malfunction, which is produced, recovers narrow pulse sequence, and by described recovery burst pulse sequence
Row are sent to the failure sequence processing unit of main side control chip by coupling transformer；Failure sequence in main side control chip
If processing unit detects two or more recovery narrow pulse sequences within the time of setting, shielded signal is removed
Pin, recovers the normal transmission of control signal.
Second object of the present invention is to provide a kind of IGBT failures feedback and process circuit, and the purpose is by following skill
What art scheme was realized：
A kind of IGBT failures feedback and process circuit, including signal coupling transformer, fault secure circuit, in addition to failure
Sequence production unit and failure sequence processing unit.Described failure sequence generation unit include the first drop-down high pressure NMOS pipe,
First charges with door, the first phase inverter, the second phase inverter, the one or four digit counter, first comparator, the first current source, first
Electric capacity, first switch NMOS tube, the first NAND gate, the first delayer and the first rest-set flip-flop；The first described drop-down high pressure
The drain electrode of NMOS tube connects the upper end pin of signal coupling transformer secondary, and the grid of the first drop-down high pressure NMOS pipe connects first and door
Output end, source electrode meets the reference ground VEE that secondary is powered.Described first with the output of one of door input the first phase inverter of termination
End, the output end of another input the second phase inverter of termination, the output of input the one or four digit counter of termination of the second phase inverter
End.The output end of the input termination first comparator of first phase inverter, the output end of the first comparator is accessed simultaneously
The input of one or four digit counter and the first delayer input.Output the first NAND gate of termination of first delayer
One input.The positive input termination reference voltage V of the first comparatorREF, negative input end connects the negative of the first current source respectively
The drain electrode at end, first charging capacitor one end and first switch NMOS tube.The power supply electricity of the positive termination secondary of first current source
Source VDDS, the grid of the first switch NMOS tube connects the output end of first NAND gate, the first switch NMOS tube
The other end of source electrode and first charging capacitor meets the reference ground VEE of secondary together.Another input of first NAND gate
Terminate the Q output of the first rest-set flip-flop.The output end of the S input termination fault secure circuits of first rest-set flip-flop, R ends
Connect the Self-resetting narrow pulse signal of the one or four digit counter output.
Described failure sequence processing unit includes the first d type flip flop, first liang of digit counter, the second comparator, second
Current source, the second charging capacitor, second switch NMOS tube, the 3rd phase inverter, the first narrow-pulse generator and the second d type flip flop；
The power supply VDD of the D input termination primary sides of second d type flip flop, the triggering end CP of second d type flip flop receive main side
Failure narrow pulse sequence that push-pull drive is detected recovers narrow pulse sequence, and the reset terminal CLR of second d type flip flop connects the
The output end of one narrow-pulse generator, the Q output of second d type flip flop connects the input of the 3rd phase inverter.Described 3rd
The grid of the output termination second switch NMOS tube of phase inverter, the drain electrode of the second switch NMOS tube connects the second current source respectively
Negative terminal, the negative input end of one end of the second charging capacitor and the second comparator, the source electrode of the second NMOS tube and the second charging
The reference ground VSS on the main side of another termination of electric capacity.The positive input termination reference voltage V of second comparatorREF, output termination
The Enable Pin EN of the input of first narrow-pulse generator and first liang of digit counter.Another input of first liang of digit counter
End receives failure narrow pulse sequence or recovers narrow pulse sequence, the CP triggering ends of output the first d type flip flop of termination.First D
Trigger is connected into the form of frequency divider, i.e., its inverted Q output is connected to D inputs, and the reset terminal CLR of the first trigger connects chip
Initializing signal.
The basic functional principle of the present invention is as follows：When the failures such as IGBT generations short circuit, excessively stream or its drive circuit occur to owe
During the failures such as pressure, overvoltage, corresponding protection act is made to IGBT drive signal by fault secure circuit.Meanwhile, failure is protected
Fault status signal is sent to failure sequence generation unit by protection circuit in burst pulse form, and acquiescence receives first burst pulse
Represent that IGBT breaks down, receive second burst pulse and represent IGBT failture evacuations.First burst pulse triggers the first RS
The output set of device, the original state of above-mentioned first charging capacitor is 0V, then first comparator output high level, the first NAND gate
Output low level turns off first switch NMOS.First current source starts to charge to the first electric capacity, when charging voltage reaches VREF
When, first comparator output low level burst pulse causes the output end change of first and door after the constant time lag of delayer
For high level, the first NMOS tube is opened and rapid by the voltage pull-down on the first electric capacity, and first comparator exports high level again.Weight
Multiple above-mentioned action, so that first comparator exports continuous low level burst pulse.This burst pulse is input to the first phase inverter and
In one or four digit counters.The original state output low level of counter, exports high level to first after the second phase inverter
The high level narrow pulse sequence of the first phase inverter output is received with another input of door with an input of door, first, then
First is open-minded by trombone slide under the first high pressure NMOS with door output high level burst pulse, and the upper end of coupling transformer secondary is continuously drawn
Low level pulse sequence of the low yield life corresponding to high level burst pulse.Exported after four digit counters receive four burst pulses
High level, and produce the narrow pulse signal of Self-resetting and reset four digit counters, touched while reset pulse is output into the first RS
The R input of device is sent out, Q output is reset to low level.So as to which the first NAND gate exports high level by first switch NMOS tube
It is open-minded, the current potential on the first charging capacitor is dragged down.Above-mentioned down pulse Sequence Generation circuit is stopped, until error protection
The narrow pulse signal that the next representing fault of circuit output is excluded, pulse train generation circuit produces the narrow arteries and veins for representing and recovering signal
Rush sequence.
After down pulse sequence is sent to the main side of coupling transformer, is detected by push-pull driver circuit and be output to event
Hinder processing unit.First liang of digit counter in fault processing unit is started counting up after receiving first pulse.Simultaneously
The CP ends of second d type flip flop receive described pulse train, i.e. by Q output set are high level since first pulse,
So as to which second switch NMOS tube be turned off.Second current source starts to charge to the second charging capacitor, when charging potential reaches VREF
When, the second comparator output low level resets first liang of digit counter.A low level is produced by narrow-pulse generator simultaneously
Burst pulse the second d type flip flop is resetted so that second switch NMOS tube is open-minded, the current potential of the second charging capacitor is dragged down.
If first liang of digit counter is charged to V in the second electric capacityREFTwo down pulses are able to detect that in period, then export one
Burst pulse triggers the first d type flip flop, while two digit counter is resetted.The inverted Q output of first d type flip flop produces one
Low level shielded signal masks the control signal that control chip is sent.Hereafter, if fault processing unit is detected again
Then it is defaulted as recovering signal to narrow pulse sequence, the burst pulse that two digit counters are produced triggers the first d type flip flop, anti-phase Q outputs
End is changed into high level, that is, recovers the transmission of control signal.
The beneficial effects of the present invention are：
1st, setting timing circuit and counting circuit to cooperate can avoid the mistake of fault-signal from protecting and recover by mistake, improve
The reliability of IGBT work；
2nd, because secondary chip uses dual power supply, failure narrow pulse sequence only can be produced with a lower trombone slide, simplified
Circuit.
Brief description of the drawings
Fig. 1 is the typical application circuit of failure feedback of the present invention and process circuit；
Fig. 2 is the workflow diagram of failure feedback of the present invention and processing method；
Fig. 3 is the exemplary waveform diagram of failure feedback of the present invention and process circuit.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, below in conjunction with accompanying drawing 1, accompanying drawing 2 is attached
The present invention is described in more detail by Fig. 3.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention,
It is not intended to limit the present invention.
Embodiment one
A kind of IGBT failures feedback and process circuit, as shown in figure 1, including：At failure sequence generation unit 12 and failure
Manage unit 11.In order to make it easy to understand, also drawn other functional modules of application circuit out in figure, including：Second with door 14,
Edge pulse modulation unit 15, main side push-pull drive unit 16, signal coupling transformer 17, pulse reduction unit 13, excessively stream inspection
Survey unit 18, TVS pipe 23, secondary push-pull drive 19, fault secure circuit 21, IGBT22.
Whole circuit has three power supplies, is the VDD15V on main side, the VDDS25V of secondary, the COM10V of secondary respectively,
VSS and VEE are the reference ground of main side and secondary respectively.
Described second control signal produced with one of door 14 input termination control chip, another input termination failure
The shielded signal that processing unit is produced, input of the output end edge fit along pulse modulation unit 15；The edge impulse modulation list
Two output ends of member 15 connect two inputs of main side push-pull drive unit 16 respectively, and 16 two output ends connect coupling respectively
Two inputs of transformer 17；The upper end output end of the coupling transformer 17 connects the input of pulse reduction unit 13 respectively
With the output end of failure sequence generation unit 12, lower end output termination secondary power supply COM10V；The pulse reduction unit
The input of 13 output termination secondary push-pull drive 19, an output of 19 another input termination fault secure circuit 21
End, 19 output termination IGBT grid G.The negative electrode of the TVS pipe meets IGBT colelctor electrode C, and anode connects over-current detection unit
18 input.One input of the output termination fault secure circuit of the over-current detection unit 18；The error protection
Another input of circuit terminates other fault-signals, the input of another output termination failure sequence generation unit.
The failure sequence generation unit 12 includes：First drop-down high pressure NMOS pipe 121, first and door 122, first is anti-phase
Device 123, the digit counter 125 of the second phase inverter the 124, the 1st, first comparator 126, the first current source 127, the first charging electricity
Hold 128, first switch NMOS tube 129, the first NAND gate 1210, the first delayer 1211, the first rest-set flip-flop 1212.Described
The drain electrode of first drop-down high pressure NOMS pipes 121 connects the upper end pin of signal coupling transformer secondary, and grid connects first and door 122
Output end, source electrode meets the reference ground VEE that secondary is powered.Described first is defeated with one of door input the first phase inverter 123 of termination
Go out end, the output end of another input the second phase inverter 124 of termination, the input of the second phase inverter 124 terminates the one or four counting
The output end of device 125.The output end of the input termination first comparator 126 of first phase inverter 123, the first comparator
Output end simultaneously access the one or four digit counter 125 input and the input of the first delayer 1211.First delay
One input of output the first NAND gate 1210 of termination of device.The positive input termination reference voltage V of the first comparatorREF,
Negative input end connects the leakage of negative terminal, the one end of the first charging capacitor 128 and the first switch NMOS tube 129 of the first current source 127 respectively
Pole.The power supply VDDS of the positive termination secondary of first current source, the grid of the first switch NMOS tube 129 connects described
The other end of the output end of first NAND gate, source electrode and first charging capacitor meets the reference ground VEE of secondary together.Described
Another input of one NAND gate terminates the Q output of the first rest-set flip-flop 1212.The S input termination events of first rest-set flip-flop
Hinder the fault status signal of protection circuit output, R terminates the Self-resetting narrow pulse signal of the one or four digit counter 125 output.
Described failure sequence processing unit includes the first d type flip flop 111, first liang of digit counter 112, the second comparator
113, the second current source 114, second switch NMOS tube 115, the second charging capacitor 116, the 3rd phase inverter 117, the second d type flip flop
118, the first narrow-pulse generator 119.The power supply VDD of the D input termination primary sides of second d type flip flop 118, triggering end
CP receives the pulse train for the fault-signal that main side push-pull drive 16 is detected or recovers the pulse train of signal, reset terminal CLR
The output end of the first narrow-pulse generator 119 is connect, Q output connects the input of the 3rd phase inverter 117.3rd phase inverter
The grid of 117 output termination second switch NMOS tube 115, the drain electrode of the second switch NMOS tube connects the second current source respectively
The negative input end of 114 negative terminal, one end of the second charging capacitor 116 and the second comparator 113, the source electrode of the second NMOS tube and
The reference ground VSS on the main side of another termination of the second charging capacitor 116.The positive input termination reference voltage of second comparator
VREF, export the input of the first narrow-pulse generator of termination and the Enable Pin EN of first liang of digit counter 112.Described first liang
Another input of digit counter receives the pulse train of fault-signal or recovers the pulse train of signal, and the first D of output termination is touched
Send out the CP triggering ends of device 111.First d type flip flop 111 is connected into the form of frequency divider, i.e., its inverted Q output is connected to D inputs
End, the reset terminal CLR of the first trigger 111 connects the initializing signal of chip.
The pulse reduction unit 13 includes the 3rd comparator 131, the 4th comparator 132 and the second rest-set flip-flop 133.
131 negative input ends and 132 positive input terminal are connected to the upper end of transformer secondary, and 131 positive input terminates larger reference voltage
VH, 132 negative input terminates less reference voltage；The output end of the two connects the S inputs of the second rest-set flip-flop 133 respectively
End and R input, the input of the output termination secondary push-pull drive unit 19 of second rest-set flip-flop.
Operation principle is as follows：
Control signal is modulated to correspondence by edge pulse modulation unit 15 and rises edge and trailing edge thereon during normal transmission
Burst pulse be sent to push-pull drive unit 16, it is 15V burst pulse to coupling change to carry out output high level after level conversion
The upper end input and lower end input of depressor.Wherein, upper end input receives rising edge burst pulse, under lower end input is received
Drop is along burst pulse, because the lower end of transformer secondary is fixed to 10V power supplys, what secondary upper end was received corresponds to rising
Edge and the respectively 25V burst pulse and 0V low level burst pulse of trailing edge.25V burst pulse causes comparator 131 to export
It is " 1 " by the Q output set of the second rest-set flip-flop for high level, 0V low level burst pulse causes the output of comparator 132
High level, " 0 " is reset to by 133 Q output, so as to realize the reduction of control signal.Control signal passes through push-pull drive 19
Afterwards, IGBT22 break-make is driven.
When a failure occurs it, occurs protection act.By taking over current fault as an example, when excessively stream, collector voltage liter occur for IGBT
Height, the anode voltage of TVS pipe 23 is equally raised, when the threshold value set in more than over-current detection unit 18,18 output low levels
Fault-signal.Fault secure circuit is protected according to failure duration selection drop grid voltage or soft switching.While making protection
The burst pulse for being modulated to correspond to its trailing edge and rising edge by fault status signal is output to failure sequence generation unit 12.Therefore
Barrier feedback and processing procedure start to start.
Specific failure feedback and processing procedure are as follows：
Failure sequence generation unit acquiescence receives first burst pulse and represents that IGBT breaks down, and receives second burst pulse
Represent IGBT failture evacuations.Burst pulse by the output set of the first rest-set flip-flop 1212, above-mentioned first charging capacitor 128 it is initial
State is 0V, then first comparator 126 initially exports high level, and the first NAND gate 1210 exports low level by first switch NMOS
Shut-off.First current source 127 starts to charge to the first electric capacity, when charging voltage reaches VREFWhen, the output low level of comparator 126,
The output end of NAND gate 1210 is caused to be changed into high level after the constant time lag of delayer 1211, the first NMOS tube is opened fast
Speed is by the voltage pull-down on the first electric capacity, and first comparator exports high level again.Such repetitive operation, so that first comparator is defeated
Go out continuous low level burst pulse.The high level lasting time T of burst pulseHBy the capacitance C of electric capacity 1281, current source 127 electric current
I1With reference voltage VREFDetermine：
The low duration T of burst pulseLBy the delay time T of delayer 1211DIt is determined that：TL=TD。
This burst pulse is input in the first phase inverter 123 and the one or four digit counter 125.The original state of counter 125
Low level is exported, output high level is to first input with door 122 after the second phase inverter 124, first and door
Another input receive the high level narrow pulse sequence that phase inverter 123 is exported, then first will with door output high level burst pulse
Trombone slide 121 is open-minded under first high pressure NMOS, and the upper end of coupling transformer secondary is continuously dragged down into generation corresponds to the narrow arteries and veins of high level
The low level pulse sequence of punching.Meanwhile, high level is exported after four digit counters 125 receive four burst pulses, and produce
The narrow pulse signal of Self-resetting resets four digit counters, while the R that reset pulse is output into the first rest-set flip-flop 1212 is defeated
Enter end, Q output is reset to low level.So as to which the first NAND gate 1210 output high level opens first switch NMOS tube 129
It is logical, the current potential on the first charging capacitor 128 is dragged down, above-mentioned down pulse Sequence Generation circuit is stopped.Hereafter, failure is protected
Protection circuit exports the narrow pulse signal that next representing fault is excluded, and pulse train generation circuit, which produces to represent, recovers the narrow of signal
Pulse train.
After down pulse sequence is sent to the main side of coupling transformer, is detected by push-pull driver circuit and be output to event
Hinder processing unit 11.First liang of digit counter 112 in fault processing unit is started counting up after receiving first pulse.
The CP ends of the second d type flip flop 118 receive described pulse train simultaneously, are by Q output set since first pulse
High level, so that second switch NMOS tube 115 be turned off.Second current source 114 starts to charge to the second charging capacitor 116, when
Charging potential reaches VREFWhen, the second comparator output low level resets two digit counters 112.Simultaneously by narrow-pulse generator
119 one low level burst pulse of generation reset the second d type flip flop 118, thus second switch NMOS tube 115 is open-minded, will
The current potential of charging capacitor 116 is dragged down.If first liang of digit counter 112 is charged to V in the second electric capacityREFTime TPIt is interior to examine
Two down pulses are measured, then exports a burst pulse and triggers the first d type flip flop 111, while two digit counter is resetted.
116 are charged to VREFTime fixed timing time T is determinedP：
Wherein, C2For the capacitance of electric capacity 116, I2The electric current exported for current source 114.
The inverted Q output of first d type flip flop produces what a low level shielded signal sent control chip
Control signal is masked.Hereafter, fault processing unit is defaulted as recovering signal, two countings if narrow pulse sequence is detected again
The burst pulse that device 112 is produced triggers the first d type flip flop 111, and inverted Q output is changed into high level, that is, recovers the biography of control signal
It is defeated.
Fig. 2 workflow diagram gives fault-signal and recovers the regeneration processes and processing procedure of signal.Fig. 3 is then provided
Type signal in main side fault logic circuits, wherein pulse train above represents fault-signal and recovers signal respectively,
Middle sawtooth waveforms is timing waveform, and square wave below is the waveform of the shielded signal produced.
The implementation of the present invention is not limited to this, according to the above, according to the ordinary technical knowledge of this area and usual
Means, under the premise of above-mentioned basic fundamental thought of the invention is not departed from, failure feedback of the invention and process circuit are also other
Embodiment；Therefore the present invention can also make the modification of other diversified forms, replace or change, and all fall within right of the present invention
Within protection domain.
Claims (2)
1. a kind of IGBT failures feedback and process circuit, it is characterised in that：At failure sequence generation unit and failure sequence
Unit is managed to realize；When an error occurs, failure sequence generation unit failsafe state produces failure narrow pulse sequence, and
Described failure narrow pulse sequence is sent to the failure sequence processing unit of main side control chip by coupling transformer；Main side
If the failure sequence processing unit in control chip detects the narrow arteries and veins of two or more failures within the time of setting
Sequence is rushed, then produces shielded signal and masks control signal；After failture evacuation, failure sequence generation unit malfunction
Produce and recover narrow pulse sequence, and described recovery narrow pulse sequence is sent to main side control chip by coupling transformer
Failure sequence processing unit；If the failure sequence processing unit in main side control chip detects two within the time of setting
Or more than two recovery narrow pulse sequences, then shielded signal is cancelled, recover the normal transmission of control signal；
Described failure sequence generation unit include the first drop-down high pressure NMOS pipe, first with door, the first phase inverter, second anti-phase
Device, the one or four digit counter, first comparator, the first current source, the first charging capacitor, first switch NMOS tube, first with it is non-
Door, the first delayer and the first rest-set flip-flop；The drain electrode of the first described drop-down high pressure NMOS pipe connects signal coupling transformer pair
The upper end pin on side, the grid of the first drop-down high pressure NMOS pipe connects the output end of first and door, the first drop-down high pressure NMOS pipe
Source electrode meets the reference ground VEE that secondary is powered；Described first with the output end of one of door input the first phase inverter of termination, first with
The output end of another input the second phase inverter of termination of door, the output of input the one or four digit counter of termination of the second phase inverter
End；The output end of the input termination first comparator of first phase inverter, the output end of the first comparator is accessed simultaneously
The input of one or four digit counter and the first delayer input；Output the first NAND gate of termination of first delayer
One input；The positive input termination reference voltage V of the first comparatorREF, the negative input end of first comparator connects respectively
The drain electrode of the negative terminal of one current source, first charging capacitor one end and first switch NMOS tube；The positive termination of first current source
The power supply VDDS of secondary, the grid of the first switch NMOS tube connects the output end of first NAND gate, described first
The other end of the source electrode and first charging capacitor that switch NMOS tube meets the reference ground VEE of secondary together；Described first with it is non-
Another input of door terminates the Q output of the first rest-set flip-flop；The S input termination fault secure circuits of first rest-set flip-flop
Output end, the R of the first rest-set flip-flop terminates the Self-resetting narrow pulse signal of the one or four digit counter output；
Described failure sequence processing unit includes the first d type flip flop, first liang of digit counter, the second comparator, second electric current
Source, the second charging capacitor, second switch NMOS tube, the 3rd phase inverter, the first narrow-pulse generator and the second d type flip flop；It is described
The power supply VDD of the D input termination primary sides of second d type flip flop, the triggering end CP of second d type flip flop receive main side and recommended
Drive the failure narrow pulse sequence that detects or recover narrow pulse sequence, it is narrow that the reset terminal CLR of second d type flip flop connects first
The output end of impulse generator, the Q output of second d type flip flop connects the input of the 3rd phase inverter；Described 3rd is anti-phase
The grid of the output termination second switch NMOS tube of device, the drain electrode of the second switch NMOS tube connects the negative of the second current source respectively
The negative input end at end, one end of the second charging capacitor and the second comparator, the source electrode of the second NMOS tube and the second charging capacitor
The main side of another termination reference ground VSS；The positive input termination reference voltage V of second comparatorREF, the second comparator
The input of output the first narrow-pulse generator of termination and the Enable Pin EN of first liang of digit counter；First liang of digit counter
Another input receives failure narrow pulse sequence or recovers narrow pulse sequence, and the output of first liang of digit counter terminates the first D and touched
Send out the CP triggering ends of device.
2. a kind of IGBT failures feedback according to claim 1 and process circuit, it is characterised in that：The first described D is touched
Hair device is connected into the form of frequency divider, i.e. the inverted Q output of the first described d type flip flop is connected to D inputs, and reset terminal CLR connects
The initializing signal of chip.
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| CN201510108527.0A CN104767506B (en) | 2015-03-12 | 2015-03-12 | A kind of IGBT failures feedback and process circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108376967A (en) * | 2018-02-23 | 2018-08-07 | 扬州海通电子科技有限公司 | A kind of multiple-channel output low voltage difference overcurrent protector |
| EP3584737B1 (en) * | 2018-06-19 | 2022-02-23 | Secure-IC SAS | Improved detection of laser fault injection attacks on cryptographic devices |
| CN110501555A (en) * | 2019-08-22 | 2019-11-26 | 江阴市六和智能设备有限公司 | A kind of parallel IGBT delay current foldback circuit based on saturation voltage drop detection |
| CN110572142A (en) * | 2019-08-22 | 2019-12-13 | 宜宾市叙芯半导体有限公司 | edge conversion method and coding and decoding circuit applied to integrated magnetic isolation chip |
| CN112147481B (en) * | 2020-11-27 | 2021-02-05 | 杭州飞仕得科技有限公司 | IGBT fault return circuit and electronic equipment |
| CN112394713A (en) * | 2021-01-20 | 2021-02-23 | 杭州飞仕得科技有限公司 | Fault classification method and fault classification system |
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| CN201266914Y (en) * | 2008-08-22 | 2009-07-01 | 比亚迪股份有限公司 | Driver circuit of IGBT |
| CN202488417U (en) * | 2012-02-22 | 2012-10-10 | 常熟开关制造有限公司(原常熟开关厂） | Anti-jamming protection circuit |
| CN103337835A (en) * | 2013-06-07 | 2013-10-02 | 国家电网公司 | Circuit used for IGBT fault protection and self resetting |
| CN104270129A (en) * | 2014-09-26 | 2015-01-07 | 永济新时速电机电器有限责任公司 | IGBT driving receiving and fault feedback circuit of converter |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4246965B2 (en) * | 2002-05-31 | 2009-04-02 | 株式会社日立製作所 | Semiconductor integrated circuit device |
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2015
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201266914Y (en) * | 2008-08-22 | 2009-07-01 | 比亚迪股份有限公司 | Driver circuit of IGBT |
| CN202488417U (en) * | 2012-02-22 | 2012-10-10 | 常熟开关制造有限公司(原常熟开关厂） | Anti-jamming protection circuit |
| CN103337835A (en) * | 2013-06-07 | 2013-10-02 | 国家电网公司 | Circuit used for IGBT fault protection and self resetting |
| CN104270129A (en) * | 2014-09-26 | 2015-01-07 | 永济新时速电机电器有限责任公司 | IGBT driving receiving and fault feedback circuit of converter |
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| CN104767506A (en) | 2015-07-08 |
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