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CN104750885A - Method for pre-distributing wiring resources for pins in integrated circuit layout wiring - Google Patents

Method for pre-distributing wiring resources for pins in integrated circuit layout wiring Download PDF

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Publication number
CN104750885A
CN104750885A CN201310735842.7A CN201310735842A CN104750885A CN 104750885 A CN104750885 A CN 104750885A CN 201310735842 A CN201310735842 A CN 201310735842A CN 104750885 A CN104750885 A CN 104750885A
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CN
China
Prior art keywords
wiring
gauze
wire
resources
pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310735842.7A
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Chinese (zh)
Inventor
敖健常
贾艳明
陆涛涛
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Beijing CEC Huada Electronic Design Co Ltd
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Beijing CEC Huada Electronic Design Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Beijing CEC Huada Electronic Design Co Ltd filed Critical Beijing CEC Huada Electronic Design Co Ltd
Priority to CN201310735842.7A priority Critical patent/CN104750885A/en
Publication of CN104750885A publication Critical patent/CN104750885A/en
Pending legal-status Critical Current

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Abstract

The invention provides a method for pre-distributing wiring resources for pins in integrated circuit layout wiring. The method comprises the steps of firstly pre-distributing the wiring resources for upper metal layers of all wire network pins before layout wiring and releasing previously pre-distributed wiring resources and then normally laying wire network when a certain wire is laid in the follow-up wire laying process, wherein the pre-distributed wiring resources of other wire network pines cannot be used during wire network laying. The method well gives considerate to the competition of the wiring resources of the wire networks, unreasonable embezzlement of the previous wire networks to the wiring resources of later wire networks is avoided, the influence on wiring quality of wiring sequence is greatly reduced, and design rule violations are decreased, and wiring quality is improved.

Description

Pin interconnection resource method for pre-distributing in integrated circuit diagram wiring
Technical field
Integrated circuit diagram wiring in pin pre-allocation of resources method be eda tool in domain wires design by gauze pin is carried out pre-allocation of resources and delay to discharge process line sequence dependence and interconnection resource competition method.The invention belongs to EDA design field.
Background technology
Along with semiconductor technology node enters the sub-micro epoch, the physical Design complexity of chip rear end constantly increases, to EDA(electric design automation) dependence of instrument constantly deepens.The integrated circuit diagram wiring tool of current main flow is all intended to the physical connection efficiently logic netlist of circuit converted on domain, and namely geometric figure connects; Need the requirement meeting many design rules simultaneously, as can not short circuit, minimum spacing constraint, minimum vertex-covering constraint, minimum area constraint etc.Design rule fault on domain can cause chip cannot tape out(deliver manufacture), therefore meet design rule constraints be wiring basic demand.
Circuit meshwork list is the set of gauze, and each gauze comprises a series of pin.Wiring unit requires all pins of each gauze to be connected by metal wire or through hole, makes its UNICOM.Since deep submicron process, circuit meshwork list scale, number of pins are more and more, and available metal wiring layer also gets more and more, and the geometry meeting design rule constraints how generating institute's wired network rapidly connects also more and more difficulty.Under normal circumstances, wiring unit can connect up one by one, sequentially to gauze.Different wirings time ordered pair wire bond fruit has significant impact, and multiple gauze may be fought for the interconnection resource in same region.Between the impact of time ordered pair wire bond fruit and gauze, the competition of interconnection resource blindly being connected up if do not consider to connect up, will the gauze of first cloth being caused the possible path of the gauze of rear cloth to blocking, and cause design rule to break rules greatly increasing.
Therefore we have proposed the method to pin pre-allocation of resources in domain wiring here, it by carrying out suitable pre-allocation of resources to institute's wired network pin before wiring, avoid unreasonable the fighting for of first cloth gauze to rear wiring net interconnection resource, and in wiring subsequently, decontrol such resource restriction gradually, thus greatly alleviate the impact of wiring time ordered pair wiring quality, decrease the fault of design rule, improve cloth line mass.
Summary of the invention
The present invention proposes the method for pin pre-allocation of resources, the method considers the competition to interconnection resource between wiring order dependency and gauze, before wiring, first pre-allocation of resources is carried out to all gauze pins, avoid unreasonable the occupying of first cloth gauze to rear wiring net interconnection resource, and in wiring process, decontrol such resource restriction gradually.Ignoring wiring order dependency is very large hidden danger for EDA wiring tool, will elaborate its harm and corresponding solution herein.
The definition of wiring order dependency: in order wiring, the wiring time ordered pair wiring quality of gauze has a significant impact, and the gauze of first cloth may block the possible routing path of the gauze of rear cloth, thus causes more design rule to break rules.
Fig. 1 shows the original layout of a wiring, and domain has two metal wiring layer M1 and M2, and metal interlevel is connected by through hole; Have two gauzes treating cloth: gauze A and gauze B, gauze A has pin A-1 and A-2, and gauze B has pin B-1 and B-2.In FIG, the region outside M1 layer pin is nearly all blocked by obstacle block, and therefore gauze A or gauze B can only be connected by the metal wire of through hole and M2 layer.What Fig. 2 showed is the wiring result not considering pre-allocation of resources, wherein first cloth gauze A(Fig. 2 (a)), rear cloth gauze B(Fig. 2 (b)).Can find out from Fig. 2 (a), the gauze A of first cloth corresponding for the pin B-1 via regions at M2 layer to having blocked; But for pin B-1, due to peripheral region all by wiring obstacle block and the pin of gauze A to having blocked, therefore it must be drawn through hole to M2 layer and walk metal wire at M2 layer, so, routing path with regard to result in gauze B and gauze A on M2 layer overlaps, i.e. short circuit (Fig. 2 (b)).
Ignore the harm of wiring order dependency: from Fig. 2 (a), a kind of solution removes gauze A, then first cloth gauze B, rear cloth gauze A; But more complicated also more generally situation be, gauze A has blocked the possible routing path of gauze B, and gauze C and gauze D gives the path candidate of gauze A stifled, and gauze E gives the path candidate of gauze C and gauze D stifled again,, material is thus formed a lot of dependence; Especially since Super deep submicron process; the scale of gauze collection is more and more huger (gauze quantity is up to up to ten thousand, hundreds of thousands even up to a million); the dependence that so huge net table scale can cause gauze to connect up between order becomes extremely intricate, also extremely complicated to the competition of interconnection resource between gauze.Rely on rip up and reroute simply to solve line sequence dependence and will cause a large amount of iteration of taking out stitches; And when next rip up and reroute, still face same wiring order problem.
The disposal route of wiring order dependency, namely pin interconnection resource method for pre-distributing is as follows: before connecting up, and first carries out interconnection resource predistribution to the upper metal layers of institute's wired network pin; In wiring process, when cloth gauze, first discharge the previous preallocated interconnection resource of this gauze, then normal this gauze of cloth, but other gauze pin preallocated interconnection resource can not be used, otherwise be judged to be that design rule breaks rules (although other gauze pin does not now also carry out the wiring of " truly ", " predistribution " of interconnection resource just supposes that this pin " " occupies this resource).
Fig. 3 shows the wiring result after to pin predistribution interconnection resource, still first cloth gauze A, rear cloth gauze B.First, before wiring, first corresponding pre-allocation of resources (Fig. 3 (a)) has been carried out to the upper strata metal of all pins (being pin A-1, A-2 and B-1, B-2 in figure) of gauze; When cloth gauze A subsequently, because gauze B " predistribution " interconnection resource of M2 layer respective regions, therefore gauze A needs to get around the preallocated resource area of gauze B (Fig. 3 (b)); Last gauze B is smooth cloth logical (Fig. 3 (c)) also.
Accompanying drawing explanation
The initial domain of Fig. 1: gauze A and B with wiring order dependency
Fig. 2 does not consider pin interconnection resource preallocated wiring result: first cloth gauze A, rear cloth gauze B
Fig. 3 is the wiring result after pin predistribution interconnection resource: first cloth gauze A, rear cloth gauze B
concrete implementation step
Illustrate by carrying out interconnection resource method for pre-distributing to pin in conjunction with a concrete example, operating process is as follows:
1) circuit unit library file is prepared, the circuit meshwork list file of record annexation;
2) prepare some layout datas before wiring, as layout result, generate wiring tracks etc.;
3) interconnection resource predistribution is carried out to the upper metal layers of institute's wired network pin;
4) order wiring is carried out to institute's wired network, and decontrol the restriction of the interconnection resource to pin belonging to it when cloth wall scroll gauze;
Carry out follow-up Route step, as rip up and reroute etc.

Claims (2)

1. pin interconnection resource method for pre-distributing in integrated circuit diagram wiring, the principal character relating to EDA design tool is:
(1) before domain wiring, interconnection resource predistribution is carried out to the upper metal layers of institute's wired network pin;
(2) in wiring process, when cloth gauze, first discharge the previous preallocated interconnection resource of this gauze, then normal this gauze of cloth, can not use other gauze pin preallocated interconnection resource when this gauze of cloth.
2. the combination of claimed feature (1) and (2).
CN201310735842.7A 2013-12-29 2013-12-29 Method for pre-distributing wiring resources for pins in integrated circuit layout wiring Pending CN104750885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310735842.7A CN104750885A (en) 2013-12-29 2013-12-29 Method for pre-distributing wiring resources for pins in integrated circuit layout wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310735842.7A CN104750885A (en) 2013-12-29 2013-12-29 Method for pre-distributing wiring resources for pins in integrated circuit layout wiring

Publications (1)

Publication Number Publication Date
CN104750885A true CN104750885A (en) 2015-07-01

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109684731A (en) * 2018-12-25 2019-04-26 福州大学 A kind of efficient detailed routing driving track allocation algorithm
CN111027275A (en) * 2019-12-19 2020-04-17 北京华大九天软件有限公司 Pin connection preprocessing method meeting minimum groove constraint
CN114556352A (en) * 2019-08-12 2022-05-27 美商新思科技有限公司 Method and system for performing automatic wiring
CN115983183A (en) * 2022-12-28 2023-04-18 上海华大九天信息科技有限公司 Method for placing pins in integrated circuit layout design

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US6487706B1 (en) * 2000-08-30 2002-11-26 International Business Machines Corporation Contract methodology for concurrent hierarchical design
CN101421733A (en) * 2006-03-24 2009-04-29 新思公司 Carry out the FPGA wiring by keeping long transmission line and shared long transmission line
CN103246554A (en) * 2013-04-10 2013-08-14 上海安路信息科技有限公司 Wiring method and wiring system on basis of graphics processing units
CN103366029A (en) * 2012-03-31 2013-10-23 中国科学院微电子研究所 On-site programmable gate array chip layout method

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US6487706B1 (en) * 2000-08-30 2002-11-26 International Business Machines Corporation Contract methodology for concurrent hierarchical design
CN101421733A (en) * 2006-03-24 2009-04-29 新思公司 Carry out the FPGA wiring by keeping long transmission line and shared long transmission line
CN103366029A (en) * 2012-03-31 2013-10-23 中国科学院微电子研究所 On-site programmable gate array chip layout method
CN103246554A (en) * 2013-04-10 2013-08-14 上海安路信息科技有限公司 Wiring method and wiring system on basis of graphics processing units

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Title
杜昶旭: "面向模拟和数模混合集成电路的自动布线方法研究", 《中国博士学位论文全文数据库 信息科技辑》 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109684731A (en) * 2018-12-25 2019-04-26 福州大学 A kind of efficient detailed routing driving track allocation algorithm
CN109684731B (en) * 2018-12-25 2022-06-14 福州大学 Efficient detailed wiring driving track distribution method
CN114556352A (en) * 2019-08-12 2022-05-27 美商新思科技有限公司 Method and system for performing automatic wiring
CN111027275A (en) * 2019-12-19 2020-04-17 北京华大九天软件有限公司 Pin connection preprocessing method meeting minimum groove constraint
CN115983183A (en) * 2022-12-28 2023-04-18 上海华大九天信息科技有限公司 Method for placing pins in integrated circuit layout design
CN115983183B (en) * 2022-12-28 2024-07-30 上海华大九天信息科技有限公司 Method for placing pins in integrated circuit layout design

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Application publication date: 20150701