CN104700807A - Data transmission device of embedded clock point-to-point transmission architecture and data transmission method - Google Patents
Data transmission device of embedded clock point-to-point transmission architecture and data transmission method Download PDFInfo
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Abstract
The invention provides a data transmission device of an embedded clock point-to-point transmission architecture for a liquid crystal display and a data transmission method. The method comprises the steps as follows: a first timing sequence generation unit provides a first clock signal; a first data processor packages the data to be transmitted into a series of packets according to the first clock signal; the first data processor encodes each packet to obtain encoded data; a second timing sequence generation unit provides a second clock signal; a second data processor decodes the packets according to the second clock signal and the encoded data to obtain the valid data of the packets. Compared with the prior art, a method of defining packet states is provided for the embedded clock point-to-point transmission architecture, the packet state information of each packet is provided by virtue of the combination of some special data bits, and therefore, the transmission between a timing sequence controller and a source driver can be elastically adjusted according to the system states and requirements.
Description
Technical Field
The present invention relates to data transmission technologies, and in particular, to a data transmission device and method for a Point-to-Point (Point-to-Point) transmission architecture of a Clock Embedded in a liquid crystal display.
Background
A Timing Controller (Tcon) and a Source Driver (SD) are two key components of the panel display Driver. In brief, the main function of the timing controller in transmitting display data is to receive an input signal (such as LVDS) with a specific format, wherein the input signal can be generated by a signal source such as a signal generator, converted by a transfer board (so-called "dongle"), properly arranged according to the number of corresponding output channels, encoded (encode) or scattered (scatter), and output to a source driver. On one side of the source driver, the main function of the source driver in transmitting the display data is to receive the signal output by the time schedule controller, analyze the display data and the setting data, write the display data into the buffer of the source driver, and drive the liquid crystal panel when the reference signal appears. Here, the setting data is mainly used to provide information required by the source driver, such as polarity, the number of channels, and the like.
In the prior art, the early transmission interface mostly adopts a "multi drop" architecture (i.e., a multi-point architecture), and the timing controller respectively routes and transmits the data signal and the clock signal to the source driver. Because Electromagnetic Interference (EMI) is large when a single Signal line is transmitted, and is not favorable for high-speed transmission, a Differential pair (Differential pair) such as a mini Low Voltage Differential Signal (mini-LVDS) interface or a Reduced Swing Differential Signal (RSDS) interface is often used for signals transmitted. As the resolution requirements of displays become higher, the requirements for data transmission become higher, for example, it is desirable that data can be transmitted faster, the wiring is more simplified, and the like. The multi-drop architecture has a significant limitation on the transmission rate, limited by the impedance matching problem. In addition, in the high frequency state, the cabling structure for transmitting the clock signal and the data signal respectively is prone to cause clock skew or skew (clock skew) problem, so that the clock signal received by the source driver cannot correctly capture valid data.
To increase the signal transmission speed, the current mainstream method is a point-to-point (point-to-point) structure, which is matched with a clock embedded signal (clock embedded signal). In addition, in order to confirm that the source driver can analyze the clock information transmitted by the timing controller, a "latch" signal can be set to display the current clock state. The action mode is as follows: when the clock signal is not locked (unlock), the opposite logic is passed back as when locked (lock). When the point-to-point transmission interface is used for operation, the timing controller firstly transmits a training code (training code) to the source driver, and Data transmission can be started until a Clock Data Recovery (CDR) circuit in the source driver returns a latch state. Furthermore, the transmission signal between the timing controller and the source driver needs to transmit the Register Setting (Register Setting) of the source driver in addition to the Display data. If a set of transmission protocols is not established, the buffer settings of the source driver can only be transmitted by adding additional hardware wiring, which consumes space and cost of a Printed Circuit Board (PCB). Although the above method can smoothly transmit the Display data and the Setting of the source driver buffer (Setting), it is not flexible. For example, once the packet number (packet number) of the buffer setting of the source driver needs to be changed, and even the transmission status needs to be added or changed in order, the transmission protocol must be redefined.
In view of the above, a need exists in the art for a flexible data transmission protocol based on an embedded clock point-to-point transmission architecture between a timing controller and a source driver to overcome the above-mentioned drawbacks and deficiencies in the prior art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art in which the timing controller and the source driver transmit the display data and the register setting value of the source driver based on the embedded clock point-to-point transmission architecture, the present invention provides a data transmission apparatus and method for the embedded clock point-to-point transmission architecture of the liquid crystal display.
According to an aspect of the present invention, a data transmission method for an embedded clock point-to-point transmission architecture, the embedded clock point-to-point transmission architecture including a timing controller and at least one source driver, is provided, wherein the data transmission method includes the following steps:
a first time sequence generating unit of the time sequence controller provides a first clock signal;
a first data processor of the time schedule controller packages data to be transmitted into a series of packets according to the received first clock signal;
the first data processor encodes each packet to obtain encoded data, wherein the encoded data is used for flexibly defining the packet state of the packet;
the second time sequence generating unit of the source driver provides a second clock signal; and
and the second data processor of the source driver decodes the coded data according to the received second clock signal and the coded data so as to obtain the effective data of the packet.
In one embodiment, the packet status of each packet corresponds to a set field, a display field, a blank field, or an end field.
In one embodiment, each packet is composed of (N-1) data bits and 1 additional bit, the 1 st data bit is a first flag bit, the 2 nd to (N-2) th data bits include at least one extended flag bit, the (N-1) th data bit is a second flag bit, and the packet status is determined as the set field, the display field, the blank field, or the end field by a combination of the first flag bit, the extended flag bit, and the second flag bit, where N is a natural number greater than 3.
In one embodiment, the determination rule for determining the setting field, the display field, the blank field, or the end field is:
when the first flag bit of the Nth packet is not equal to the second flag bit of the (N-1) th packet, the packet state corresponds to a display field;
when a first flag bit of an Nth packet is equal to a second flag bit of an (N-1) th packet and is different from an extended flag bit of the Nth packet, the packet status corresponds to a set field;
when the first flag bit of the Nth packet is equal to the second flag bit of the (N-1) th packet and the extended flag bit of the Nth packet, the packet status corresponds to a blank field; and
the packet status corresponds to the end field when all data bits in the packet are 1.
In an embodiment of the present invention, the step of encoding each packet by the first data processor to obtain an encoded data further includes: adding 1 additional bit to increase the packet from (N-1) data bits to N data bits, wherein the additional bit is used for recording the flipping action of the display field; and determining a packet status to be encoded, and adjusting the first flag bit, the second flag bit and/or the extended flag bit according to the determined packet status to conform to a status indicator (state indicator) of a corresponding field.
In an embodiment of the foregoing, the step of decoding, by the second data processor of the source driver, the encoded data according to the received second clock signal and the encoded data further includes: comparing whether the first zone bit, the second zone bit and the expansion zone bit in the packet are matched with the state indicator or not; and determining whether to flip the data bits in the packet according to the matching result, thereby taking out the valid data of the packet.
In one embodiment, when the packet status corresponds to a display field, if the additional bit is not marked to be inverted, the valid data is all data bits except the additional bit in the packet; and if the additional bit is marked to be inverted, the effective data are all data bits, except the additional bit, of the packet, of which the first flag bit is inverted.
According to another aspect of the present invention, there is provided a data transmission apparatus for an embedded clock point-to-point transmission architecture, comprising:
a timing controller having: a first timing generation unit for providing a first clock signal; the first data processor is used for packaging data to be transmitted into a series of packets according to the received first clock signal and coding each packet to obtain coded data, wherein the coded data is used for flexibly defining the packet state of the packet; and
a source driver having: a second timing generation unit for receiving the encoded data from the first data processor and providing a second clock signal; and the second data processor is used for decoding the coded data according to the received second clock signal and the coded data so as to obtain the effective data of the packet.
In one embodiment, the first data processor sequentially includes a state-defined encoder and a scrambler, and the second data processor sequentially includes a descrambler and a state-defined decoder, wherein the scrambler is electrically connected to the descrambler.
In one embodiment, the first data processor sequentially includes a scrambler and a state definition encoder, and the second data processor sequentially includes a state definition decoder and a descrambler, wherein the state definition encoder is electrically connected to the state definition decoder.
The invention relates to a data transmission device and a method for an embedded clock point-to-point transmission framework of a liquid crystal display.A first time sequence generating unit of a time schedule controller provides a first clock signal, a first data processor packages data to be transmitted into a series of packets according to the received first clock signal, and the first data processor encodes each packet to obtain encoded data, wherein the encoded data is used for flexibly defining the packet state of the packet. The second timing generation unit of the source driver provides a second clock signal, and the second data processor of the source driver decodes the encoded data according to the received second clock signal and the encoded data to obtain the effective data of the packet. Compared with the prior art, the invention provides a method for defining the packet state aiming at the embedded clock point-to-point transmission architecture, and the packet state information of each packet, such as the packet state of a display field, a set field, a blank field, an end field and the like, is endowed by the combination of some special data bits. Therefore, the source driver can compare the data bits in the received packet data with the well-defined status indicator, and determine whether to flip the data bits in the packet according to the comparison result, thereby taking out the valid data of the packet, so that the transmission between the timing controller and the source driver can be flexibly adjusted according to the system status and the requirement.
Drawings
The various aspects of the present invention will become more apparent to the reader after reading the detailed description of the invention with reference to the attached drawings. Wherein,
fig. 1 is a schematic diagram illustrating a data transmission method using a multipoint architecture in the prior art;
FIG. 2 is a diagram illustrating a prior art data transmission using a point-to-point architecture;
FIG. 3 is a schematic diagram illustrating the use of the point-to-point architecture of FIG. 2 to define the order and number of packets;
FIG. 4 is a block diagram of a data transmission apparatus based on embedded clock peer-to-peer transmission architecture and capable of flexibly defining the packet status of a packet according to an embodiment of the present invention;
FIG. 5a illustrates one embodiment of a first data processor and a second data processor in the data transmission device of FIG. 4;
FIG. 5b shows another embodiment of the first data processor and the second data processor in the data transmission device of FIG. 4;
FIG. 6 is a diagram illustrating a state of data transmission frame by frame through a packet format defined in the present invention;
FIG. 7a is a schematic diagram showing the packet distribution of the LCD device during the V-active period;
FIG. 7b is a block diagram illustrating exemplary embodiments of special flags for flexibly defining packet status of a packet according to the present invention;
FIGS. 8a to 8d are diagrams illustrating additional bit setting for the (N-1) th packet and the Nth packet, respectively;
FIGS. 9a to 9d are schematic diagrams illustrating that the first flag bit, the second flag bit and/or the extended flag bit match the status indicator of the corresponding field in the packet status of display data;
FIGS. 10a to 10f are schematic diagrams respectively illustrating that in the packet status of display data, the first flag bit, the second flag bit and/or the extended flag bit do not conform to the status indicator of the corresponding field; and
FIG. 11 is a flow chart illustrating a data transmission method based on embedded clock point-to-point transmission architecture and capable of flexibly defining the packet status of a packet according to another embodiment of the invention.
Detailed Description
In order to make the present disclosure more complete and complete, reference is made to the accompanying drawings, in which like references indicate similar or analogous elements, and to the various embodiments of the invention described below. However, it will be understood by those of ordinary skill in the art that the examples provided below are not intended to limit the scope of the present invention. In addition, the drawings are only for illustrative purposes and are not drawn to scale.
Fig. 1 is a schematic diagram illustrating a data transmission using a multipoint architecture in the prior art, fig. 2 is a schematic diagram illustrating a data transmission using a point-to-point architecture in the prior art, and fig. 3 is a schematic diagram illustrating an order and a number of packets defined using the point-to-point architecture of fig. 2.
Referring to fig. 1, as described above, when the "multi drop" architecture (i.e., the multi-drop architecture) is adopted, the timing controller routes and transmits the data signal and the clock signal to each source driver, respectively, after receiving the parallel data. Because the electromagnetic interference is larger when a single signal line is transmitted, it is not favorable for high-speed transmission. As the resolution requirement of the display is higher and higher, the requirement for data transmission is also higher and higher, but the architecture has a great limit to the transmission rate due to the limitation of the impedance matching problem.
Referring to fig. 2 and 3, in order to increase the signal transmission speed, the structure may be changed to a point-to-point structure with an embedded clock, after receiving the parallel data, the timing controller embeds the data to be transmitted into a clock signal and transmits the data to a corresponding source driver by using the same wire, and the source driver sets a "latch" signal to display the current clock state when analyzing the clock information transmitted by the timing controller. For example, in fig. 3, a clock training state is defined first, and the timing controller transmits a clock training code packet to the source driver until the source driver locks the clock signal, then directly enters the "Setting" state, and finally enters the "Display" state. In order to determine whether the content of the currently transmitted packet is the set value of the source driver register or the display data, the timing controller and the source driver first determine the number of packets, e.g., M packets as indicated in the figure, that are continuously received in the Setting state. After the transmission of the time schedule controller is finished, the Display state is entered, the transmission of Display data is started, and the number of the packets is N packets marked in the figure. Obviously, this method is not flexible, although it can smoothly transmit the display data and the setting value. Once the packet number (packet number) of the buffer setting of the source driver needs to be changed, the transmission protocol must be redefined even if the transmission status needs to be added or changed in order.
In order to solve the above problems in the prior art, the present invention provides a new data transmission device. FIG. 4 is a block diagram of a data transmission apparatus based on an embedded clock peer-to-peer transmission architecture and capable of flexibly defining a packet status of a packet according to an embodiment of the present invention.
Referring to fig. 4, the data transmission apparatus for an embedded clock point-to-point transmission architecture according to the present invention includes a timing controller 10 and at least one source driver 20.
Specifically, the timing controller 10 has a first timing generation unit and a first data processor 102. The source driver 20 has a second timing generation unit and a second data processor 202. The first timing generation unit receives a clock reference signal clk _ ref and the latch signal LOCK, and outputs a first clock signal clk _ 1. The first Data processor 102 receives parallel Data _ P and a first clock signal clk _1, so as to package Data to be transmitted into a series of packets, and encodes each packet to obtain encoded Data _ S, wherein the encoded Data _ S can flexibly define a packet state of the packet.
The second timing generation unit receives the encoded Data _ S from the first Data processor 102 and provides a second clock signal clk _2 and a latch signal LOCK. The second Data processor 202 is configured to decode the encoded Data _ S according to the received second clock signal clk _2 and the encoded Data _ S, so as to obtain valid Data of the packet.
In one embodiment, as shown in fig. 7b, each packet is composed of (N-1) data bits and 1 additional bit, the 1 st data bit is a first flag bit sp _1, the 2 nd to (N-2) th data bits include at least one extended flag bit sp _ ext, the (N-1) th data bit is a second flag bit sp _2, and the packet status is determined as a set field (Setting), a Display field (Display), a Blank field (Blank) or an end field (EOL) by the combination of the first flag bit sp _1, the extended flag bit sp _ ext and the second flag bit sp _2, where N is a natural number greater than 3. For example, N equals 9, and each packet includes 8 data bits and 1 additional bit.
In one embodiment, the determination rule for determining the setting field, the display field, the blank field, or the ending field is:
when the first flag bit of the Nth packet is not equal to the second flag bit of the (N-1) th packet, namely sp _1(N) is not equal to sp _2(N-1), the packet state corresponds to the display field;
when the first flag bit of the Nth packet is equal to the second flag bit of the (N-1) th packet and is different from the extended flag bit of the Nth packet, i.e., sp _1(N) is equal to sp _2(N-1) and is not equal to sp _ ext (N), the packet status corresponds to the set field;
when the first flag bit of the Nth packet is equal to the second flag bit of the (N-1) th packet and the extended flag bit of the Nth packet, i.e., sp _1(N) is equal to sp _2(N-1) and equal to sp _ ext (N), the packet status corresponds to a blank field; and
the packet status corresponds to the end field when all data bits in the packet are 1.
Fig. 5a shows a specific embodiment of the first data processor and the second data processor in the data transmission device of fig. 4, and fig. 5b shows another specific embodiment of the first data processor and the second data processor in the data transmission device of fig. 4.
Referring to fig. 5a, in this embodiment, the first data processor 102 sequentially includes a state-defined encoder and a scrambler, and the second data processor 202 sequentially includes a descrambler and a state-defined decoder, the scrambler being electrically connected to the descrambler.
Referring to fig. 5b, in this embodiment, the first data processor 102 sequentially comprises a scrambler and a state definition encoder, and the second data processor 202 sequentially comprises a state definition decoder and a descrambler, wherein the state definition encoder and the state definition decoder are electrically connected. As can be seen from fig. 5a and 5b, the scrambler is a unit for data scattering, which aims to provide better balance and avoid high EMI caused by repetitive data patterns.
Fig. 6 is a diagram illustrating a state of data transmission frame by frame through a packet format defined in the present invention.
Referring to fig. 6, a state after the data transfer apparatus starts from power on is described. Initial is the period before the system has not entered the first V-active (i.e., V-active (1)). In the Initial period, the timing controller starts to transmit the clock training code packet to the source driver after being powered on, until the source driver returns a latch signal "Lock" to inform the timing controller that the clock information is locked, the Initial period is not ended, and the first V-active period is entered. The states transmitted in V-active are the source driver Setting (Setting), Display data (Display), clock correction interval (Blank), and End of Line (EOL), respectively. In the V-Blank interval, the state combination of each scan Line may be defined as a source driver Setting (Setting), a clock correction interval (Blank), and an End of Line (EOL). Furthermore, during clock training, two situations can occur: 1) the Lock signal is low, which indicates that the clock signal is not locked, and the timing controller immediately transmits the training code; 2) the Lock signal is high, and the timing controller sets the register value in the "Setting" period and informs the source driver to start clock training in the next scan line.
FIG. 7a is a schematic diagram showing the packet distribution of the LCD device during the V-active period, and FIG. 7b is a schematic diagram showing various special flags for flexibly defining the packet status of the packet according to the present invention.
Referring to fig. 7a and 7b, the state distribution of the display in the V-active interval is described. In the Nth scan line case, each of the N scan lines is divided into H-active and H-blank intervals, wherein H-active interval transmission source driver Setting (Setting) and Display data (Display) can be defined. The H-blank interval is the interval between the start time position and clock calibration for the source driver to write the analog signal to the panel. Each strip may define an end field to indicate the end of the packet and then begin transmitting the next data transmission.
In FIG. 7b, each packet has an extra bit (sp) and a plurality of data bits are defined as special bits (sp). For example, the original packet is (N-1) bit, and becomes N bit after adding an additional bit. In addition, bit1, bit2 and bit (N-1) are defined as a first flag sp _1, an extended flag sp _ ext and a second flag sp _2, respectively.
FIGS. 8a to 8d are diagrams illustrating additional bit setting for the (N-1) th packet and the Nth packet, respectively.
In FIG. 8a, the (N-1) th packet includes 8 data bits, and the incoming packet is added with 1 extra bit (overhead bit), and the packet becomes 9 data bits, as shown in FIG. 8 b. The additional bit is used to record the "flip packet" action in the display data state, and when the additional bit is 1, some bits in the packet are flipped, including sp _ 1. Similarly, in FIG. 8c, the (N) th packet includes 8 data bits, and the input packet is added with 1 extra bit (overhead bit), and the packet becomes 9 data bits, as shown in FIG. 8 d.
Fig. 9a to 9d are schematic diagrams respectively illustrating that in the packet state of display data, the first flag bit, the second flag bit and/or the extended flag bit match the status indicator of the corresponding field.
Referring to fig. 9a to 9d, if the packet status is display data and the data bits of the packet completely match the status indicator (state indicator) of the display data, i.e., sp _1(N) is 1, sp _2(N-1) is 0, and sp _1(N) is not equal to sp _2 (N-1); in other words, sp _1(N-1) is 0, sp _2(N-2) is 1, and sp _1(N-1) is not equal to sp _2(N-2), so that no flip operation is required for any data bit of the packet, and the overhead bits (N) and (N-1) are both set to 0. On the contrary, in the process of data Decoding (Decoding), for the combination, the packet data does not need to be inverted, and the valid data is 8 bits except the overhead bit.
Fig. 10a to 10f are schematic diagrams respectively illustrating that the first flag bit, the second flag bit and/or the extended flag bit do not conform to the status indicator of the corresponding field in the packet state of the display data.
Referring to fig. 10a to 10f, if the packet status is display data and the data bits of the packet do not match the status indicator (state indicator) of the display data, i.e., sp _1(N) is 0, sp _2(N-1) is 0, and sp _1(N) is equal to sp _2(N-1), the packet needs to be flipped. At this time, the extra bits overhead bit (N) and (N-1) should be set to "1" first, marking the packet as being flipped. The packet (N) is then flipped, which necessarily includes a first flag sp _1 (N). This embodiment is only to
The overhead bit flag toggles sp _1(N), which is found to be inverted, i.e. to match the packet status definition of the display data, e.g. sp _1(N) changes from "0" in FIG. 10e to "1" in FIG. 10 f. On the contrary, in the process of data Decoding (Decoding), since the overhead bit is marked with the inversion state, after the current packet is confirmed to be in the display state according to the description of the state indicator and the combination of the specific bits, the corresponding data inversion can be performed. Wherein the effective data is 8 bits except the overhead bit. Referring to fig. 10a to 10f, since only sp _1(N) is inverted in the process of data Encoding (Encoding), only sp _1(N) needs to be inverted in the process of reduction.
FIG. 11 is a flow chart illustrating a data transmission method based on embedded clock point-to-point transmission architecture and capable of flexibly defining the packet status of a packet according to another embodiment of the invention.
Referring to fig. 11 in conjunction with fig. 4, in the data transmission method, step S11 is first executed, and the first timing generation unit of the timing controller 10 provides a first clock signal clk _ 1; then, in step S13, the first data processor 102 of the timing controller 10 packages the data to be transmitted into a series of packets according to the received first clock signal clk _ 1; then, in step S15, the first Data processor 102 encodes each packet to obtain encoded Data _ S, where the encoded Data is used to flexibly define the packet status of the packet; then, in step S17, the second timing generation unit of the source driver 20 provides a second clock signal clk _ 2; finally, in step S19, the second Data processor 202 of the source driver 20 decodes the encoded Data according to the received second clock signal clk _2 and the encoded Data _ S to obtain the valid Data of the packet.
In one embodiment, the step of encoding each packet by the first data processor to obtain an encoded data further includes: adding 1 additional bit to increase the packet from (N-1) data bits to N data bits, wherein the additional bit is used for recording the flipping action of the display field; and determining the packet state to be encoded, and adjusting the first flag bit, the second flag bit and/or the extended flag bit according to the determined packet state to make the first flag bit, the second flag bit and/or the extended flag bit conform to the state indicator of the corresponding field.
In a specific embodiment, the step of decoding the encoded data by the second data processor of the source driver according to the received second clock signal and the encoded data further includes: comparing whether the first zone bit, the second zone bit and the expansion zone bit in the packet are matched with the state indicator or not; and determining whether to flip the data bits in the packet according to the matching result, thereby taking out the valid data of the packet.
The invention relates to a data transmission device and a method for an embedded clock point-to-point transmission framework of a liquid crystal display.A first time sequence generating unit of a time schedule controller provides a first clock signal, a first data processor packages data to be transmitted into a series of packets according to the received first clock signal, and the first data processor encodes each packet to obtain encoded data, wherein the encoded data is used for flexibly defining the packet state of the packet. The second timing generation unit of the source driver provides a second clock signal, and the second data processor of the source driver decodes the encoded data according to the received second clock signal and the encoded data to obtain the effective data of the packet. Compared with the prior art, the invention provides a method for defining the packet state aiming at the embedded clock point-to-point transmission architecture, and the packet state information of each packet, such as the packet state of a display field, a set field, a blank field, an end field and the like, is endowed by the combination of some special data bits. Therefore, the source driver can compare the data bits in the received packet data with the well-defined status indicator, and determine whether to flip the data bits in the packet according to the comparison result, thereby taking out the valid data of the packet, so that the transmission between the timing controller and the source driver can be flexibly adjusted according to the system status and the requirement.
Hereinbefore, specific embodiments of the present invention are described with reference to the drawings. However, those skilled in the art will appreciate that various modifications and substitutions can be made to the specific embodiments of the present invention without departing from the spirit and scope of the invention. Such modifications and substitutions are intended to be included within the scope of the present invention as defined by the appended claims.
Claims (10)
1. A data transmission method for an embedded clock point-to-point transmission architecture, the embedded clock point-to-point transmission architecture comprising a timing controller and at least one source driver, the data transmission method comprising the steps of:
a first time sequence generating unit of the time sequence controller provides a first clock signal;
a first data processor of the time schedule controller packages data to be transmitted into a series of packets according to the received first clock signal;
the first data processor encodes each packet to obtain encoded data, wherein the encoded data is used for flexibly defining the packet state of the packet;
the second time sequence generating unit of the source driver provides a second clock signal; and
and the second data processor of the source driver decodes the coded data according to the received second clock signal and the coded data so as to obtain the effective data of the packet.
2. The data transmission method of claim 1, wherein the packet status of each packet corresponds to a set field, a display field, a blank field, or an end field.
3. The data transmission method according to claim 2, wherein each packet is composed of (N-1) data bits and 1 additional bit, the 1 st data bit is a first flag bit, the 2 nd to (N-2) th data bits include at least one extended flag bit, the (N-1) th data bit is a second flag bit, and the packet status is determined as the set field, the display field, the blank field, or the end field by a combination of the first flag bit, the extended flag bit, and the second flag bit, where N is a natural number greater than 3.
4. The data transmission method according to claim 3, wherein the determination rule for determining the setting field, the display field, the blank field or the end field is:
when the first flag bit of the Nth packet is not equal to the second flag bit of the (N-1) th packet, the packet state corresponds to a display field;
when a first flag bit of an Nth packet is equal to a second flag bit of an (N-1) th packet and is different from an extended flag bit of the Nth packet, the packet status corresponds to a set field;
when the first flag bit of the Nth packet is equal to the second flag bit of the (N-1) th packet and the extended flag bit of the Nth packet, the packet status corresponds to a blank field; and
the packet status corresponds to the end field when all data bits in the packet are 1.
5. The data transmission method of claim 4, wherein the step of the first data processor encoding each packet to obtain an encoded data further comprises:
adding 1 additional bit to increase the packet from (N-1) data bits to N data bits, wherein the additional bit is used for recording the flipping action of the display field; and
and determining the packet state to be coded, and adjusting the first zone bit, the second zone bit and/or the extended zone bit according to the determined packet state to enable the first zone bit, the second zone bit and/or the extended zone bit to accord with the state indicator of the corresponding field.
6. The data transmission method of claim 1, wherein the step of decoding the encoded data by the second data processor of the source driver according to the received second clock signal and the encoded data further comprises:
comparing whether the first zone bit, the second zone bit and the expansion zone bit in the packet are matched with the state indicator or not; and
and determining whether to flip the data bits in the packet according to the matching result so as to take out the valid data of the packet.
7. The data transmission method according to claim 6, wherein when the packet status corresponds to a display field,
if the additional bit is not marked to be turned over, the valid data is all data bits except the additional bit in the packet;
and if the additional bit is marked to be inverted, the effective data are all data bits, except the additional bit, of the packet, of which the first flag bit is inverted.
8. A data transmission apparatus for an embedded clock point-to-point transmission architecture, the data transmission apparatus comprising:
a timing controller having: a first timing generation unit for providing a first clock signal; the first data processor is used for packaging data to be transmitted into a series of packets according to the received first clock signal and coding each packet to obtain coded data, wherein the coded data is used for flexibly defining the packet state of the packet; and
a source driver having: a second timing generation unit for receiving the encoded data from the first data processor and providing a second clock signal; and the second data processor is used for decoding the coded data according to the received second clock signal and the coded data so as to obtain the effective data of the packet.
9. The data transmission apparatus of claim 8, wherein the first data processor comprises a state-defined coder and a scrambler, and the second data processor comprises a descrambler and a state-defined decoder, wherein the scrambler is electrically connected to the descrambler.
10. The data transmission apparatus of claim 8, wherein the first data processor comprises a scrambler and a state definition encoder in sequence, and the second data processor comprises a state definition decoder and a descrambler in sequence, wherein the state definition encoder is electrically connected to the state definition decoder.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016177078A1 (en) * | 2015-07-20 | 2016-11-10 | 中兴通讯股份有限公司 | Method and system for processing announcement messages |
| CN108694897A (en) * | 2017-06-09 | 2018-10-23 | 京东方科技集团股份有限公司 | Drive control method, component and display device |
| CN109036328A (en) * | 2017-06-09 | 2018-12-18 | 京东方科技集团股份有限公司 | Register value transmission method and component, display device |
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| CN115457904A (en) * | 2022-05-05 | 2022-12-09 | 友达光电股份有限公司 | Display driving system and related display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016177078A1 (en) * | 2015-07-20 | 2016-11-10 | 中兴通讯股份有限公司 | Method and system for processing announcement messages |
| CN106375242A (en) * | 2015-07-20 | 2017-02-01 | 中兴通讯股份有限公司 | Notification message processing method and system |
| CN106375242B (en) * | 2015-07-20 | 2020-09-08 | 中兴通讯股份有限公司 | Notification message processing method and system |
| CN108694897A (en) * | 2017-06-09 | 2018-10-23 | 京东方科技集团股份有限公司 | Drive control method, component and display device |
| CN109036328A (en) * | 2017-06-09 | 2018-12-18 | 京东方科技集团股份有限公司 | Register value transmission method and component, display device |
| CN109036328B (en) * | 2017-06-09 | 2021-09-03 | 京东方科技集团股份有限公司 | Register value transmission method and assembly and display device |
| US11302281B2 (en) | 2017-06-09 | 2022-04-12 | Beijing Boe Display Technology Co., Ltd. | Register value transmission method and transmitter, display device and computer readable storage medium |
| CN110223643A (en) * | 2018-03-01 | 2019-09-10 | 京东方科技集团股份有限公司 | Data transmission method, component and system, display device |
| CN110223643B (en) * | 2018-03-01 | 2022-02-11 | 京东方科技集团股份有限公司 | Data transmission method, assembly and system and display device |
| CN115457904A (en) * | 2022-05-05 | 2022-12-09 | 友达光电股份有限公司 | Display driving system and related display device |
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