CN104658933A - POP structure applying lamination process and preparation method thereof - Google Patents
POP structure applying lamination process and preparation method thereof Download PDFInfo
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- CN104658933A CN104658933A CN201410843559.0A CN201410843559A CN104658933A CN 104658933 A CN104658933 A CN 104658933A CN 201410843559 A CN201410843559 A CN 201410843559A CN 104658933 A CN104658933 A CN 104658933A
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- package body
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/732—Location after the connecting process
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/151—Die mounting substrate
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- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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Abstract
The invention discloses a POP (Package on Package) structure applying the lamination process and a preparation method thereof. The POP structure comprises a lower packaging body and an upper packaging body, wherein the lower packaging body mainly consists of a lower packaging body baseplate, a bonding pad, welded ball convex points, a chip, welded balls on the upper surface of the lower packaging body substrate, a plastic package body and welded balls on the lower surface of the lower packaging body baseplate; the upper packaging body mainly consists of an upper packaging body baseplate, a bonding pad, welded ball convex points, an upper packaging body chip, a bottom filling adhesive and welded balls on the lower surface of the upper packaging body baseplate. The preparation method comprises the following steps: interconnecting a lower packaging body baseplate and a chip, manufacturing welded balls on the upper surface of the lower packaging body baseplate, laminating the upper surfaces of the welded balls, conducting plastic-packaging and post curing, uncovering a film, manufacturing welded balls on the lower surface of the lower packaging body baseplate, and welding a lower packaging body and an upper packaging body. The manufacture process is simplified, the cost is lowered, the thicknesses of the packaging bodies are reduced, the I/O density is increased and the packaging efficiency is improved at the same time.
Description
Technical field
The present invention relates to field of semiconductor package, particularly relate to a kind of POP encapsulating structure using film coating process and preparation method thereof.
Background technology
POP encapsulation is the very typical semiconductor stack encapsulation of one, and in logical circuit and memory area, it is by the first-selection as industry, is mainly used in the advanced mobile communication platform manufacturing high-end portable formula equipment and smart mobile phone use.Traditional POP encapsulating structure, the preparation of its lower package body and the interconnected window of upper packaging body, normally first plastic packaging is carried out to lower encapsulating structure, then the method for laser ablation is utilized to slot at lower package body (in correspondence packaging body base lower surface soldered ball position) upper surface, this groove is identical with lower package body upper surface pad locations, expose the soldered ball that is pre-existing in or in groove, carry out paste solder printing and plant ball, finally for carrying out solder interconnections with upper packaging body.
But method described above, in the processing procedure process of existing POP, need fluting and the method by solder printing formation interconnection soldered ball on plastic-sealed body, complex manufacturing technology, and cost is higher.
Summary of the invention
The preparation that the present invention is directed to packaging body in POP encapsulating structure provides a kind of POP encapsulating structure using film coating process and preparation method thereof, by first forming soldered ball at lower package body upper surface, then film coating process is carried out at solder ball surface, carry out plastic packaging process, thus ensure that after completing plastic packaging process, the upper surface of soldered ball exposes outside plastic-sealed body, and convenient and upper strata packaging body interconnects.Avoid plastic-sealed body fluting and to the processing step carrying out fill solder in groove, it is simple that the present invention has manufacture craft, low cost, low package thickness, high I/O density, the advantage of high yield.
Use a POP encapsulating structure for film coating process, described structure comprises lower package body and upper packaging body, lower package body is primarily of lower package body substrate, pad, solder bumps, chip, lower package body upper surface of base plate soldered ball, plastic-sealed body and lower package body base lower surface soldered ball composition, the lower surface of described lower package body substrate is connected with lower package body base lower surface soldered ball by pad, the pad of described lower package body upper surface of base plate there is solder bumps, described chips welding is in solder bumps, the pad of described lower package body upper surface of base plate also has lower package body upper surface of base plate soldered ball, described plastic-sealed body parcel solder bumps, the lower part of chip and lower package body upper surface of base plate soldered ball,
Upper packaging body forms primarily of the solder bumps of upper packaging body substrate, pad, upper packaging body, upper packaging body chip, underfill and upper packaging body base lower surface soldered ball, the lower surface of described upper packaging body substrate is connected with upper packaging body base lower surface soldered ball by pad, the pad of described upper packaging body upper surface of base plate there is the solder bumps of upper packaging body, described upper packaging body chips welding is in the solder bumps of upper packaging body, and described underfill superscribes the part of the solder bumps of packaging body, the part of upper packaging body chip and upper packaging body substrate; Described lower package body upper surface of base plate soldered ball and the mutual wielding neck of upper packaging body base lower surface soldered ball.
Use a preparation method for the POP encapsulating structure of film coating process, its technical process is: lower package body substrate and the chip interconnects on it → lower package body upper surface of base plate make soldered ball → soldered ball upper surface pad pasting → plastic packaging and Post RDBMS → take off film → lower package body base lower surface to make soldered ball → lower package body and weld with upper packaging body.
Use a preparation method for the POP encapsulating structure of film coating process, specifically carry out in accordance with the following steps:
Steps A: core and Reflow Soldering in the upside-down mounting of lower package body upper surface of base plate, lower package body substrate forms current path by pad, solder bumps and chip interconnects;
Step B: make soldered ball at the welding disking area of lower package body upper surface of base plate, form lower package body upper surface of base plate soldered ball, lower package body upper surface of base plate soldered ball be greater than chip with the height of lower package body upper surface of base plate with the height of lower package body upper surface of base plate;
Step C: at lower package body upper surface of base plate soldered ball upper surface rubberizing film, make part lower package body upper surface of base plate soldered ball be absorbed in the glue-line of glued membrane;
Step D: to lower package body plastic packaging, the lower part of described plastic-sealed body parcel solder bumps, chip and lower package body upper surface of base plate soldered ball;
Step e: take off glued membrane, exposes the upper surface of lower package body upper surface of base plate soldered ball;
Step F: make soldered ball at the welding disking area of lower package body base lower surface, forms lower package body base lower surface soldered ball;
Step G: upper packaging body substrate is by the solder bumps of pad, upper packaging body and upper packaging body chip interconnects, underfill coated interconnect area, soldered ball is made, packaging body base lower surface soldered ball in formation at the welding disking area of upper packaging body base lower surface;
Step H: by lower package body upper surface of base plate soldered ball and the mutual wielding neck of upper packaging body base lower surface soldered ball, completes packaging body attachment at lower package body upper surface, forms stacked structure.
Another technique with regard to step B, step C is:
Step B: make soldered ball at the welding disking area of lower package body upper surface of base plate, form lower package body upper surface of base plate soldered ball, lower package body upper surface of base plate soldered ball equal chip with the height of lower package body upper surface of base plate with the height of lower package body upper surface of base plate, chip is for leaking chip;
Step C: at lower package body upper surface of base plate soldered ball upper surface rubberizing film, part lower package body upper surface of base plate soldered ball and segment chip are absorbed in the glue-line of glued membrane.
Another technique with regard to step B, step C is:
Step B: make soldered ball at the welding disking area of lower package body upper surface of base plate, form lower package body upper surface of base plate soldered ball, lower package body upper surface of base plate soldered ball be greater than chip with the height of lower package body upper surface of base plate with the height of lower package body upper surface of base plate, chip is for leaking chip;
Step C: at lower package body upper surface of base plate soldered ball upper surface rubberizing film, the part surface of part lower package body upper surface of base plate soldered ball and chip is absorbed in the glue-line of glued membrane.
Another technique with regard to step B, step C is:
Step B: make soldered ball at the welding disking area of lower package body upper surface of base plate, form lower package body upper surface of base plate soldered ball, lower package body upper surface of base plate soldered ball be less than chip with the height of lower package body upper surface of base plate with the height of lower package body upper surface of base plate, chip is for leaking chip;
Step C: at lower package body upper surface of base plate soldered ball upper surface rubberizing film, the part surface of part lower package body upper surface of base plate soldered ball and chip is absorbed in the glue-line of glued membrane.
The glued membrane of described step C is high temperature resistant glued membrane.
Lower package body upper surface of base plate soldered ball composition in described step B and step e is Sn, SnAg, SnCu, SnPb or SnAgCu solder.
Described step D: use MUF technique or CUF technique to carry out filling to flip-chip packaged body and reinforce.
Stacked structure in described preparation method is not limited to two-layer packaging body and carries out stacking, also can be two or more packaging body and forms stacked structure.
In described steps A, lower package body is reverse installation process, also can be bonding technology, also can be upside-down mounting and bonding hybrid technique.
Accompanying drawing explanation
Fig. 1 is lower package body substrate and the chip interconnects schematic diagram on it;
Fig. 2 is that lower package body upper surface of base plate makes soldered ball schematic diagram;
Fig. 3 is soldered ball upper surface pad pasting schematic diagram (ball height is higher than chip-encapsulate chip);
Fig. 4 is plastic packaging and Post RDBMS schematic diagram;
Fig. 5 is for taking off film schematic diagram;
Fig. 6 is that lower package body base lower surface makes soldered ball schematic diagram;
Fig. 7 is that lower package body welds I schematic diagram with upper packaging body;
Fig. 8 is soldered ball upper surface pad pasting schematic diagram (ball height and chip height together-leak chip);
Fig. 9 is that lower package body welds II schematic diagram with upper packaging body;
Figure 10 is soldered ball upper surface pad pasting schematic diagram (ball height is higher than chip-leakage chip);
Figure 11 is that lower package body welds III schematic diagram with upper packaging body;
Figure 12 is soldered ball upper surface pad pasting schematic diagram (ball height is lower than chip-leakage chip);
Figure 13 is that lower package body welds IV schematic diagram with upper packaging body;
Figure 14 is that upper strata packaging body also uses this manufacture craft to carry out stacking formation more than three layers stack package structure schematic diagrames;
Figure 15 is the encapsulating structure schematic diagram that upper lower package body all adopts bonding technology;
Figure 16 is that bonding technology and reverse installation process (MUF) carry out stackingly forming POP structure chart.
In figure: 1 is lower package body upper surface of base plate soldered ball, 2 is lower package body base lower surface soldered ball, and 3 is upper packaging body base lower surface soldered ball, 4 is lower package body substrate, and 5 is chip, and 6 is solder bumps, 7 is glued membrane, 8 is plastic-sealed body, and 9 is upper packaging body substrate, and 10 is upper packaging body chip, 11 is the solder bumps of upper packaging body, 12 is underfill, and 13 is pad, and 14 is upper packaging body plastic-sealed body.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
As shown in Fig. 7, Fig. 9, Figure 11 and Figure 13, a kind of POP encapsulating structure using film coating process, described structure comprises lower package body and upper packaging body, lower package body is primarily of lower package body substrate 4, pad 13, solder bumps 6, chip 5, lower package body upper surface of base plate soldered ball 1, plastic-sealed body 8 and lower package body base lower surface soldered ball 2 form, the lower surface of described lower package body substrate 4 is connected with lower package body base lower surface soldered ball 2 by pad 13, the pad 13 of described lower package body substrate 4 upper surface there is solder bumps 6, described chip 5 is welded in solder bumps 6, the pad 13 of described lower package body substrate 4 upper surface also has lower package body upper surface of base plate soldered ball 1, described plastic-sealed body 8 wraps up solder bumps 6, the lower part of chip 5 and lower package body upper surface of base plate soldered ball 1,
Upper packaging body is primarily of upper packaging body substrate 9, pad 13, the solder bumps 11 of upper packaging body, upper packaging body chip 10, underfill 12 and upper packaging body base lower surface soldered ball 3 form, the lower surface of described upper packaging body substrate 9 is connected with upper packaging body base lower surface soldered ball 3 by pad 13, the pad 13 of described upper packaging body substrate 9 upper surface there is the solder bumps 11 of upper packaging body, described upper packaging body chip 10 is welded in the solder bumps 11 of packaging body, described underfill 12 superscribes the solder bumps 11 of packaging body, the part of upper packaging body chip 10 and the part of upper packaging body substrate 9, described lower package body upper surface of base plate soldered ball 1 and the mutual wielding neck of upper packaging body base lower surface soldered ball 3.
Use a preparation method for the POP encapsulating structure of film coating process, its technical process is: lower package body substrate and the chip interconnects on it → lower package body upper surface of base plate make soldered ball → soldered ball upper surface pad pasting → plastic packaging and Post RDBMS → take off film → lower package body base lower surface to make soldered ball → lower package body and weld with upper packaging body.
Use a preparation method for the POP encapsulating structure of film coating process, specifically carry out in accordance with the following steps:
Steps A: core and Reflow Soldering in the upside-down mounting of lower package body substrate 4 upper surface, lower package body substrate 4 is interconnected by pad 13, solder bumps 6 and chip 5 and forms current path, as shown in Figure 1;
Step B: make soldered ball in pad 13 region of lower package body substrate 4 upper surface, form lower package body upper surface of base plate soldered ball 1, lower package body upper surface of base plate soldered ball 1 be greater than chip 5 with the height of lower package body substrate 4 upper surface with the height of lower package body substrate 4 upper surface, as shown in Figure 2;
Step C: at lower package body upper surface of base plate soldered ball 1 upper surface rubberizing film 7, make part lower package body upper surface of base plate soldered ball 1 be absorbed in the glue-line of glued membrane 7, as shown in Figure 3;
Step D: to lower package body plastic packaging, described plastic-sealed body 8 wraps up the lower part of solder bumps 6, chip 5 and lower package body upper surface of base plate soldered ball 1, as shown in Figure 4;
Step e: take off glued membrane 7, exposes the upper surface of lower package body upper surface of base plate soldered ball 1, as shown in Figure 5;
Step F: make soldered ball in pad 13 region of lower package body substrate 4 lower surface, forms lower package body base lower surface soldered ball 2, as shown in Figure 6;
Step G: upper packaging body substrate 9 is interconnected with upper packaging body chip 10 by the solder bumps 11 of pad 13, upper packaging body, coated four interconnect area of underfill 12, soldered ball is made in pad 13 region of upper packaging body substrate 9 lower surface, packaging body base lower surface soldered ball 3 in formation, as shown in Figure 7;
Step H: by lower package body upper surface of base plate soldered ball 1 and the mutual wielding neck of upper packaging body base lower surface soldered ball 3, completes packaging body attachment at lower package body upper surface, forms stacked structure, as shown in Figure 7.
Wherein, another technique with regard to step B, step C and step H is:
Step B: make soldered ball in pad 13 region of lower package body substrate 4 upper surface, form lower package body upper surface of base plate soldered ball 1, lower package body upper surface of base plate soldered ball 1 equal chip 5 with the height of lower package body substrate 4 upper surface with the height of lower package body substrate 4 upper surface, chip 5 is leakage chip, as shown in Figure 8;
Step C: at lower package body upper surface of base plate soldered ball 1 upper surface rubberizing film 7, make part lower package body upper surface of base plate soldered ball 1 and segment chip 5 be absorbed in the glue-line of glued membrane 7, as shown in Figure 8;
Step H: by lower package body upper surface of base plate soldered ball 1 and the mutual wielding neck of upper packaging body base lower surface soldered ball 3, completes packaging body attachment at lower package body upper surface, as shown in Figure 9.
Wherein, another technique with regard to step B, step C and step H is:
Step B: make soldered ball in pad 13 region of lower package body substrate 4 upper surface, form lower package body upper surface of base plate soldered ball 1, lower package body upper surface of base plate soldered ball 1 be greater than chip 5 with the height of lower package body substrate 4 upper surface with the height of lower package body substrate 4 upper surface, chip 5 is leakage chip, as shown in Figure 10;
Step C: at lower package body upper surface of base plate soldered ball 1 upper surface rubberizing film 7, make the part surface of part lower package body upper surface of base plate soldered ball 1 and chip 5 be absorbed in the glue-line of glued membrane 7, as shown in Figure 10;
Step H: by lower package body upper surface of base plate soldered ball 1 and the mutual wielding neck of upper packaging body base lower surface soldered ball 3, completes packaging body attachment at lower package body upper surface, as shown in figure 11.
Wherein, another technique with regard to step B, step C and step H is:
Step B: make soldered ball in pad 13 region of lower package body substrate 4 upper surface, form lower package body upper surface of base plate soldered ball 1, lower package body upper surface of base plate soldered ball 1 be less than chip 5 with the height of lower package body substrate 4 upper surface with the height of lower package body substrate 4 upper surface, chip 5 is leakage chip, as shown in figure 12;
Step C: at lower package body upper surface of base plate soldered ball 1 upper surface rubberizing film 7, make the part surface of part lower package body upper surface of base plate soldered ball 1 and chip 5 be absorbed in the glue-line of glued membrane 7, as shown in figure 12;
Step H: by lower package body upper surface of base plate soldered ball 1 and the mutual wielding neck of upper packaging body base lower surface soldered ball 3, completes packaging body attachment at lower package body upper surface, as shown in figure 13.
In described preparation method, stacked structure is not limited to two-layer packaging body and carries out stacking, also can be two or more packaging body and forms stacked structure, as shown in figure 14.
The present invention is by carrying out pad pasting process to lower package body upper surface of base plate soldered ball 1 and chip 5; thus effectively prevent soldered ball impaired in plastic packaging process; protect soldered ball and chip simultaneously; finally expose plastic-sealed body; soldered ball and upper packaging body carry out solder interconnections; chip exposed part is beneficial to heat radiation, also can mount dissipating cover at chip surface, strengthens radiating effect.This process saves the process of lbg, and technique is simple, and reduce the ball height that to interconnect with upper strata packaging body, can increase soldered ball density accordingly, reduce packaging body thickness, also improve packaging efficiency, packaging cost is reduced simultaneously.
In described preparation method, each stacked structure packaging body is as adopted reverse installation process, its chip underfill has plastic packaging material (MUF technique and Mold Underfill) or underfill (Underfill technique), or other can be used for the filler in order to reinforce welding, determine according to product actual requirement, shown in Figure 16, upper plastic-sealed body adopts MUF technique, and shown in Figure 13, upper plastic-sealed body flip-chip underfill has Underfill glue.
In described preparation method, stacked structure is not limited to two-layer packaging body and carries out stacking, also can be two or more packaging body and forms stacked structure, as shown in figure 14.
The application of described preparation method is not limited to the encapsulation of orlop packaging body, and other layer of package body structure also can be applied this packaging technology and realize, and as in Figure 14, the second layer, third layer, the 4th layer of packaging body all can use this packaging technology.
In described preparation method, each stacked structure packaging body can be reverse installation process, also can be bonding technology, also can be upside-down mounting and bonding hybrid technique, is not limited to a kind of encapsulating structure, as shown in figure 16.
With regard to several preparation methods described above, step C is high temperature resistant glued membrane at solder ball surface institute rubberizing film, can bear plastic packaging process high-temperature condition.
Step C is at solder ball surface institute rubberizing film, and its bondline thickness exposes plastic-sealed body demand according to actual product soldered ball and selects.Soldered ball exposes the half height that plastic-sealed body height can be soldered ball, also can be other arbitrary heights (depending on product requirement and material context).
Ball height on described lower package body substrate can, higher than chip or identical with chip height or lower than chip, be determine according to Product processing requirement.
The flip-chip of described lower package body can expose outside plastic-sealed body, namely also all can be wrapped up by plastic-sealed body by plastic-sealed body wrapping portion.
The chip of described lower package body can expose outside plastic-sealed body, namely by plastic-sealed body wrapping portion, can carry out subsides dissipating cover technique on exposed chip surface, increases radiating effect.
Make soldered ball composition in described step B, E in packaging body and can be the solders such as Sn, SnAg, SnCu, SnPb, SnAgCu.
In described steps A, lower package body is reverse installation process, also can be bonding technology, also can be upside-down mounting and bonding hybrid technique.
Described POP encapsulating structure is not limited to two packaging bodies and carries out stacking, also can be two or more packaging body and forms stacked structure.
The foregoing is only an exemplary embodiments of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. use a POP encapsulating structure for film coating process, it is characterized in that, described structure comprises lower package body and upper packaging body, lower package body is primarily of lower package body substrate (4), pad (13), solder bumps (6), chip (5), lower package body upper surface of base plate soldered ball (1), plastic-sealed body (8) and lower package body base lower surface soldered ball (2) composition, the lower surface of described lower package body substrate (4) is connected with lower package body base lower surface soldered ball (2) by pad (13), the pad (13) of described lower package body substrate (4) upper surface there is solder bumps (6), described chip (5) is welded in solder bumps (6), the pad (13) of described lower package body substrate (4) upper surface is upper also has lower package body upper surface of base plate soldered ball (1), described plastic-sealed body (8) parcel solder bumps (6), the lower part of chip (5) and lower package body upper surface of base plate soldered ball (1),
Upper packaging body is primarily of upper packaging body substrate (9), pad (13), the solder bumps (11) of upper packaging body, upper packaging body chip (10), underfill (12) and upper packaging body base lower surface soldered ball (3) composition, the lower surface of described upper packaging body substrate (9) is connected with packaging body base lower surface soldered ball (3) by pad (13), the pad (13) of described upper packaging body substrate (9) upper surface there is the solder bumps (11) of upper packaging body, described upper packaging body chip (10) is welded in the solder bumps (11) of packaging body, described underfill (12) superscribes the solder bumps (11) of packaging body, the part of upper packaging body chip (10) and the part of upper packaging body substrate (9), described lower package body upper surface of base plate soldered ball (1) and upper packaging body base lower surface soldered ball (3) wielding neck mutually.
2. use a preparation method for the POP encapsulating structure of film coating process, it is characterized in that, specifically carry out in accordance with the following steps:
Steps A: core and Reflow Soldering in lower package body substrate (4) upper surface upside-down mounting, lower package body substrate (4) is interconnected by pad (13), solder bumps (6) and chip (5) and forms current path;
Step B: make soldered ball in pad (13) region of lower package body substrate (4) upper surface, form lower package body upper surface of base plate soldered ball (1), lower package body upper surface of base plate soldered ball (1) be greater than chip (5) with the height of lower package body substrate (4) upper surface with the height of lower package body substrate (4) upper surface;
Step C: in lower package body upper surface of base plate soldered ball (1) upper surface rubberizing film (7), makes part lower package body upper surface of base plate soldered ball (1) be absorbed in the glue-line of glued membrane (7);
Step D: to lower package body plastic packaging, the lower part of described plastic-sealed body (8) parcel solder bumps (6), chip (5) and lower package body upper surface of base plate soldered ball (1);
Step e: take off glued membrane (7), exposes the upper surface of lower package body upper surface of base plate soldered ball (1);
Step F: make soldered ball in pad (13) region of lower package body substrate (4) lower surface, forms lower package body base lower surface soldered ball (2);
Step G: upper packaging body substrate (9) is interconnected with upper packaging body chip (10) by the solder bumps (11) of pad (13), upper packaging body, coated four interconnect area of underfill (12), soldered ball is made, packaging body base lower surface soldered ball (3) in formation in pad (13) region of upper packaging body substrate (9) lower surface;
Step H: by lower package body upper surface of base plate soldered ball (1) and upper packaging body base lower surface soldered ball (3) wielding neck mutually, complete packaging body attachment at lower package body upper surface, form stacked structure.
3. a kind of preparation method using the POP encapsulating structure of film coating process according to claim 2, it is characterized in that, another technique with regard to step B, step C is:
Step B: make soldered ball in pad (13) region of lower package body substrate (4) upper surface, form lower package body upper surface of base plate soldered ball (1), lower package body upper surface of base plate soldered ball (1) equal chip (5) with the height of lower package body substrate (4) upper surface with the height of lower package body substrate (4) upper surface, chip (5) is for leaking chip;
Step C: in lower package body upper surface of base plate soldered ball (1) upper surface rubberizing film (7), makes part lower package body upper surface of base plate soldered ball (1) and segment chip (5) be absorbed in the glue-line of glued membrane (7).
4. a kind of preparation method using the POP encapsulating structure of film coating process according to claim 2, it is characterized in that, another technique with regard to step B, step C is:
Step B: make soldered ball in pad (13) region of lower package body substrate (4) upper surface, form lower package body upper surface of base plate soldered ball (1), lower package body upper surface of base plate soldered ball (1) be greater than chip (5) with the height of lower package body substrate (4) upper surface with the height of lower package body substrate (4) upper surface, chip (5) is for leaking chip;
Step C: in lower package body upper surface of base plate soldered ball (1) upper surface rubberizing film (7), makes the part surface of part lower package body upper surface of base plate soldered ball (1) and chip (5) be absorbed in the glue-line of glued membrane (7).
5. a kind of preparation method using the POP encapsulating structure of film coating process according to claim 2, it is characterized in that, another technique with regard to step B, step C is:
Step B: make soldered ball in pad (13) region of lower package body substrate (4) upper surface, form lower package body upper surface of base plate soldered ball (1), lower package body upper surface of base plate soldered ball (1) be less than chip (5) with the height of lower package body substrate (4) upper surface with the height of lower package body substrate (4) upper surface, chip (5) is for leaking chip;
Step C: in lower package body upper surface of base plate soldered ball (1) upper surface rubberizing film (7), makes the part surface of part lower package body upper surface of base plate soldered ball (1) and chip (5) be absorbed in the glue-line of glued membrane (7).
6. a kind of preparation method using the POP encapsulating structure of film coating process according to claim 2,3,4 and 5, is characterized in that, the glued membrane (7) of described step C is high temperature resistant glued membrane.
7. a kind of preparation method using the POP encapsulating structure of film coating process according to claim 2,3,4 and 5, it is characterized in that, lower package body upper surface of base plate soldered ball (1) composition in described step B and step e is Sn, SnAg, SnCu, SnPb or SnAgCu solder.
8. a kind of preparation method using the POP encapsulating structure of film coating process according to claim 2, it is characterized in that: described step D lower package body flip-chip is connected on substrate, its chip underfill has plastic packaging material (MUF technique and Mold Underfill) or underfill (Underfill technique), or other can be used for the filler in order to reinforce welding.
9. a kind of preparation method using the POP encapsulating structure of film coating process according to claim 2, it is characterized in that, the stacked structure in described preparation method is not limited to two-layer packaging body and carries out stacking, also can be two or more packaging body and forms stacked structure.
10. a kind of preparation method using the POP encapsulating structure of film coating process according to claim 2, it is characterized in that, in described steps A, lower package body is reverse installation process, also can be bonding technology, also can be upside-down mounting and bonding hybrid technique.
11. a kind of preparation methods using the POP encapsulating structure of film coating process according to claim 2, is characterized in that: described preparation method is not limited to the encapsulation of orlop packaging body, and other layer of package body structure also can be applied this packaging technology and realize.
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105428254A (en) * | 2015-12-23 | 2016-03-23 | 南通富士通微电子股份有限公司 | Package on package method |
CN105551988A (en) * | 2015-12-22 | 2016-05-04 | 华进半导体封装先导技术研发中心有限公司 | Multi-layered fanout type packaging structure and preparation method therefor |
CN107275225A (en) * | 2017-06-20 | 2017-10-20 | 上海图正信息科技股份有限公司 | The preparation method and encapsulating structure of chip package module |
CN107316818A (en) * | 2017-06-20 | 2017-11-03 | 上海图正信息科技股份有限公司 | The preparation method and encapsulating structure of chip package module |
WO2019127264A1 (en) * | 2017-12-28 | 2019-07-04 | 华天科技(西安)有限公司 | Three-dimensional chip stacking chip size packaging structure and manufacturing method therefor |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004327855A (en) * | 2003-04-25 | 2004-11-18 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
CN1808692A (en) * | 2004-12-22 | 2006-07-26 | 国家淀粉及化学投资控股公司 | Hot-melt underfill composition and methos of coating |
US20110204494A1 (en) * | 2010-02-23 | 2011-08-25 | Chi Heejo | Integrated circuit packaging system with shield and method of manufacture thereof |
CN102456584A (en) * | 2010-11-02 | 2012-05-16 | 新科金朋有限公司 | Semiconductor device and method of forming pentrable film encapsulant around semiconductor die and interconnect structure |
CN102623359A (en) * | 2012-04-17 | 2012-08-01 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure and manufacturing method thereof |
CN103681468A (en) * | 2012-09-14 | 2014-03-26 | 新科金朋有限公司 | Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP |
CN104078435A (en) * | 2014-07-15 | 2014-10-01 | 南通富士通微电子股份有限公司 | Pop packaging structure |
-
2014
- 2014-12-30 CN CN201410843559.0A patent/CN104658933A/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004327855A (en) * | 2003-04-25 | 2004-11-18 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
CN1808692A (en) * | 2004-12-22 | 2006-07-26 | 国家淀粉及化学投资控股公司 | Hot-melt underfill composition and methos of coating |
US20110204494A1 (en) * | 2010-02-23 | 2011-08-25 | Chi Heejo | Integrated circuit packaging system with shield and method of manufacture thereof |
CN102456584A (en) * | 2010-11-02 | 2012-05-16 | 新科金朋有限公司 | Semiconductor device and method of forming pentrable film encapsulant around semiconductor die and interconnect structure |
CN102623359A (en) * | 2012-04-17 | 2012-08-01 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure and manufacturing method thereof |
CN103681468A (en) * | 2012-09-14 | 2014-03-26 | 新科金朋有限公司 | Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP |
CN104078435A (en) * | 2014-07-15 | 2014-10-01 | 南通富士通微电子股份有限公司 | Pop packaging structure |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105551988A (en) * | 2015-12-22 | 2016-05-04 | 华进半导体封装先导技术研发中心有限公司 | Multi-layered fanout type packaging structure and preparation method therefor |
CN105428254A (en) * | 2015-12-23 | 2016-03-23 | 南通富士通微电子股份有限公司 | Package on package method |
CN107275225A (en) * | 2017-06-20 | 2017-10-20 | 上海图正信息科技股份有限公司 | The preparation method and encapsulating structure of chip package module |
CN107316818A (en) * | 2017-06-20 | 2017-11-03 | 上海图正信息科技股份有限公司 | The preparation method and encapsulating structure of chip package module |
WO2019127264A1 (en) * | 2017-12-28 | 2019-07-04 | 华天科技(西安)有限公司 | Three-dimensional chip stacking chip size packaging structure and manufacturing method therefor |
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