CN104638001B - Radio frequency LDMOS device and process - Google Patents

Abstract

The invention discloses a radio-frequency LDMOS device, which has a body region and an N-type lightly doped drift region in a P-type epitaxy on a P-type substrate, and a single-layer trench-type Faraday ring is above the N-type drift region. The single-layer trench Faraday ring has the same electric field modulation effect as the traditional double-layer Faraday ring structure, and can achieve a high breakdown voltage. The invention also discloses the process method of the radio frequency LDMOS device, which includes the steps of polysilicon gate formation, trench etching, drift region implantation, body region and source-drain region formation, oxide layer deposition, and Faraday ring formation. Layer Faraday rings reduce the deposition of primary metal layers.

Description

Radio frequency LDMOS device and process method

technical field

The invention relates to the field of semiconductors, in particular to a radio frequency LDMOS device, and the invention also relates to a process method of the radio frequency LDMOS device.

Background technique

RF LDMOS (LDMOS: Laterally Diffused Metal Oxide Semiconductor) device is a new generation of integrated solid-state microwave power semiconductor products formed by the integration of semiconductor integrated circuit technology and microwave electronic technology. It has good linearity, high gain, high withstand voltage, and output power. Large size, good thermal stability, high efficiency, good broadband matching performance, easy to integrate with MOS process, etc., and its price is much lower than that of gallium arsenide devices. It is a very competitive power device and is widely used in GSM , PCS, power amplifiers for W-CDMA base stations, as well as wireless broadcasting and nuclear magnetic resonance.

In the design process of RF LDMOS, a large breakdown voltage BV and a small on-resistance Rdson are required. At the same time, in order to obtain good RF performance, the input capacitance Cgs and output capacitance Cds are required to be as small as possible, thereby reducing Effect of parasitic capacitance on device gain and efficiency. A higher breakdown voltage helps to ensure the stability of the device in actual operation. For example, a radio frequency LDMOS device with a working voltage of 50V must have a breakdown voltage of more than 110V. The on-resistance Rdson will directly affect the radio frequency characteristics of the device, such as gain and efficiency. In order to achieve a higher breakdown voltage (above 110V), the general RF LDMOS tube structure is shown in Figure 1, where 1 is a P-type substrate, 10 is a P-type epitaxy, 11 is a P-type body region, and 12 is an N-type drift Region, 23 is the source region, 21 is the drain region. The most notable feature in the figure is the two-layer Faraday ring (G-Shield) 17. This two-layer Faraday ring structure is conducive to a more uniform distribution of the electric field, but in the manufacturing process, the two-layer Faraday ring structure also corresponds to Two times of metal deposition, the process is more complicated.

Contents of the invention

The technical problem to be solved by the present invention is to provide a radio frequency LDMOS device, which has a trench-type single-layer Faraday ring.

Another technical problem to be solved by the present invention is to provide a process method for the radio frequency LDMOS device.

In order to solve the above problems, the radio frequency LDMOS device described in the present invention has P-type epitaxy on the P-type substrate, and the P-type epitaxy has a P-type body region, and a heavily doped P-type body region located in the P-type body region. region and the source region of the RF LDMOS device;

The P-type epitaxy also has a lightly doped drift region, and the lightly doped drift region has a drain region of the LDMOS device;

The silicon surface between the P-type body region and the lightly doped drift region has a gate oxide and a polysilicon gate covering the gate oxide;

On the side of the P-type body region away from the lightly doped drift region, there is a tungsten plug that penetrates the epitaxial layer and its bottom is located on the P-type substrate, and the upper end of the tungsten plug is connected to the heavily doped P-type region;

Two trenches of different sizes are etched in the lightly doped drift region, and the lightly doped drift region and the polysilicon gate are covered with silicon oxide, and the silicon oxide fills the trench far from the polysilicon gate, and does not fill The trench close to the polysilicon gate is filled, the lightly doped drift region and the silicon oxide above part of the polysilicon gate are covered with metal to form a Faraday ring.

Further, among the two trenches of different sizes in the lightly doped drift region, one of the trenches closer to the polysilicon gate is 0.4-1 μm away from the side edge of the polysilicon gate, and the opening width of the trench is 0.4-1 μm. 1.2 μm; the other groove is 0.2-0.8 μm away from the edge of the aforementioned groove, and the opening width of the groove is 0.4-1.2 μm; the depth of the two grooves is

A process method for a radio frequency LDMOS device, comprising the following process steps:

Step 1: Form a P-type epitaxy on a P-type substrate, grow gate oxide and deposit polysilicon, then photolithography and etch to form a polysilicon gate;

In the second step, use photolithography to define the region in the lightly doped drift region to etch to form two trenches of different sizes;

In the third step, a lightly doped drift region is defined by photoresist, and a lightly doped ion implantation is performed;

Step 4, forming a P-type body region, and ion implantation to form a heavily doped P-type region leading out of the P-type body region, and a source region and a drain region of a radio frequency LDMOS device;

In step 5, an oxide layer is deposited on the entire device surface, and the oxide layer does not fill the trenches closer to the polysilicon gate, but completely fills the trenches farther from the polysilicon gate;

Step 6: Deposit a metal layer and etch to form a Faraday ring structure; make a tungsten plug.

Further, in the second step, the trench closer to the polysilicon gate is 0.4-1 μm away from the side edge of the polysilicon gate, and the opening width of the trench is 0.4-1.2 μm; the other trench is 0.2 μm away from the edge of the aforementioned trench. ~0.8μm, groove opening width 0.4~1.2μm; the depth of the two grooves is

Further, in the third step, phosphorus or arsenic is implanted into the N-type drift region, the implantation energy is 50-300KeV, and the implantation dose is 5x10 ¹¹ -4x10 ¹² cm ^-2 .

Further, in the fourth step, the P-type body region is formed in two ways: one is formed by ion implantation and high-temperature push-in before the polysilicon gate is formed, and the other is formed by self-alignment process and high-temperature push-in ; The impurity implanted in the P-type body region is boron, the implantation energy is 30-80KeV, and the implantation dose is 1x10 ¹² ～1x10 ¹⁴ cm ^-2 ; the source and drain regions are heavily doped N-type regions, and the implanted impurities are phosphorus or arsenic , the implantation energy is below 200KeV, and the implantation dose is 1x10 ¹³ ～1x10 ¹⁶ cm ^-2 ; the heavily doped P-type region in the P-type body region is implanted with boron or boron difluoride, the implantation energy is below 100KeV, and the implantation dose is 1x10 ¹³ ～1x10 ¹⁶ cm ^-2 .

Further, in the 5th step, the thickness of the deposited silicon oxide layer is

The radio frequency LDMOS device described in the present invention has a grooved single-layer Faraday ring structure, and by adjusting the morphology of the silicon oxide layer and the silicon layer below the Faraday ring, the same N-type drift as that of the traditional double-layer Faraday ring is achieved. The adjustment effect of the regional electric field distribution makes the device have the same high breakdown voltage characteristics. The primary metal deposition is reduced, and the manufacturing process is simplified.

Description of drawings

Figure 1 is a schematic diagram of the structure of a traditional RF LDMOS device.

2 to 7 are schematic diagrams of the process steps of the present invention.

Fig. 8 is a flowchart of the process steps of the present invention.

9-10 are simulation comparison diagrams of the present invention and traditional LDMOS.

Explanation of reference signs

1 is a P-type substrate, 10 is a P-type epitaxial layer, 11 is a P-type body region, 12 is a lightly doped drift region, 13 is a tungsten plug, 14 is a gate oxide, 15 is a polysilicon gate, and 16 is an oxide layer. 17 is a Faraday ring, 21 is a drain region, 22 is a heavily doped P-type region, 23 is a source region, and 105 is a photoresist.

detailed description

The radio frequency LDMOS device described in the present invention, as shown in FIG. The heavily doped P-type region 22 and the source region 23 of the RF LDMOS device;

The P-type epitaxy 10 also has a lightly doped drift region 12, and the lightly doped drift region has a drain region 21 of the LDMOS device;

The silicon surface between the P-type body region 11 and the lightly doped drift region 12 has a gate oxide 14 and a polysilicon gate 15 covering the gate oxide 14;

On the side of the P-type body region 11 away from the lightly doped drift region 12, there is a tungsten plug 13 that penetrates the epitaxial layer 10 and its bottom is located on the P-type substrate 1, and the upper end of the tungsten plug 13 is connected to the heavily doped P-type region 22;

Two grooves of different sizes are etched in the lightly doped drift region 12, and the lightly doped drift region 12 and the polysilicon gate 15 are covered with silicon oxide 16, and the silicon oxide 16 fills the gap farther away from the polysilicon gate 15. The grooves close to the polysilicon gate 15 are not filled, and the lightly doped drift region 12 and the silicon oxide 16 above the polysilicon gate 15 are covered with metal to form a Faraday ring 17 .

The processing method of the radio frequency LDMOS device of the present invention, enumerates an embodiment and explains as follows:

Process steps:

In the first step, as shown in FIG. 2 , a P-type epitaxy 10 is formed on a P-type substrate 1 , a gate oxide 14 is grown and polysilicon is deposited, and a photoresist 105 is defined to form a polysilicon gate 15 .

In the second step, as shown in FIG. 3 , two grooves of different sizes are formed by etching in the area of the lightly doped drift region defined by photolithography; Side edge d1=0.4～1μm, trench opening width d2=0.4～1.2μm; the distance from the other trench to the edge of the trench d3=0.2～0.8μm, trench opening width d4=0.4～1.2μm; it is required to be close to the polysilicon gate The opening width of the groove of the pole is greater than the opening width of the other groove, and the depth of the two grooves is The depths of the two grooves can be the same or different.

In the third step, as shown in FIG. 4 , the photoresist 105 is used to define a lightly doped drift region, and a lightly doped ion implantation is performed; the N-type drift region 12 is implanted with phosphorus or arsenic as an impurity, and the implantation energy is 50-300KeV. The injection dose is 5x10 ¹¹ -4x10 ¹² cm ^-2 .

Step 4, as shown in Figure 5, forms the P-type body region 11. There are two ways to form the P-type body region 11: one is formed by ion implantation and high-temperature advancement before the polysilicon gate is formed, and the other is by Formed by self-alignment process and high-temperature advancement; the impurity implanted in the P-type body region is boron, the implantation energy is 30-80KeV, and the implantation dose is 1x10 ¹² -1x10 ¹⁴ cm ^-2 . Then ion implantation forms the heavily doped P-type region 22 leading out the P-type body region 11, the implanted impurity is boron or boron difluoride, the implantation energy is below 100KeV, and the implantation dose is 1×10 ¹³ ~1×10 ¹⁶ cm ⁻² . Both the source region 23 and the drain region 21 are heavily doped N-type regions, the impurity implanted is phosphorus or arsenic, the implantation energy is below 200KeV, and the implantation dose is 1x10 ¹³ -1x10 ¹⁶ cm ^-2 .

In the 5th step, as shown in Figure 6, an oxide layer 16 is deposited on the surface of the entire device, and the thickness of the deposited silicon oxide layer 16 is The oxide layer does not fill the trenches closer to the polysilicon gate, that is, the trenches with larger opening widths, and the trenches farther from the polysilicon gate are completely filled.

In step 6, metal layers are deposited and etched to form a Faraday ring structure 17; a tungsten plug 13 is fabricated to complete the device, as shown in FIG. 7 .

The fabrication process of the whole device is shown in Fig. 8 .

In order to illustrate the actual effect of the present invention, TCAD simulation software is used to simulate and compare the effects of the radio frequency LDMOS tube of the present invention and the effect of the traditional radio frequency LDMOS tube. The distribution of the X-axis, the area enclosed by the curve in the figure and the X-axis is the breakdown voltage BV of the RF LDMOS tube. It can be seen from the figure that in most ranges, the curve distributions of the two are similar, and correspondingly, the breakdown voltage BV of the two is almost the same. This is mainly because the vertical direction of the metal at the bottom of the first trench (the trench closer to the polysilicon gate) of the present invention is closer to the drift region and has a stronger pulling electric field effect, while the second trench ( The trench farther away from the polysilicon gate) The metal on the top is farther away from the drift region in the vertical direction, which also has the effect of pulling the electric field, so that a certain gradient is formed, and combined with the difference in their distance from the drain end, it helps to obtain The more uniform electric field distribution enables the device with the single-layer trench Faraday ring structure to have the same high breakdown voltage as the double-layer Faraday ring structure. Fig. 10 is the simulation curve of the actual breakdown voltage of the present invention and the traditional structure, from the results, the curves of the two almost completely overlap, in the figure, the breakdown voltage BV of the traditional double-layer Faraday ring structure is 118V, the present invention can not The breakdown voltage BV of the slot-type single-layer Faraday ring is 117.2V.

The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and variations of the present invention will occur to those skilled in the art. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (7)

1. A radio frequency LDMOS device, having a P-type epitaxy on a P-type substrate, having a P-type body region in the P-type epitaxy, and a heavily doped P-type region in the P-type body region and the radio frequency LDMOS the source area of the device; The P-type epitaxy also has a lightly doped drift region, and the lightly doped drift region has a drain region of the LDMOS device; The silicon surface between the P-type body region and the lightly doped drift region has a gate oxide and a polysilicon gate covering the gate oxide; On the side of the P-type body region away from the lightly doped drift region, there is a tungsten plug that penetrates the epitaxial layer and its bottom is located on the P-type substrate, and the upper end of the tungsten plug is connected to the heavily doped P-type region; It is characterized in that: two grooves of different sizes are etched in the lightly doped drift region, and the lightly doped drift region and the polysilicon gate are covered with silicon oxide, and the silicon oxide fills the trench far from the polysilicon gate The trench is not filled with the trench close to the polysilicon gate, and the lightly doped drift region and part of the silicon oxide above the polysilicon gate are covered with metal to form a Faraday ring. 2. The radio frequency LDMOS device as claimed in claim 1, characterized in that: two trenches with different opening widths in the lightly doped drift region, one of which is closer to the polysilicon gate, the distance between The side edge of the polysilicon gate is 0.4-1 μm, and the opening width of the trench is 0.4-1.2 μm; the other trench is 0.2-0.8 μm away from the edge of the aforementioned trench, and the opening width of the trench is 0.4-1.2 μm; the opening width of the trench close to the polysilicon gate Greater than the opening width of the other groove; the depth of the two grooves is 1000-5000Å. 3. the process method of a kind of radio frequency LDMOS device as claimed in claim 1, is characterized in that: comprise following process steps: Step 1: Form a P-type epitaxy on a P-type substrate, grow gate oxide and deposit polysilicon, then photolithography and etch to form a polysilicon gate; In the second step, use photolithography to define the region in the lightly doped drift region to etch to form two trenches of different sizes; In the third step, a lightly doped drift region is defined by photoresist, and a lightly doped ion implantation is performed; Step 4, forming a P-type body region, and ion implantation to form a heavily doped P-type region leading out of the P-type body region, and a source region and a drain region of a radio frequency LDMOS device; In step 5, an oxide layer is deposited on the entire device surface, and the oxide layer does not fill the trenches closer to the polysilicon gate, but completely fills the trenches farther from the polysilicon gate; Step 6: Deposit a metal layer and etch to form a Faraday ring structure; make a tungsten plug. 4. The process method of a radio frequency LDMOS device as claimed in claim 3, characterized in that: in the second step, the trench that is closer to the polysilicon gate is 0.4 to 1 μm away from the side edge of the polysilicon gate, The opening width of the groove is 0.4-1.2 μm; the distance between the other groove and the edge of the groove is 0.2-0.8 μm, and the opening width of the groove is 0.4-1.2 μm; the depth of the two grooves is 1000-5000Å. 5. The process method of a radio frequency LDMOS device according to claim 3, characterized in that: in the third step, the impurity implanted into the N-type drift region is phosphorus or arsenic, the implantation energy is 50-300KeV, and the implantation dose is 5x10 ¹¹ ~ 4x10 ¹² cm ^-2 . 6. The process method of a kind of radio frequency LDMOS device as claimed in claim 3, it is characterized in that: in the 4th step, the formation of P-type body region is two ways: one is to pass ion before the polysilicon gate is formed Implantation and high-temperature boosting formation, the other is formed by self-alignment process and high-temperature boosting; the impurity implanted in the P-type body region is boron, the implantation energy is 30-80KeV, and the implantation dose is 1x10 ¹² ～1x10 ¹⁴ cm ^-2 ; the source Both the region and the drain region are heavily doped N-type regions, the implanted impurity is phosphorus or arsenic, the implantation energy is below 200KeV, and the implantation dose is 1x10 ¹³ ~ 1x10 ¹⁶ cm ^-2 ; the heavily doped P-type region in the P-type body region The implanted impurity is boron or boron difluoride, the implantation energy is below 100KeV, and the implantation dose is 1x10 ¹³ -1x10 ¹⁶ cm ^-2 . 7. The process method of a radio frequency LDMOS device according to claim 3, characterized in that: in the fifth step, the thickness of the deposited silicon oxide layer is 1000-4000Å.