CN104635826A - Simple linear power supply circuit - Google Patents

Abstract

The invention discloses a simple linear power supply circuit. The circuit controls the power-on speed of a power supply trough an RC, reduces the peak pulse of the power supply, and achieves a simple linear power supply by being combined with a negative feedback principle.

Description

A kind of simple linear power source circuit

Technical field

The present invention relates generally to the design field of power circuit, refers in particular to a kind of simple linear power source circuit.

Background technology

For Analogous Integrated Electronic Circuits, the quality of its performance depends on several factors, wherein the quality of power supply is also the key factor affecting Analogous Integrated Electronic Circuits performance, particularly some high-precision analog circuit, as high-precision adc (ADC), high precision digital-to-analog converter (DAC), instrument amplifier etc., this kind of circuit all needs a high-quality Power supply usually, usually be all adopt linear power supply (LDO), LDO power supply signal bad for performance is converted to performance relatively preferably power supply export, the performance of LDO is usually all fine, but the area taken is also larger, for some simple modules, or the circuit module that scale is less, and under the performance requirement of power supply is not again extra high situation, LDO is not a wise selection.

Summary of the invention

The problem to be solved in the present invention is just: the technical matters existed for prior art, proposes a kind of simple linear power source circuit.

The solution that the present invention proposes is: this circuit controls the power-up speeds of power supply by RC, reduces power supply spike, then achieves a simple linear power supply in conjunction with negative-feedback principle.

Accompanying drawing explanation

Fig. 1 is circuit theory schematic diagram of the present invention;

Embodiment

Below with reference to accompanying drawing and concrete enforcement, the present invention is described in further details.

As shown in Figure 1, circuit is by resistance R ₁, R ₂, R ₃dividing potential drop, produces voltage VB and VR, M ₁with falling than pipe realization, i.e. M ₁l much larger than W; Metal-oxide-semiconductor M ₁, M ₂, M ₃, M ₄, M ₅, M ₆can find out a discharge circuit, the load of this amplifier is not adopt conventional structure, M ₄for diode-connected, M ₅for current mirror-, adopt the advantage of this structure to have 2 points, the first is relative to conventional diode structure, and the gain of this amplifier is comparatively large, and it two is relative to simple current-mirror structure, and the output impedance of this amplifier is little, and pole frequency is high, is conducive to loop stability.

$\mathrm{VR}=\mathrm{Vref}=\mathrm{VDD}\·\frac{R_2+R_3}{R_1+R_2+R_3}---\left(1\right)$

$\mathrm{VB}=\mathrm{VDD}\·\frac{R_3}{R_1+R_2+R_3}---\left(2\right)$

VB provides biased to amplifier, upon power-up, and M ₁conducting, Vref level slowly rises, and finally makes Vref=VB, due to negative voltage feedback, can obtain:

$\mathrm{VOUT}=\frac{(R_2+R_3)\·(R_4+R_5)}{(R_1+R_2+R_3)\·R_5}\·\mathrm{VDD}---\left(3\right)$

Adjustment electric capacity C ₁control the speed that powers on, thus spike during the powering on of control VOUT; Electric capacity C ₂compensate and filter action.

In sum, this circuit controls the power-up speeds of power supply by RC, reduces power supply spike, then achieves a simple linear power supply in conjunction with negative-feedback principle.

Claims (1)

1. a simple linear power source circuit, is characterized in that:

Circuit is by PMOS M ₄, PMOS M ₅, PMOS M ₆, PMOS M ₇, NMOS tube M ₁, NMOS tube M ₂, NMOS tube M ₃, NMOS tube M ₄, resistance R ₁, resistance R ₂, resistance R ₃, resistance R ₄, resistance R ₅with electric capacity C ₁, C ₂composition; System power supply VDD is connected to PMOS M ₄, M ₅, M ₆and M ₇source electrode and NMOS tube M ₁grid and resistance R ₁one end; Earth signal GND is connected to resistance R ₃one end, resistance R ₅one end, electric capacity C ₁one end, electric capacity C ₂one end and NMOS tube M ₄source electrode; Resistance R ₂one end be connected to NMOS tube M ₁drain electrode and resistance R ₁one end, resistance R ₂the other end be connected to resistance R ₃one end and NMOS tube M ₄grid; NMOS tube M ₁source electrode be connected to electric capacity C ₁one end and NMOS tube M ₂grid; NMOS tube M ₄drain electrode be connected to NMOS tube M ₂, M ₃source electrode; M ₃grid be connected to resistance R ₄, R ₅one end; PMOS M ₄grid, drain electrode be connected to PMOS M ₅drain electrode, PMOS M ₇grid and NMOS pipe M ₂drain electrode; PMOS M ₆grid, drain electrode be connected to PMOS M ₅grid and NMOS tube M ₃drain electrode; PMOS M ₇drain electrode be connected to resistance R ₄with electric capacity C ₂one end, namely VOUT exports.