CN104617915B - Master-slave flip-flop based on FinFET transistor - Google Patents
Master-slave flip-flop based on FinFET transistor Download PDFInfo
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Abstract
The invention discloses a master-slave flip-flop based on a FinFET transistor. The master-slave flip-flop based on the FinFET transistor is that a first P type FinFET pipe, a second P type FinFET pipe, a third P type FinFET pipe, a first N type FinFET pipe, a second N type FinFET pipe, a third N type FinFET pipe, a fourth N type FinFET pipe, a fifth N type FinFET pipe and a sixth N type FinFET pipe form a master latch; a slave latch comprises a second phase inverter and a third phase inverter, wherein the second phase inverter consists of a fourth P type FinFET pipe and a seventh N type FinFET pipe; the third phase inverter consists of a fifth P type FinFET pipe and an eighth N type FinFET pipe; the slave lock is a loop composed of two phase inverters. The master-slave flip-flop based on the FinFET transistor has the advantages that the circuit structure is simple, the power consumption and spreading delay are small, the 32nm process device parameters of a PTM model are adopted for simulating under a standard voltage (1v) condition; compared with the existing flip-flop, the master-slave flip-flop has the advantages that the circuit power consumption is reduced by about 66%, and the spreading delay is reduced by about 48%.
Description
Technical field
The present invention relates to a kind of trigger, more particularly, to a kind of master-slave flip-flop based on FinFET transistors.
Background technology
At present, the design technology of integrated circuit technique enters into a nanometer stage, in chip design process, no matter from chip
The cost of itself and performance consider, or consider that power consumption size has become measurement core from the market angle of electronics and IT products
The important indicator of piece performance.Low power dissipation design has become the focus and difficult point of current chip design.
With the continuous diminution of transistor size, limited by short-channel effect and present production process, common CMOS
The space that transistor size is reduced extremely reduces.When the size reduction of common CMOS transistor is to below 20nm, CMOS crystal
The leakage current of pipe can be increased drastically, cause larger circuit to leak power consumption.Also, circuit short-channel effect becomes readily apparent from,
CMOS transistor becomes rather unstable, significantly limit the raising of circuit performance.The raceway groove of FinFET transistors adopts zero
Adulterate or low-doped, raceway groove is enclosed by the bread of grid three, this special 3-D solid structure, enhances controling power of the grid to raceway groove
Degree, greatly inhibits short-channel effect, it is suppressed that the leakage current of device.FinFET (fin field-effect transistor, Fin Field-
Effect Transistor) as a kind of new 3D transistors, it is increasingly becoming and takes over common CMOS transistor, continuity mole
One of improved device of law.
Trigger, as a kind of basic processing unit of electronic system, is the important composition portion for constituting basic timing unit
Part, in being widely used in large-scale IC design.The quality of trigger performance tends to decision-making circuit performance
Quality.Design one is swift in response, and the relatively low trigger of power consumption has become one of unavoidable problem of circuit designers.It is existing
The master-slave flip-flop based on FinFET transistors having mainly has two kinds：Variable connector type master-slave flip-flop and pressure impulse type master
Slave flipflop.The circuit diagram of variable connector type master-slave flip-flop is as shown in figure 1, there is problems with the trigger：First, used
FinFET number of transistors it is more, circuit structure is complicated, takes chip area big and can cause larger circuit power consumption；2nd,
The clock signal that the circuit is accessed needs to drive four FinFET transmission gates, and load clock signal is very big, causes very big circuit
Power consumption and propagation delay, the propagation delay of the circuit is the time delay and a FinFET phase inverter time delay of a FinFET transmission gate
Sum.The circuit diagram of impulse type master-slave flip-flop is forced as shown in Fig. 2 the quantity of transistor that uses of the trigger is with respect to multichannel
Switching mode master-slave flip-flop is reduced, and clock signal only needs to drive two FinFET transmission gates, clock load to reduce, but this is touched
Send out device and there is problems with：The change of latch state in trigger, needs stronger input data pulse, of short duration direct current to lead to
Larger quiescent dissipation is caused on road, and power consumption is larger.
In view of this, a circuit structure is designed simple, power consumption and the less master based on FinFET transistors of propagation delay
Slave flipflop is significant.
The content of the invention
The technical problem to be solved is to provide a kind of circuit structure simply, and power consumption and propagation delay are less
Master-slave flip-flop based on FinFET transistors.
The present invention solve the technical scheme that adopted of above-mentioned technical problem for：A kind of principal and subordinate based on FinFET transistors touches
Send out device, including the first p-type FinFET pipe, the second p-type FinFET pipe, the 3rd p-type FinFET pipe, the 4th p-type FinFET pipe, the 5th
P-type FinFET pipe, the first N-type FinFET pipe, the second N-type FinFET pipe, the 3rd N-type FinFET are managed, the 4th N-type FinFET is managed,
5th N-type FinFET pipe, the 6th N-type FinFET pipe, the 7th N-type FinFET pipe and the 8th N-type FinFET pipe；
The source electrode of the first described p-type FinFET pipe, the source electrode of the second described p-type FinFET pipe, the 4th described p-type
It is the source electrode of FinFET pipes, the source electrode of the 5th described p-type FinFET pipe, the substrate of the first described p-type FinFET pipe, described
The substrate of the second p-type FinFET pipe, the substrate of the 3rd described p-type FinFET pipe, the substrate of the 4th described p-type FinFET pipe
Power supply is accessed with the substrate of the 5th described p-type FinFET pipe；
The substrate of the first described N-type FinFET pipe, the substrate of the second described N-type FinFET pipe, the 3rd described N-type
It is the substrate of FinFET pipes, the substrate of the 4th described N-type FinFET pipe, the substrate of the 5th described N-type FinFET pipe, described
The substrate of the 6th N-type FinFET pipe, the substrate of the 7th described N-type FinFET pipe, the lining of the 8th described N-type FinFET pipe
Bottom, the source electrode of the first described N-type FinFET pipe, the source electrode of the 5th described N-type FinFET pipe, the 7th described N-type
The source grounding of the source electrode of FinFET pipes and the 8th described N-type FinFET pipe；
The drain electrode of the second described N-type FinFET pipe is signal input part, and the drain electrode of the 3rd described N-type FinFET pipe is
Inversion signal input；The grid of the second described N-type FinFET pipe, the grid of the 3rd described p-type FinFET pipe and described
The 3rd N-type FinFET pipe grid connection and its connection end is clock signal input terminal, described the 4th N-type FinFET pipe
The grid of grid and the 6th described N-type FinFET pipe connects and its connection end is inverting clock signal input；
The drain electrode of the first described N-type FinFET pipe, the grid of the first described p-type FinFET pipe, the second described N-type
The drain electrode connection of the source electrode of FinFET pipes and the 4th described N-type FinFET pipe；The drain electrode of the first described p-type FinFET pipe,
The grid of the second described p-type FinFET pipe, the grid of the first described N-type FinFET pipe, described the 5th N-type FinFET pipe
Grid and the 3rd described N-type FinFET pipe source electrode connection；The drain electrode of the second described p-type FinFET pipe, described
The drain electrode of three p-type FinFET pipes, the drain electrode of the 5th described N-type FinFET pipe and the drain electrode of the 6th described N-type FinFET pipe
Connection；
The source electrode of the 3rd described p-type FinFET pipe, the drain electrode of the 4th described p-type FinFET pipe, the 5th described p-type
It is the grid of FinFET pipes, the source electrode of the 4th described N-type FinFET pipe, the source electrode of the 6th described N-type FinFET pipe, described
The drain electrode of the 7th N-type FinFET pipe and the grid of the 8th described N-type FinFET pipe connect and its connection end is signal output part；
The grid of the 4th described p-type FinFET pipe, the drain electrode of the 5th described p-type FinFET pipe, described the 7th N-type FinFET pipe
Grid and the 8th described N-type FinFET pipe drain electrode connection and its connection end be inversion signal outfan.
It is the channel length of the first described p-type FinFET pipe, the channel length of the second described p-type FinFET pipe, described
The 3rd p-type FinFET pipe channel length, the channel length of the 4th described p-type FinFET pipe, the 5th described p-type
The channel length of FinFET pipes, the channel length of the first described N-type FinFET pipe, the ditch of the second described N-type FinFET pipe
It is road length, the channel length of the 3rd described N-type FinFET pipe, the channel length of the 4th described N-type FinFET pipe, described
The channel length of the 5th N-type FinFET pipe, the channel length of the 6th described N-type FinFET pipe, the 7th described N-type FinFET
The channel length of the channel length of pipe and the 8th described N-type FinFET pipe is 32nm.
Compared with prior art, it is an advantage of the current invention that by the first p-type FinFET pipe, the second p-type FinFET pipe, the
Three p-types FinFET pipe, the first N-type FinFET pipe, the second N-type FinFET pipe, the 3rd N-type FinFET pipe, the 4th N-type FinFET
Pipe, the 5th N-type FinFET pipe and the 6th N-type FinFET pipe constitute main latch；From latch by the 4th p-type FinFET pipe and the
The second phase inverter that seven N-type FinFET pipes are constituted manage with the 5th p-type FinFET and the 8th N-type FinFET pipe composition it is the 3rd anti-phase
Device is constituted, from the loop that latch is two phase inverter compositions；Main latch and from there is no on-off circuit between latch
Isolation, is embedded in the phase inverter ring of main latch from latch, it is possible thereby to greatly reduce the propagation delay of trigger
Time；And the master-slave flip-flop of the present invention is made up of 13 FinFET pipes, and number of transistors is less, circuit structure is simple,
Chip area is reduced, circuit power consumption is reduced, clock signal only needs to five FinFET pipes of load, and clock load reduces, enters
One step reduces circuit power consumption；The passgate structures that 3rd p-type FinFET is managed and the 6th N-type FinFET pipe is constituted, not only ensure electricity
The Full-swing output on road, but also can be with the driving force of intensifier circuit；Using the 32nm process devices parameters of PTM models,
Emulated under the conditions of normal voltage (1v), the circuit power consumption of the present invention is than existing flip-flop circuit lower power consumption about
66%, propagation delay reduces about 48%.
Description of the drawings
Fig. 1 is the circuit diagram of the variable connector type master-slave flip-flop of prior art；
Fig. 2 is the circuit diagram of the pressure impulse type master-slave flip-flop of prior art；
Fig. 3 (a) is the circuit diagram of the master-slave flip-flop based on FinFET transistors of the present invention；
Fig. 3 (b) is the simplified electrical circuit diagram of Fig. 3 (a)；
Fig. 4 is circuit simulation of the master-slave flip-flop based on FinFET transistors of the present invention under normal voltage (1v)
Figure；
Fig. 5 is that circuit of the master-slave flip-flop based on FinFET transistors of the present invention under superthreshold threshold voltage (0.8v) is imitated
True figure；
Fig. 6 is the propagation of the master-slave flip-flop based on FinFET transistors with two kinds of triggers of prior art of the present invention
Time delay comparative analysiss figure；
Fig. 7 is the unit of the master-slave flip-flop based on FinFET transistors with two kinds of triggers of prior art of the present invention
Switch observable index is compared with analysis chart.
Specific embodiment
The present invention is described in further detail below in conjunction with accompanying drawing embodiment.
Embodiment：As shown in Fig. 3 (a), a kind of master-slave flip-flop based on FinFET transistors, including the first p-type
FinFET pipe P1, the second p-type FinFET pipe P2, the 3rd p-type FinFET pipe P3, the 4th p-type FinFET pipe P4, the 5th p-type
FinFET pipe P5, the first N-type FinFET pipe N1, the second N-type FinFET pipe N2, the 3rd N-type FinFET pipe N3, the 4th N-type
FinFET pipe N4, the 5th N-type FinFET pipe N5, the 6th N-type FinFET pipe N6, the 7th N-type FinFET pipe N7 and the 8th N-type
FinFET pipe N8；
The source electrode of the first p-type FinFET pipe P1, the source electrode of the second p-type FinFET pipe P2, the source of the 4th p-type FinFET pipe P4
Pole, the source electrode of the 5th p-type FinFET pipe P5, the substrate of the first p-type FinFET pipe P1, the substrate of the second p-type FinFET pipe P2,
The substrate of three p-type FinFET pipe P3, the substrate of the 4th p-type FinFET pipe P4 and the substrate of the 5th p-type FinFET pipe P5 are accessed
Power supply；
The substrate of the first N-type FinFET pipe N1, the substrate of the second N-type FinFET pipe N2, the lining of the 3rd N-type FinFET pipe N3
Bottom, the substrate of the 4th N-type FinFET pipe N4, the substrate of the 5th N-type FinFET pipe N5, the substrate of the 6th N-type FinFET pipe N6,
The substrate of seven N-type FinFET pipe N7, the substrate of the 8th N-type FinFET pipe N8, source electrode, the 5th N-type of the first N-type FinFET pipe N1
The source grounding of the source electrode of FinFET pipe N5, the source electrode of the 7th N-type FinFET pipe N7 and the 8th N-type FinFET pipe N8；
The drain electrode of the second N-type FinFET pipe N2 is signal input part, accesses input signal D, the 3rd N-type FinFET pipe N3's
Drain as inversion signal input, access rp input signal Db；Grid, the 3rd p-type FinFET of the second N-type FinFET pipe N2
The grid of the grid of pipe P3 and the 3rd N-type FinFET pipe N3 connects and its connection end is clock signal input terminal, and incoming clock is believed
The grid of number CLK, the 4th N-type FinFET pipe N4 and the grid connection of the 6th N-type FinFET pipe N6 and its connection end for it is anti-phase when
Clock signal input part, accesses inverting clock signal CLKb；Input signal D and rp input signal Db's differs only in both
The phase 180 degree for differing only in both of phase 180 degree, clock signal clk and inverting clock signal CLKb；
The drain electrode of the first N-type FinFET pipe N1, the grid of the first p-type FinFET pipe P1, the source of the second N-type FinFET pipe N2
The drain electrode connection of pole and the 4th N-type FinFET pipe N4；The drain electrode of the first p-type FinFET pipe P1, the grid of the second p-type FinFET pipe P2
Pole, the source electrode of the grid, the grid of the 5th N-type FinFET pipe N5 and the 3rd N-type FinFET pipe N3 of the first N-type FinFET pipe N1 connect
Connect；The drain electrode of the second p-type FinFET pipe P2, the drain electrode of the 3rd p-type FinFET pipe P3, the drain electrode of the 5th N-type FinFET pipe N5 and
The drain electrode connection of the 6th N-type FinFET pipe N6；
The source electrode of the 3rd p-type FinFET pipe P3, the drain electrode of the 4th p-type FinFET pipe P4, the grid of the 5th p-type FinFET pipe P5
Pole, the source electrode of the 4th N-type FinFET pipe N4, the source electrode of the 6th N-type FinFET pipe N6, the drain electrode of the 7th N-type FinFET pipe N7 and
8th N-type FinFET pipe N8 grid connection and its connection end be signal output part, output signal output Q；4th p-type FinFET
The grid of pipe P4, the drain electrode of the 5th p-type FinFET pipe P5, the grid of the 7th N-type FinFET pipe N7 and the 8th N-type FinFET pipe N8
Drain electrode connection and its connection end be inversion signal outfan, export reversed-phase output signal Qb；Output signal Q and anti-phase output are believed
The phase 180 degree for differing only in both of number Qb.
In the present embodiment, the channel length of the first p-type FinFET pipe P1, the channel length of the second p-type FinFET pipe P2,
The channel length of three p-type FinFET pipe P3, the channel length of the 4th p-type FinFET pipe P4, the raceway groove of the 5th p-type FinFET pipe P5
Length, the channel length of the first N-type FinFET pipe N1, the channel length of the second N-type FinFET pipe N2, the 3rd N-type FinFET pipe
The channel length of N3, the channel length of the 4th N-type FinFET pipe N4, channel length, the 6th N-type of the 5th N-type FinFET pipe N5
The channel length of the channel length of FinFET pipe N6, the channel length of the 7th N-type FinFET pipe N7 and the 8th N-type FinFET pipe N8
It is 32nm.
In the present embodiment, the second p-type FinFET pipe P2 and the 5th N-type FinFET pipe N5 constitutes the first phase inverter F1, the 4th P
Type FinFET pipe P4 and the 7th N-type FinFET pipe N7 constitutes the second phase inverter F2, the 5th p-type FinFET pipe P5 and the 8th N-type
FinFET pipes N8 constitutes the 3rd phase inverter F3.The master-slave flip-flop of the present embodiment replaces its corresponding FinFET pipe using phase inverter
Shown in the such as Fig. 3 (b) of simplified electrical circuit diagram afterwards.
In the master-slave flip-flop of the present embodiment, the first p-type FinFET pipe P1, the second p-type FinFET pipe P2, the 3rd p-type
FinFET pipe P3, the first N-type FinFET pipe N1, the second N-type FinFET pipe N2, the 3rd N-type FinFET pipe N3, the 4th N-type
FinFET pipe N4, the 5th N-type FinFET pipe N5 and the 6th N-type FinFET pipe N6 constitute main latch；In main latch, the 3rd
P-type FinFET pipe P3 and the 6th N-type FinFET pipe N6 constitutes transmission gate circuit, the 3rd p-type FinFET pipe P3, the 4th N-type
FinFET pipes N4 and the 6th N-type FinFET pipe N6 constitutes on-off circuit, the first p-type FinFET pipe P1, the first N-type FinFET pipe
N1, the second N-type FinFET pipe N2 and the 3rd N-type FinFET pipe N3 constitute assignment circuit.4th p-type FinFET pipe P4, the 5th p-type
FinFET pipe P5, the 7th N-type FinFET pipe N7 and the 8th N-type FinFET pipe N8 are constituted from latch, are by second from latch
The loop of phase inverter F2 and the 3rd phase inverter F3 compositions.
The operation principle of the master-slave flip-flop of the present embodiment is as described below：
When clock signal clk is high level, the first p-type FinFET pipe P1, the second p-type FinFET pipe P2, the 3rd p-type
FinFET pipe P3, the first N-type FinFET pipe N1, the second N-type FinFET pipe N2, the 3rd N-type FinFET pipe N3, the 4th N-type
The main latch that FinFET pipe N4, the 5th N-type FinFET pipe N5 and the 6th N-type FinFET pipe N6 are constituted is in sample states, defeated
Enter signal D and rp input signal Db is input in master-slave flip-flop, if input signal D is low level, the first N-type FinFET
The circuit of pipe N1 and the first p-type FinFET pipe P1 compositions has latch function；If input signal D is high level, the first N-type
The circuit of FinFET pipes N1 and the first p-type FinFET pipe P1 compositions does not have latch function, and circuit relies on the charge and discharge of node capacitor
Electricity is operated.Input signal D and rp input signal Db are transferred to the 3rd p-type FinFET pipe P3 and the 6th N-type FinFET pipe
The drain electrode of N6；Now, it is in the anti-of hold mode, output signal Q of signal output part and inversion signal outfan from latch
Phase output signal Qb is in maintenance state.
When CLK is low level, the 3rd p-type FinFET pipe P3, the 4th N-type FinFET pipe N4 and the 6th N-type FinFET are managed
The on-off circuit of N6 compositions is in the conduction state, at the same time, the 4th p-type FinFET pipe P4, the 5th p-type FinFET pipe P5, the
What seven N-type FinFET pipe P7 and the 8th N-type FinFET pipe P8 were constituted is changed from the state of latch, the output of signal output part
The reversed-phase output signal Qb of signal Q and inversion signal outfan accordingly changes.
Using PTM models (Predictive Technology Model), the specially BSIM- of Berkeley University
The 32nm process devices parameters of CMG108 models, respectively under the conditions of normal voltage (1v) and superthreshold threshold voltage (0.8v) condition
Under, functional simulation emulation is carried out to the master-slave flip-flop of the present invention, wherein Fig. 4 is the circuit simulation figure under normal voltage (1v),
Abscissa represents simulation time, and vertical coordinate V (CLK) represents the amplitude voltage of clock signal clk, and V (D) represents input signal D
Amplitude voltage, V (Q) represents the amplitude voltage of output signal Q；Fig. 5 is the circuit simulation figure under superthreshold threshold voltage (0.8v), horizontal seat
Mark represents simulation time, and vertical coordinate V (CLK) represents the amplitude voltage of clock signal clk, and V (D) represents the amplitude of input signal D
Voltage, V (Q) represents the amplitude voltage of output signal Q.Analysis Fig. 4 and Fig. 5 it is recognised that the master-slave flip-flop of the present invention not only
There is high-speed low-power-consumption feature with correct logic function, wherein master-slave flip-flop is operated in superthreshold threshold voltage (0.8v) condition
Under propagation delay be operated in propagation delay under the conditions of normal voltage (1v) relative to master-slave flip-flop and increase by 14% or so, but
The lower power consumption of circuit 38% or so.
Under 32nm techniques, respectively to two kinds of master-slave flip-flop (multichannels of master-slave flip-flop and prior art of the invention
Switching mode master-slave flip-flop and force impulse type master-slave flip-flop) propagation delay and circuit energy consumption contrasted, wherein propagating
Time delay comparative analysiss figure is as shown in fig. 6, unit switch observable index is as shown in Figure 7 compared with analysis chart.Knowable to analysis Fig. 6 and Fig. 7,
Under 32nm FinFET techniques, when the master-slave flip-flop circuit of the present invention is operated in normal voltage (1v), the master-slave flip-flop
Circuit power consumption reduces about 66% than the circuit power consumption of two kinds of master-slave flip-flops of prior art, and propagation delay is reduced about
48%.
Claims (2)
1. a kind of master-slave flip-flop based on FinFET transistors, it is characterised in that including the first p-type FinFET pipe, the second p-type
FinFET pipe, the 3rd p-type FinFET pipe, the 4th p-type FinFET pipe, the 5th p-type FinFET pipe, the first N-type FinFET pipe, second
N-type FinFET pipe, the 3rd N-type FinFET pipe, the 4th N-type FinFET pipe, the 5th N-type FinFET are managed, the 6th N-type FinFET is managed,
7th N-type FinFET is managed and the 8th N-type FinFET pipe；
The source electrode of the first described p-type FinFET pipe, the source electrode of the second described p-type FinFET pipe, the 4th described p-type
It is the source electrode of FinFET pipes, the source electrode of the 5th described p-type FinFET pipe, the substrate of the first described p-type FinFET pipe, described
The substrate of the second p-type FinFET pipe, the substrate of the 3rd described p-type FinFET pipe, the substrate of the 4th described p-type FinFET pipe
Power supply is accessed with the substrate of the 5th described p-type FinFET pipe；
The substrate of the first described N-type FinFET pipe, the substrate of the second described N-type FinFET pipe, the 3rd described N-type
It is the substrate of FinFET pipes, the substrate of the 4th described N-type FinFET pipe, the substrate of the 5th described N-type FinFET pipe, described
The substrate of the 6th N-type FinFET pipe, the substrate of the 7th described N-type FinFET pipe, the lining of the 8th described N-type FinFET pipe
Bottom, the source electrode of the first described N-type FinFET pipe, the source electrode of the 5th described N-type FinFET pipe, the 7th described N-type
The source grounding of the source electrode of FinFET pipes and the 8th described N-type FinFET pipe；
The drain electrode of the second described N-type FinFET pipe is signal input part, and the drain electrode of the 3rd described N-type FinFET pipe is anti-phase
Signal input part；The grid of the second described N-type FinFET pipe, the grid of the 3rd described p-type FinFET pipe and described
The grid connection of three N-type FinFET pipes and its connection end are clock signal input terminal, the grid of described the 4th N-type FinFET pipe
Connect with the grid of the 6th described N-type FinFET pipe and its connection end is inverting clock signal input；
The drain electrode of the first described N-type FinFET pipe, the grid of the first described p-type FinFET pipe, the second described N-type
The drain electrode connection of the source electrode of FinFET pipes and the 4th described N-type FinFET pipe；The drain electrode of the first described p-type FinFET pipe,
The grid of the second described p-type FinFET pipe, the grid of the first described N-type FinFET pipe, described the 5th N-type FinFET pipe
Grid and the 3rd described N-type FinFET pipe source electrode connection；The drain electrode of the second described p-type FinFET pipe, described
The drain electrode of three p-type FinFET pipes, the drain electrode of the 5th described N-type FinFET pipe and the drain electrode of the 6th described N-type FinFET pipe
Connection；
The source electrode of the 3rd described p-type FinFET pipe, the drain electrode of the 4th described p-type FinFET pipe, the 5th described p-type
It is the grid of FinFET pipes, the source electrode of the 4th described N-type FinFET pipe, the source electrode of the 6th described N-type FinFET pipe, described
The drain electrode of the 7th N-type FinFET pipe and the grid of the 8th described N-type FinFET pipe connect and its connection end is signal output part；
The grid of the 4th described p-type FinFET pipe, the drain electrode of the 5th described p-type FinFET pipe, described the 7th N-type FinFET pipe
Grid and the 8th described N-type FinFET pipe drain electrode connection and its connection end be inversion signal outfan.
2. a kind of master-slave flip-flop based on FinFET transistors according to claim 1, it is characterised in that described
The channel length of one p-type FinFET pipe, the channel length of the second described p-type FinFET pipe, described the 3rd p-type FinFET pipe
Channel length, the channel length of the 4th described p-type FinFET pipe, channel length, the institute of the 5th described p-type FinFET pipe
The channel length of the first N-type FinFET pipe stated, the channel length of the second described N-type FinFET pipe, the 3rd described N-type
The channel length of FinFET pipes, the channel length of the 4th described N-type FinFET pipe, the ditch of the 5th described N-type FinFET pipe
Road length, the channel length of the 6th described N-type FinFET pipe, the channel length of the 7th described N-type FinFET pipe and described
The channel length of the 8th N-type FinFET pipe be 32nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410808899.XA CN104617915B (en) | 2014-12-23 | 2014-12-23 | Master-slave flip-flop based on FinFET transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410808899.XA CN104617915B (en) | 2014-12-23 | 2014-12-23 | Master-slave flip-flop based on FinFET transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104617915A CN104617915A (en) | 2015-05-13 |
| CN104617915B true CN104617915B (en) | 2017-04-26 |
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| CN201410808899.XA Expired - Fee Related CN104617915B (en) | 2014-12-23 | 2014-12-23 | Master-slave flip-flop based on FinFET transistor |
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| US12003242B2 (en) | 2022-11-01 | 2024-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having latch with transistors of different gate widths |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1431778A (en) * | 1995-09-05 | 2003-07-23 | 三菱电机株式会社 | Trigger circuit |
| EP0768758B1 (en) * | 1995-10-12 | 2004-01-02 | STMicroelectronics S.r.l. | Low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries |
| CN1855716A (en) * | 2005-04-29 | 2006-11-01 | 上海贝岭股份有限公司 | Structure and method for preventing primary and secondary trigger timers from interconnection |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070085585A1 (en) * | 2005-10-13 | 2007-04-19 | Arm Limited | Data retention in operational and sleep modes |
| TWI455129B (en) * | 2010-07-16 | 2014-10-01 | Univ Nat Chiao Tung | A schmitt trigger based finfet sub-threshold static random access memory (sram) cells |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1431778A (en) * | 1995-09-05 | 2003-07-23 | 三菱电机株式会社 | Trigger circuit |
| EP0768758B1 (en) * | 1995-10-12 | 2004-01-02 | STMicroelectronics S.r.l. | Low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries |
| CN1855716A (en) * | 2005-04-29 | 2006-11-01 | 上海贝岭股份有限公司 | Structure and method for preventing primary and secondary trigger timers from interconnection |
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| CN104617915A (en) | 2015-05-13 |
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