CN104615412A - Control flow executing method and system based on trigger instruction structure - Google Patents
Control flow executing method and system based on trigger instruction structure Download PDFInfo
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Abstract
The invention provides a control flow executing method based on a trigger instruction structure. The method comprises the following steps of 1, conducting initialization configuration; 2, obtaining triggering conditions of instructions according to the status of a processing unit and a triggering expression of the multiple instructions; 3, selecting the instructions conforming to the triggering conditions from the multiple instructions, the instructions conforming to the triggering conditions are divided into a preset number of sub-instructions through operators, transmitting bits for representing the control relationship between a preset number of operator instructions to the output control ends of corresponding arithmetic devices so as to select the executed control flow, and meanwhile sequentially distributing the preset number of sub-instructions to a preset number of arithmetic devices; 4, obtaining and outputting arithmetic results for representing the status of the processing unit when each arithmetic device executes arithmetic corresponding to the operators; 5, repeatedly executing the second, third and fourth steps until the circulation cut-off conditions are met. The method is good in real time performance and high in efficiency. The invention further provides a control flow executing system based on the trigger construction structure.
Description
Technical field
The present invention relates to field of computer technology, particularly relate to a kind of method and system of the execution control flow check based on triggering command structure.
Background technology
Coarseness reconfigurable processor is that one has dirigibility and high performance new types of processors framework concurrently, compared to traditional single core processor, special chip, field programmable logic array (FPLA) etc., especially in the algorithm of process computation-intensive, have the advantage of highly significant, be a direction of further circuits structural development.But there is significant limitation for controlling intensive algorithm, is the bottleneck of current reconfigurable processor improving performance.
Coarseness reconfigurable processor structure can be divided into centralized control structure and distributed control structure.On centralized control structure, whole (process element, PE) array shares a Configuration Control Unit.And for distributed control structure, each PE has respective Configuration Control Unit.Triggering command structure (triggered instruction architecture, TIA) is a kind of distributed control structure proposed in A.Parshar " Triggered instructions:a control paradigm for spatially programmed architectures " inISCA2013.When performing computing, once getting 16 instruction/configurations, and performing wherein one by trigger mechanism.This structure completely removes programmable counter (program counter, PC), the excessive serialized problem of the program that solves.In the structure shown here, the execution of next instruction/configuration is determined by the execution result of upper bar instruction/configuration, and the restriction of single PE resource, causes when performing control flow check and particularly processing larger control flow check, parallel instructions difficulty.
The types such as control flow check can be divided into long branch, short branch, uneven branch, nested branches, bounding cycle (period is determined), unbounded circulation (period is indefinite) structure.Wherein the division methods of long branch and short branch is based on the length of branch.Uneven branch refers to the branched structure that the length of two or more branches is different.Nested branches refers to the branched structure that multiple condition is mutually nested.The loop structure of indefinite period refers to that period is at the mark of the specified conditions met as end loop using the variable of loop body a certain dynamic change in the process of implementation.At present, a lot of method has been had for solving the bottleneck problem of control flow check for reconfigurable processor.Such as section declares performs (partial predication execution), states execution (full predication execution), the single execution of two transmitting (dual issue single execution), branch prediction (branch prediction), parallel condition (parallel condition) etc. completely.But current proposed method all can only be effective for the control flow check of some types.Wherein " parallel condition " proposes in J.Zhu " A Hybrid ReconfigurableArchitecture and Design Methods Aiming at Control-Intensive Kernels " in TVLSI2014.The method obtains higher performance when making to perform control flow check by parallel condition and branch.But because its basic structure is still centralized control structure, the dirigibility that controller is lower makes it can not obtain superior performance when the uneven branch of process.On the whole, due to the limitation of structure or method itself, the method of the control flow check problem that solves based on reconfigurable structures of current proposition, do not have one can tackle all types of control flow check, particularly for the control flow check of uneven branch and unbounded cyclical patterns, substantially do not have a kind of method or structure can ensure higher performance under the prerequisite ensureing correct work.
Summary of the invention
The present invention is intended to solve one of technical matters in correlation technique at least to a certain extent.For this reason, first aspect present invention object be to propose a kind of in real time, efficiently, the method for the execution control flow check based on triggering command structure that cost is low.
Second aspect present invention object is the system proposing a kind of execution control flow check based on triggering command structure.
To achieve these goals, the method of the execution control flow check based on triggering command structure of first aspect present invention embodiment, comprise the following steps: S1, initial configuration, comprise and read many instructions and trigger expression formula one to one with described many instructions, and being configured in processing unit, every bar instruction comprises predetermined number operator and the bit for representing control planning between predetermined number operator; S2, according to the state of described processing unit and the triggering expression formula of described many instructions, obtains the trigger condition of instruction; S3, the instruction meeting described trigger condition is chosen from described many instructions, according to described operator, the described instruction meeting trigger condition is divided into the sub-instructions of predetermined number, described being used for is represented that the bit of control planning between the instruction of predetermined number operator is delivered to the output control terminal of corresponding arithmetical unit to select the control flow check performed, the sub-instructions of described predetermined number is dispensed to successively the described arithmetical unit of predetermined number simultaneously; S4, each described arithmetical unit performs the computing corresponding with described operator, obtains and exports the operation result comprised for representing described processing unit state; And S5, repeated execution of steps S2 ~ S4, until reach circulation cut-off condition.
According to the method for the execution control flow check based on triggering command structure of the embodiment of the present invention, from many instructions, choose the instruction meeting trigger condition, call instruction is triggered by trigger mechanism.The triggering command of the bit comprised for representing control planning between the instruction of predetermined number operator is delivered to the output control terminal of corresponding arithmetical unit to select the control flow check performed, eliminate branch's jump instruction, achieve condition and branch parallel, improve performance.
In some instances, described predetermined number is at least 2.
The system of the execution control flow check based on triggering command structure of second aspect present invention embodiment, comprise multiple processing unit, each described processing unit comprises, order register, for storing many instructions, every bar instruction comprise predetermined value basic operator and for represent described predetermined value basic operator between the bit of control planning; Instruction triggers expression formula storer, triggers expression formula for storing one to one with described many instructions; Status register, for storing the current state of described processing unit, and configures the value of the triggering expression formula all elements of described each bar instruction; Scheduler, for according to the value of each element in described status register and described triggering expression formula, obtains the trigger condition of instruction; The arithmetical unit of predetermined number; Described scheduler is used for choosing the instruction meeting described trigger condition from described many instructions, according to described operator, the described instruction meeting trigger condition is divided into the sub-instructions of predetermined number, described being used for is represented that the bit of control planning between the instruction of predetermined number operator is delivered to the output control terminal of corresponding arithmetical unit to select the control flow check performed, the sub-instructions of described predetermined number is dispensed to successively the arithmetical unit of described predetermined number simultaneously; Described arithmetical unit performs the computing corresponding with described operator, obtains and exports the operation result comprised for representing described processing unit state.
According to the system of the execution control flow check based on triggering command structure of the embodiment of the present invention, from many instructions, choose the instruction meeting trigger condition, call instruction is triggered by trigger mechanism.The triggering command of the bit comprised for representing control planning between the instruction of predetermined number operator is delivered to the output control terminal of corresponding arithmetical unit to select the control flow check performed, eliminate branch's jump instruction, achieve condition and branch parallel, improve performance.
In some instances, described system also comprises: data register, for storing described operation result.
In some instances, described predetermined number is at least 2.
The aspect that the present invention adds and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present invention.
Accompanying drawing explanation
Fig. 1 is according to an embodiment of the invention based on the process flow diagram of the method for the execution control flow check of triggering command structure;
Fig. 2 is the implementation schematic diagram of the method for the execution control flow check based on triggering command structure of one embodiment of the invention;
Fig. 3 is the execution time schematic diagram of one embodiment of the invention;
Fig. 4 is according to an embodiment of the invention based on the block diagram of the system of the execution control flow check of triggering command structure;
Fig. 5 is the CDFG schematic diagram of the control flow check of the simple nested type of mapping of one embodiment of the invention.
Embodiment
In describing the invention, it will be appreciated that, term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ", " thickness ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward ", " clockwise ", " counterclockwise ", " axis ", " radial direction ", orientation or the position relationship of the instruction such as " circumference " are based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, instead of indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore limitation of the present invention can not be interpreted as.
In addition, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance or imply the quantity indicating indicated technical characteristic.Thus, be limited with " first ", the feature of " second " can express or impliedly comprise at least one this feature.In describing the invention, the implication of " multiple " is at least two, such as two, three etc., unless otherwise expressly limited specifically.
In the present invention, unless otherwise clearly defined and limited, the term such as term " installation ", " being connected ", " connection ", " fixing " should be interpreted broadly, and such as, can be fixedly connected with, also can be removably connect, or integral; Can be mechanical connection, also can be electrical connection; Can be directly be connected, also indirectly can be connected by intermediary, can be the connection of two element internals or the interaction relationship of two elements, unless otherwise clear and definite restriction.For the ordinary skill in the art, above-mentioned term concrete meaning in the present invention can be understood as the case may be.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature " on " or D score can be that the first and second features directly contact, or the first and second features are by intermediary indirect contact.And, fisrt feature second feature " on ", " top " and " above " but fisrt feature directly over second feature or oblique upper, or only represent that fisrt feature level height is higher than second feature.Fisrt feature second feature " under ", " below " and " below " can be fisrt feature immediately below second feature or tiltedly below, or only represent that fisrt feature level height is less than second feature.
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Be exemplary below by the embodiment be described with reference to the drawings, be intended to for explaining the present invention, and can not limitation of the present invention be interpreted as.
As shown in Figure 1, the method for the execution control flow check based on triggering command structure of first aspect present invention embodiment, comprises the following steps:
S1, initial configuration, comprise and read many instructions and trigger expression formula one to one with many instructions, and be configured in processing unit, every bar instruction comprises predetermined number operator and the bit for representing control planning between predetermined number operator;
S2, according to the state of processing unit and the triggering expression formula of many instructions, obtains the trigger condition of instruction;
S3, the instruction meeting trigger condition is chosen from many instructions, according to operator, the instruction meeting trigger condition is divided into the sub-instructions of predetermined number, representing that the bit of control planning between the instruction of predetermined number operator is delivered to the output control terminal of corresponding arithmetical unit to select the control flow check performed by being used for, the sub-instructions of predetermined number being dispensed to successively the arithmetical unit of predetermined number simultaneously;
S4, each arithmetical unit performs the computing corresponding with operator, obtains and exports the operation result comprised for representing processing unit state; And
S5, repeated execution of steps S2 ~ S4, until reach circulation cut-off condition.
The method of the execution control flow check based on triggering command structure of the embodiment of the present invention, is realized by multiple interconnected PE array.The interconnected of PE array can have multiple choices, repeats no more the interconnected of PE array herein and waits aspects.The structural representation of the single processing unit (process element, PE) of composition graphs 2, concrete implementation procedure is described below:
Step S1, initial configuration, comprise and read many instructions and trigger expression formula one to one with many instructions, and be configured in processing unit, every bar instruction comprises predetermined number operator and the bit for representing control planning between predetermined number operator.
In an example of the present invention, predetermined number is at least 2.In a concrete example, getting predetermined number is 3.These 3 respectively corresponding conditions and select the Liang Ge branch of circulation.
Stores many instructions, instruction triggers expression formula register stores many instructions trigger expression formula one to one for storing and instruction storer.Wherein, every bar instruction comprises at most predetermined number operator and the bit for representing control planning between predetermined number operator.
Initial configuration, namely carries out some settings to operational factor, such as, establishes the setup time of every bar instruction, the time of triggering and execution is 1.These instructions, before whole PE array runs, are configured in each PE and go.The triggering expression formula corresponding with these instructions is also stored in instruction triggers expression formula register.
Step S2, according to the state of processing unit and the triggering expression formula of many instructions, obtains the trigger condition of instruction.
Status register stores the running status of PE, and determines the value of the triggering expression formula all elements of each bar instruction.Scheduler is made up of the simple combinational logic of a pile, the triggering expression formula corresponding with each bar instruction according to the value of each element in status register, the predetermined condition of Real-time Obtaining triggering command, the instruction that namely will trigger.
Step S3, the instruction meeting trigger condition is chosen from many instructions, according to operator, the instruction meeting trigger condition is divided into the sub-instructions of predetermined number, representing that the bit of control planning between the instruction of predetermined number operator is delivered to the output control terminal of corresponding arithmetical unit to select the control flow check performed by being used for, the sub-instructions of predetermined number being dispensed to successively the arithmetical unit of predetermined number simultaneously.
Scheduler chooses the instruction that conforms to a predetermined condition as will triggering command from many instructions that order register stores, and is sent to data path (data path) (part for arithmetical unit).On data path, the operator of the predetermined number that triggering command comprises according to it is divided into the sub-instructions of predetermined number.A sub-instructions corresponding operator separately of this predetermined number, and the arithmetical unit sub-instructions of predetermined number being assigned to successively predetermined number gets on.Meanwhile, represent that the bit of the operator control planning of predetermined number is also transported to the output control terminal of corresponding arithmetical unit to select the control flow check performed.Namely in Fig. 2, the parallel control process of condition and spoke 1 and spoke 2.Like this, instruction triggers just can executed in parallel with the computing with control planning.
Step S4, each arithmetical unit performs the computing corresponding with operator, obtains and exports the operation result comprised for representing processing unit state.
Arithmetical unit performs the computing corresponding with operator, and exports the operation result comprising Data Update and state updating from arithmetical unit.The port of the state updating of control algorithm device also can be used as control signal simultaneously, adds mark to two other arithmetical unit output valve.Whether these marks can the action of characterization data, be namely stored in corresponding register, storer or status register.
Below for one section of simple C code, composition graphs 2, illustrates the implementation of the method for the embodiment of the present invention:
Originally, initial configuration, sets execution time Tconfig to the implementation of this section of simple C code.Executive condition (a unequal to b), and the execution of the Liang Tiao branch (and if else) of condition can be overlapping a part of with the execution of condition, if condition execution time Tcond, the Liang Ge branch execution time is respectively Tpath_sel_exe and Tpath_unsel_exe, the execution time Toverlap of lap.Therefore for a simple control flow check, total execution time can think Ttotal=Tconfig+Tcond+Tpath_sel_exe-Toverlap.Whether the operator that the length of lap depends on this branch (as deposits the data register of net result, or the register that other positions very fast (as the next cycle) can have access to the critical registers of PE.) and storer etc. change.If only have an operator to have impact to the critical data on PE, can make condition directly and branch parallel in the control bit position that output terminal increases.As can be seen from Figure 3, under the prerequisite not increasing register pressure, in the execution example of this section of C code, the execution time of control flow check obtains maximum reduction.
S5, repeated execution of steps S2 ~ S4, until reach circulation cut-off condition.
The circulation cut-off condition of C code as escribed above is a=b.
In a concrete example, for 16 instructions.The scale of instruction is determined according to scheduler.
Article (1) 16, instruction is configured in PE, and wherein every bar instruction can comprise at most 3 operators and represent the bit of control planning between these 3 operators.Trigger expression formula one to one to 16 instructions is also stored into corresponding storer simultaneously simultaneously.
(2) external trigger PE brings into operation.By the triggering expression formula completion logic computing of scheduler according to the running status of the PE of status register and all instructions, obtain predetermined condition, one that selects to conform to a predetermined condition in 16 instructions is sent to data path as triggering command.
(3) on data path, triggering command is divided into three parts, and this three part is a corresponding operator separately, is assigned to three arithmetical unit successively and gets on.Meanwhile, represent that the bit of three operator control planning is also transported to corresponding arithmetical unit output control terminal.
(4) each arithmetical unit performs the computing corresponding with its operator, and comprise Data Update and state updating from arithmetical unit output and operation result.The operation result of state updating is stored to status register.The port of the state updating of control algorithm device also can be used as control signal simultaneously, adds mark to two other arithmetical unit output valve.Whether these marks can the action of characterization data, be namely stored in corresponding register, storer or status register.
(5) after status register has been updated, repeat (2) ~ (4), the execution that so moves in circles down until meet cut-off condition.
According to the method for the execution control flow check based on triggering command structure of the embodiment of the present invention, from many instructions, choose the instruction meeting trigger condition, call instruction is triggered by trigger mechanism.The triggering command of the bit comprised for representing control planning between the instruction of predetermined number operator is delivered to the output control terminal of corresponding arithmetical unit to select the control flow check performed, eliminate branch's jump instruction, achieve condition and branch parallel, improve performance.
The system 10 of the execution control flow check based on triggering command structure of second aspect present invention embodiment, comprise: multiple processing unit, each processing unit, as shown in Figure 4, comprise, the arithmetical unit 500 of order register 100, instruction triggers expression formula storer 200, status register 300, scheduler 400 and predetermined number.
Order register 100 for storing many instructions, every bar instruction comprise at most predetermined value basic operator and for represent predetermined value basic operator between the bit of control planning.Instruction triggers expression formula storer 200 triggers expression formula for storing one to one with many instructions.Status register 300 for the current state of storage processing unit, and configures the value of the triggering expression formula all elements of each bar instruction.Scheduler 400, for according to the value of each element in status register with trigger expression formula, obtains the predetermined condition of triggering command.Scheduler 400 also for choosing the instruction conformed to a predetermined condition from many instructions, according to operator, the instruction conformed to a predetermined condition is divided into the sub-instructions of predetermined number, representing that the bit of control planning between the instruction of predetermined number operator is delivered to the output control terminal of corresponding arithmetical unit 500 to select the control flow check performed by being used for, the sub-instructions of predetermined number being dispensed to successively the arithmetical unit 500 of predetermined number simultaneously.Arithmetical unit 500 performs the computing corresponding with operator, obtains and exports the operation result comprised for representing processing unit state.
In one embodiment of the invention, system 10 also comprises: data register 600.Data register 600 is for storing operation result.
It should be noted that, the specific implementation of the system of the execution control flow check based on triggering command structure of the embodiment of the present invention and the specific implementation of method part similar, referring to the description of method part, in order to reduce redundancy, not repeating herein.
In a concrete example, the CDFG (control-data flow graph) of the control flow check of a simple nested type as shown in Figure 5:
In Fig. 5, C represents condition (condition), and P represents branch (path).Fig. 5 (a) schemes for original CDFG, altogether three layers nested, belong to the control flow check of nested branches structure type.The CDFG figure of Fig. 5 (a), has two kinds of methods mapped according to the PE of the embodiment of the present invention, and the CDFG figure after the conversion shown in Fig. 5 (b) He Fig. 5 (c) all can be mapped on the PE of the embodiment of the present invention.Nested condition performs by Fig. 5 (b) in advance simultaneously, namely condition C 1-C2-C3 performs in advance, determine the branch performed again, the method is when the execution probability of each branch is different, execution time is determined relatively, thus for branch perform probability uncertain and the nested number of plies is more time, can as map selection.Fig. 5 (c) utilizes the feature that in the PE of the embodiment of the present invention, branch and condition can walk abreast, i.e. C0-P0-P1 condition C 0 and the operator P0 in its Liang Tiao branch and P1 executed in parallel.Like this when the execution probability of some branch in control flow check can be determined, higher performance can be realized.Except the example of Fig. 5, also have very eurypalynous control flow check, as short branched structure, long branched structure and unbalanced construction, and the combined nesting etc. between them.According to different situations, corresponding method can be selected.
According to the system of the execution control flow check based on triggering command structure of the embodiment of the present invention, from many instructions, choose the instruction meeting trigger condition, call instruction is triggered by trigger mechanism.The triggering command of the bit comprised for representing control planning between the instruction of predetermined number operator is delivered to the output control terminal of corresponding arithmetical unit to select the control flow check performed, eliminate branch's jump instruction, achieve condition and branch parallel, improve performance.
In the description of this instructions, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, to the schematic representation of above-mentioned term not must for be identical embodiment or example.And the specific features of description, structure, material or feature can combine in one or more embodiment in office or example in an appropriate manner.In addition, when not conflicting, the feature of the different embodiment described in this instructions or example and different embodiment or example can carry out combining and combining by those skilled in the art.
Although illustrate and describe embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, and those of ordinary skill in the art can change above-described embodiment within the scope of the invention, revises, replace and modification.
Claims (5)
1., based on a method for the execution control flow check of triggering command structure, it is characterized in that, comprise the following steps:
S1, initial configuration, comprise and read many instructions and trigger expression formula one to one with described many instructions, and be configured in processing unit, every bar instruction comprises predetermined number operator and the bit for representing control planning between predetermined number operator;
S2, according to the state of described processing unit and the triggering expression formula of described many instructions, obtains the trigger condition of instruction;
S3, the instruction meeting described trigger condition is chosen from described many instructions, according to described operator, the instruction meeting described trigger condition is divided into the sub-instructions of predetermined number, described being used for is represented that the bit of control planning between the instruction of predetermined number operator is delivered to the output control terminal of corresponding arithmetical unit to select the control flow check performed, the sub-instructions of described predetermined number is dispensed to successively the described arithmetical unit of predetermined number simultaneously;
S4, each described arithmetical unit performs the computing corresponding with described operator, obtains and exports the operation result comprised for representing described processing unit state; And
S5, repeated execution of steps S2 ~ S4, until reach circulation cut-off condition.
2. the method for claim 1, is characterized in that, described predetermined number is at least 2.
3. based on a system for the execution control flow check of triggering command structure, it is characterized in that, comprise multiple processing unit, each described processing unit comprises,
Order register, for storing many instructions, every bar instruction comprise predetermined value basic operator and for represent described predetermined value basic operator between the bit of control planning;
Instruction triggers expression formula storer, triggers expression formula for storing one to one with described many instructions;
Status register, for storing the current state of described processing unit, and configures the value of the triggering expression formula all elements of described each bar instruction;
Scheduler, for according to the value of each element in described status register and described triggering expression formula, obtains the trigger condition of instruction;
The arithmetical unit of predetermined number, described scheduler is used for choosing the instruction meeting described trigger condition from described many instructions, according to described operator, the described instruction meeting trigger condition is divided into the sub-instructions of predetermined number, described being used for is represented that the bit of control planning between the instruction of predetermined number operator is delivered to the output control terminal of corresponding arithmetical unit to select the control flow check performed, the sub-instructions of described predetermined number is dispensed to successively the arithmetical unit of described predetermined number simultaneously;
Described arithmetical unit performs the computing corresponding with described operator, obtains and exports the operation result comprised for representing described processing unit state.
4. system as claimed in claim 3, it is characterized in that, described system also comprises:
Data register, for storing described operation result.
5. system as claimed in claim 3, it is characterized in that, described predetermined number is at least 2.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109947564A (en) * | 2019-03-07 | 2019-06-28 | 阿里巴巴集团控股有限公司 | Method for processing business, device, equipment and storage medium |
| CN112165499A (en) * | 2020-12-01 | 2021-01-01 | 南京芯驰半导体科技有限公司 | Control flow monitoring method and device and storage medium |
| CN112463717A (en) * | 2020-11-05 | 2021-03-09 | 上海交通大学 | Conditional branch implementation method under coarse-grained reconfigurable architecture |
| CN114443142A (en) * | 2022-01-29 | 2022-05-06 | 上海阵量智能科技有限公司 | Method, device, chip, electronic equipment and storage medium for processing loop instruction |
| GB2625512A (en) * | 2022-12-12 | 2024-06-26 | Advanced Risc Mach Ltd | Triggered-producer and triggered-consumer instructions |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050229018A1 (en) * | 2002-05-24 | 2005-10-13 | Koninklijke Philips Electronics N.V. | Configurable processor |
| CN1746842A (en) * | 2004-09-08 | 2006-03-15 | 三星电子株式会社 | The hardware unit and the manner of execution thereof that are used for condition commands in disorder |
| CN101965554A (en) * | 2008-03-11 | 2011-02-02 | 高通股份有限公司 | System and method of selectively committing a result of an executed instruction |
-
2015
- 2015-02-10 CN CN201510069989.6A patent/CN104615412B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050229018A1 (en) * | 2002-05-24 | 2005-10-13 | Koninklijke Philips Electronics N.V. | Configurable processor |
| CN1746842A (en) * | 2004-09-08 | 2006-03-15 | 三星电子株式会社 | The hardware unit and the manner of execution thereof that are used for condition commands in disorder |
| CN101965554A (en) * | 2008-03-11 | 2011-02-02 | 高通股份有限公司 | System and method of selectively committing a result of an executed instruction |
Non-Patent Citations (1)
| Title |
|---|
| ANGSHUMAN PARASHAR ET AL.: ""Triggered Instructions: A Control Paradigm for Spatially-Programmed Architectures"", 《ACM SIGARCH COMPUTER ARCHITECTURE NEWS》 * |
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| CN109947564A (en) * | 2019-03-07 | 2019-06-28 | 阿里巴巴集团控股有限公司 | Method for processing business, device, equipment and storage medium |
| CN109947564B (en) * | 2019-03-07 | 2023-04-11 | 蚂蚁金服（杭州）网络技术有限公司 | Service processing method, device, equipment and storage medium |
| CN112463717A (en) * | 2020-11-05 | 2021-03-09 | 上海交通大学 | Conditional branch implementation method under coarse-grained reconfigurable architecture |
| CN112463717B (en) * | 2020-11-05 | 2022-07-22 | 上海交通大学 | Conditional branch implementation method under coarse-grained reconfigurable architecture |
| CN112165499A (en) * | 2020-12-01 | 2021-01-01 | 南京芯驰半导体科技有限公司 | Control flow monitoring method and device and storage medium |
| CN114443142A (en) * | 2022-01-29 | 2022-05-06 | 上海阵量智能科技有限公司 | Method, device, chip, electronic equipment and storage medium for processing loop instruction |
| GB2625512A (en) * | 2022-12-12 | 2024-06-26 | Advanced Risc Mach Ltd | Triggered-producer and triggered-consumer instructions |
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