CN104576713A - Pn junction and preparation method - Google Patents

Abstract

The invention discloses a pn junction and a preparation method thereof. The pn junction includes an n-type Si semiconductor layer and a p-type SnO semiconductor layer located in the middle region of the n-type Si semiconductor layer, wherein the n-type Si semiconductor layer is A first electrode is provided; a second electrode is provided on the p-type SnO semiconductor layer. The pn junction of the invention has obvious rectification effect, can be applied to semiconductor devices such as light-emitting diodes, solar cells, photodetectors, gas sensors, etc., and expands the application range of the stannous oxide.

Description

pn junction and its preparation method

technical field

The invention relates to the technical field of semiconductors, in particular to a pn junction and a preparation method thereof.

Background technique

With the rapid development of transparent electronics, the oxide semiconductor pn junction has become a research hotspot. Due to the intrinsic defects of oxides and the limitation of preparation technology, stable and high-performance p-type hole-conducting materials are scarce.

As an emerging intrinsic p-type oxide semiconductor material, SnO has great application potential. At present, for SnO semiconductors, Hiroshi Yanagi et al. have prepared a SnO homojunction with a pulsed laser method, with a turn-on voltage of 0.7V and a rectification ratio of 25 at ±2V (Bipolar Conduction in SnOThin Films, Hideo Hosono, Yoichi Ogo etal, Electrochemical and Solid-State Letters, 2011,14,1); K.C.Sanal et al prepared a p-SnO/n-ZnO heterogeneous pn junction by magnetron sputtering method, its turn-on voltage is 3V, at ±4.5V When the rectification ratio is 12 (Growth and Characterization of Tin Oxide Films and Fabrication of Transparent p-SnO/n-ZnO p-n heterojunction, Materials Science and Engineering B, 2013, 178, 12).

Due to the lack of research on SnO semiconductors, the types of pn junctions prepared by SnO are limited, which greatly restricts the application of SnO. Therefore, using SnO to develop new pn junctions has become a current research trend.

Contents of the invention

Based on the above problems, the present invention provides a pn junction containing SnO and a preparation method thereof. The pn junction has excellent performance and a simple preparation method.

To achieve the above object, the present invention adopts the following technical solutions:

A pn junction comprising

an n-type Si semiconductor layer on which a first electrode is disposed; and

A p-type SnO semiconductor layer located in the middle region of the n-type Si semiconductor layer, and a second electrode is arranged on the p-type SnO semiconductor layer.

In one of the embodiments, the cross section of the p-type SnO semiconductor layer is circular;

The cross section of the first electrode is circular, and the circular first electrode surrounds the p-type SnO semiconductor layer in its inner ring;

The cross-section of the second electrode is circular, and the cross-sectional area of the second electrode is smaller than the cross-sectional area of the p-type SnO semiconductor layer.

In one of the embodiments, the thickness of the p-type SnO semiconductor layer is 50nm-80nm;

Both the first electrode and the second electrode have a thickness of 40nm-100nm.

In one embodiment, the first electrode and the second electrode are Ni-Au double-layer electrodes, Cu-Au double-layer electrodes or Ag-Au double-layer electrodes.

A method for preparing a pn junction, comprising the steps of:

S100: Depositing a layer of p-type SnO semiconductor on the Si semiconductor to obtain a Si-SnO composite;

S200: Depositing a first electrode on the n-type Si semiconductor in the Si-SnO composite, and depositing a second electrode on the SnO semiconductor in the Si-SnO composite to obtain p-SnO/n-Si heterogeneity Knot.

In one of the embodiments, the S100 includes the following steps:

Coating photoresist on the surface of the n-type Si semiconductor to form a first mask;

UV lithography of the first mask to form a first window on the n-type Si semiconductor;

A layer of p-type SnO semiconductor is deposited on the surface of the first window by electron beam evaporation to obtain a Si-SnO complex.

In one of the embodiments, the S200 includes the following steps:

Coating photoresist on the surface of the Si-SnO composite to form a second mask;

UV lithography of the second mask, forming a second window on the n-type Si semiconductor in the Si-SnO complex, and simultaneously forming a third window on the SnO semiconductor in the Si-SnO complex;

depositing a first electrode on the second window by electron beam evaporation, and simultaneously depositing a second electrode on the third window;

Removing the photoresist remaining on the surface of the Si-SnO complex after the electrodes are deposited to obtain a p-SnO/n-Si heterojunction.

In one of the embodiments, before S200, the following steps are also included:

Removing the photoresist remaining on the surface of the Si-SnO composite body and performing heat treatment on the Si-SnO composite body, the conditions of the heat treatment are: under a protective atmosphere, keep warm at 300°C-400°C for 10min-20min.

In one of the embodiments, the first window is a circular window;

The second window is a ring-shaped window, and the ring-shaped window surrounds the SnO semiconductor layer in its inner ring;

The third window is a circular window, and the area of the circular window is smaller than that of the first window.

In one of the embodiments, the thickness of the deposited p-type SnO semiconductor is 50nm-80nm;

Both the deposited first electrode and the second electrode have a thickness of 40nm-100nm.

The beneficial effects of the present invention are as follows:

The pn junction of the present invention includes n-type Si semiconductor and p-type SnO semiconductor, has obvious rectification effect, can be applied to semiconductor devices such as light-emitting diodes, solar cells, photodetectors, gas sensors, and strengthens the application of tin oxide; At the same time, the circular and ring-shaped electrodes can significantly reduce the edge discharge effect and improve the performance of the pn junction.

Utilize the preparation method of pn junction of the present invention, can obtain p-SnO/n-Si heterojunction, its preparation process is simple, and cost is low; pollutants, which can improve precision and facilitate the miniaturization of devices; at the same time, electron beam evaporation can be used to deposit thin films, which can effectively increase the quality of deposited films, thereby improving the performance of devices.

Description of drawings

Fig. 1 is a sectional view of an embodiment of a pn junction of the present invention;

Fig. 2 is a top view of the pn junction shown in Fig. 1;

Fig. 3 is the current-voltage characteristic curve of the p-SnO/n-Si heterojunction obtained in embodiment 1;

Fig. 4 is the current-voltage characteristic curve of the p-SnO/n-Si heterojunction obtained in embodiment 2;

Fig. 5 is the current-voltage characteristic curve of the p-SnO/n-Si heterojunction obtained in embodiment 3;

Fig. 6 is the current-voltage characteristic curve of the p-SnO/n-Si heterojunction obtained in embodiment 4;

Fig. 7 is the current-voltage characteristic curve of the p-SnO/n-Si heterojunction obtained in embodiment 5;

Fig. 8 is the current-voltage characteristic curve of the p-SnO/n-Si heterojunction obtained in embodiment 6;

Fig. 9 is the current-voltage characteristic curve of the p-SnO/n-Si heterojunction obtained in embodiment 7;

Fig. 10 is the current-voltage characteristic curve of the p-SnO/n-Si heterojunction obtained in embodiment 8;

FIG. 11 is a current-voltage characteristic curve of the p-SnO/n-Si heterojunction obtained in Example 9. FIG.

Detailed ways

Specific embodiments of the present invention will be described in detail below. It should be understood that the specific embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

1 and 2, the present invention provides a pn junction, including an n-type Si semiconductor layer 110 and a p-type SnO semiconductor layer 120 located in the middle region of the n-type Si semiconductor layer 110; wherein, the n-type Si semiconductor layer 110 A first electrode 112 is disposed on the p-type SnO semiconductor layer 120 , and a second electrode 122 is disposed on the p-type SnO semiconductor layer 120 . It should be noted that, the middle region of the n-type Si semiconductor layer 110 mentioned in the present invention is not limited to the center of the n-type Si semiconductor layer 110 , and generally refers to the region except the edge.

Preferably, as an implementation manner, the p-type SnO semiconductor layer 120 has a circular cross section. The structure is simple in design and easy to implement. In other embodiments, the cross section of the p-type SnO semiconductor layer 120 may also be in other shapes, such as a regular quadrangle or other polygons.

Preferably, the cross section of the first electrode 112 is circular, and the circular first electrode 112 surrounds the p-type SnO semiconductor layer 120 in its inner ring; further, the cross section of the second electrode 122 is circular, and the cross-sectional area of the second electrode 122 is smaller than that of the p-type SnO semiconductor layer 120 . Compared with the polygonal electrode, the electrode of this embodiment is circular or circular, which increases the uniformity of the charge on the edge of the electrode, avoids the edge discharge effect caused by the concentration of charge density near the tip of the polygon, and improves the stability of the pn junction. Comprehensive performance.

Preferably, when the cross section of the first electrode 112 is circular, and the cross section of the second electrode 122 and the p-type SnO semiconductor layer 120 is circular, the first electrode 112, the second electrode 122 and the p-type SnO semiconductor layer The cross-section of layer 120 is concentric circles. The pn junction obtained in this way has excellent performance, and the structure design is reasonable, and the preparation is convenient.

In the preparation process of the pn junction of the present invention, if the deposition thickness of the p-type SnO semiconductor layer 120 is too small, the performance of the formed pn junction is poor and cannot meet the practical application; if the deposition thickness is too large, not only the cost is increased, Moreover, it is not conducive to the development trend of miniaturization of devices. Therefore, the thickness of the p-type SnO semiconductor layer 120 is preferably 50nm-80nm, within this thickness range, the obtained pn junction has obvious rectifying effect.

In the pn junction of the present invention, if the cross-sectional area of the electrode is too small, large resistance will be generated, and the preparation is difficult; if the cross-sectional area of the electrode is too large, electric leakage will easily occur and the safety performance of the device will be reduced. Preferably, as an implementation manner, the ratio of the cross-sectional area of the second electrode 122 to the cross-sectional area of the p-type SnO semiconductor layer 120 is 1:10-9:10, and the ratio of the cross-sectional area of the first electrode 112 to The cross-sectional area ratio of the second electrode 122 is 0.5:1˜2:1.

Preferably, in the present invention, both the first electrode 112 and the second electrode 122 are double-layer electrodes, preferably one of Ni-Au double-layer electrodes, Cu-Au double-layer electrodes and Ag-Au double-layer electrodes. These double-layer electrodes have excellent electrical conductivity, which can effectively reduce resistance, and these double-layer electrodes have high temperature resistance, can be used in different environments, and enhance the service life of the pn junction. It should be noted that, in the present invention, the materials of the first electrode 112 and the second electrode 122 can be the same or different; meanwhile, the double-layer electrode mentioned in the present invention refers to an electrode formed of two metal material layers, For example, a Ni-Au double-layer electrode refers to an electrode formed of a Ni metal layer and an Au metal layer, and a Cu-Au double-layer electrode refers to an electrode formed of a Cu metal layer and an Au metal layer.

The pn junction of the present invention includes n-type Si semiconductor and p-type SnO semiconductor, has obvious rectification effect, can be applied to semiconductor devices such as light-emitting diodes, solar cells, photodetectors, gas sensors, and strengthens the application of tin oxide; At the same time, the circular and ring-shaped electrodes can significantly reduce the edge discharge effect and improve the performance of the pn junction.

In addition, the present invention also provides a method for preparing a pn junction, which can be used to prepare the above p-SnO/n-Si heterojunction, comprising the following steps:

S100: Deposit a layer of p-type SnO semiconductor on the Si semiconductor to obtain a Si-SnO composite.

Preferably, as an implementable manner, S100 includes the following steps:

S110: Coating a photoresist on the surface of the n-type Si semiconductor to form a first mask.

Preferably, the specific method of step S110 is: spin-coat the photoresist on the n-type silicon wafer to form a thin film; The solvent in the glue is volatilized, that is, the first mask is formed on the surface of the n-type silicon wafer.

S120: UV lithography of the first mask to form a first window on the n-type Si semiconductor, preferably, the first window is located in the middle region of the surface of the n-type Si semiconductor.

This step is a pattern transferring step, that is, transferring the pattern of the mask plate to the first mask to obtain the required pattern structure. Wherein, the pattern transfer can be carried out by wet etching or dry etching. However, the controllability and precision of wet etching are low, and the chemical reagents used in the etching process will pollute the environment; dry etching has high precision and controllability, but the traditional dry etching Etching, such as plasma etching, has high requirements on equipment, and the process is complicated, resulting in an increase in manufacturing costs.

As a preference, in this implementation mode, ultraviolet lithography is used to pattern the first mask. This method can not only avoid pollutants generated during the etching process, but also realize the etching of small-aperture windows, with high precision and effective contribute to the miniaturization of devices.

S130: Deposit a layer of p-type SnO semiconductor on the surface of the first window by electron beam evaporation to obtain a Si—SnO composite.

Wherein, the p-type SnO semiconductor layer can be deposited by a pulsed laser method, or by a magnetron sputtering method. Preferably, the electron beam evaporation method is used in this embodiment to deposit the p-type SnO semiconductor layer. Compared with the pulse laser method and magnetron sputtering method, the film obtained by this method has high quality, good uniformity and low cost.

Preferably, the thickness of the p-type SnO semiconductor layer deposited in this step is 50nm-80nm.

S200: Depositing a first electrode on the n-type Si semiconductor in the Si-SnO composite, and depositing a second electrode on the SnO semiconductor in the Si-SnO composite to obtain a p-SnO/n-Si heterojunction.

Preferably, before step S200, the following steps are also included: removing the remaining photoresist on the surface of the Si-SnO composite obtained in S100 and performing heat treatment on the Si-SnO composite, wherein the conditions of the heat treatment are: under a protective atmosphere , at 300°C to 400°C for 10min to 20min, and the protective atmosphere is preferably a nitrogen atmosphere or an argon atmosphere. This embodiment increases the density of SnO, reduces its internal stress, and is beneficial to the improvement of the performance of the pn junction.

As an implementable manner, S200 includes the following steps:

S210: Coating photoresist on the surface of the Si—SnO composite obtained in step S100 to form a second mask.

The photoresist coating process in this step can be performed in the same steps as in step S110. It should be noted that, in this step, the side of the Si-SnO complex on which the SnO is deposited is coated with a photoresist.

S220: UV lithography of the second mask, forming a second window on the n-type Si semiconductor in the Si-SnO composite, and simultaneously forming a third window on the SnO semiconductor in the Si-SnO composite.

This step is a patterning process of the second mask. It should be noted that in other embodiments, the second mask may also be patterned in other ways (such as plasma etching, chemical etching).

Preferably, the second window is a ring-shaped window, and the ring-shaped window surrounds the SnO semiconductor layer in its inner ring; more preferably, the third window is a circular window, and the area of the circular window is smaller than the area of the first window. This method avoids the edge discharge effect caused by the concentration of charge density near the tip of the polygon, and improves the performance of the pn junction.

S230: Deposit the first electrode on the second window by electron beam evaporation, and deposit the second electrode on the third window at the same time.

In this step, the electron beam evaporation method is used to deposit the first electrode and the second electrode, and this method has a fast deposition rate and a high deposition quality. In addition, the deposition of the first electrode and the second electrode may also be performed by means of magnetron sputtering, pulsed laser deposition, and the like.

As a possible implementation mode, the materials of the first electrode and the second electrode are both double-layer electrodes, preferably Ni-Au double-layer electrodes, Cu-Au double-layer electrodes or Ag-Au double-layer electrodes; preferably, the second The thicknesses of the first electrode and the second electrode are both 40nm-100nm.

S240: removing the remaining photoresist on the surface of the Si-SnO composite body after the electrodes are deposited, to obtain a p-SnO/n-Si heterojunction. As an implementation manner, the Si—SnO composite body can be soaked and cleaned in acetone, and then cleaned with deionized water. In addition, other methods in the prior art may also be used to clean the remaining photoresist.

In step S210 to step S240, since the first electrode and the second electrode are prepared at the same time, the materials of the two electrodes must be the same. When the first electrode and the second electrode are required to be made of different materials, the following method can be used for preparation:

S210': coating the surface of the Si-SnO composite obtained in step S100 with photoresist to form a second mask;

S220': UV lithography second mask, forming a second window on the n-type Si semiconductor in the Si-SnO composite;

S230': Depositing the first electrode on the second window by electron beam evaporation and cleaning the remaining photoresist;

S240': coating a photoresist on the surface of the Si-SnO composite deposited with the first electrode to form a third mask;

S250': a third mask for ultraviolet lithography, forming a third window on the p-type SnO semiconductor in the Si-SnO composite;

S260': Depositing a second electrode on the third window by electron beam evaporation and cleaning the remaining photoresist to obtain a p-SnO/n-Si heterojunction.

In addition, the second electrode can also be deposited first, and then the first electrode can be deposited.

In the present invention, multiple p-SnO/n-Si heterojunctions can be prepared simultaneously on the same n-type Si semiconductor, so as to increase the preparation speed and save the preparation cost.

The p-SnO/n-Si heterojunction can be obtained by the method of the present invention, the preparation process is simple, and the cost is low; the etching of the mask can be carried out by using ultraviolet light, which avoids the pollutants generated in the etching process and improves the etching process. The etching precision is beneficial to realize the miniaturization of the device; in addition, the deposition of thin film by electron beam evaporation can effectively increase the quality of the deposited film layer, thereby improving the performance of the device.

In order to better understand the present invention, the pn junction and its preparation method of the present invention will be further described below through specific examples.

Example 1

(1) Cut the n-type single-polished silicon wafer with ρ<0.01Ωcm into sample silicon wafers of 1.5*1.5cm ² , and clean and dry them;

(2) Spin-coat a layer of photoresist on the <100> crystal plane of the sample silicon wafer to form a first mask;

(3) Form a circular window with a diameter of 160 μm by using the first mask of ultraviolet lithography;

(4) Utilize electron beam evaporation equipment to evaporate the tin dioxide evaporation material at room temperature, and deposit an amorphous SnO semiconductor layer on the circular window to obtain a Si-SnO composite body; wherein, the deposition thickness of the SnO semiconductor layer is 80nm;

(5) utilizing acetone and deionized water to clean the Si-SnO complex obtained in step (4);

(6) Place the cleaned Si-SnO composite in a rapid annealing furnace, and anneal at 350° C. for 10 minutes under an argon atmosphere;

(7) Spin-coat a layer of photoresist on the surface of the Si-SnO composite body after annealing to form a second mask;

(8) Utilize the second mask of ultraviolet lithography to form an annular window on the n-type Si surface, and at the same time form a circular window with a diameter of 140 μm on the SnO semiconductor layer, and the annular window surrounds the SnO semiconductor layer in its inner ring ;

(9) Utilize electron beam evaporation equipment to evaporate the metal evaporation material at room temperature, and deposit a Ni-Au double-layer electrode on the circular window and the circular window with a diameter of 140 μm obtained in step (8), and the deposition thickness is Ni: 50nm, Au: 20nm, the deposition sequence is, deposit Ni first, then deposit Au;

(10) The sample obtained in step (9) was washed with acetone and deionized water, and dried with dry _N2 to obtain p-SnO/n-Si heterojunction.

Example 2

(1) Cut the n-type single-polished silicon wafer with ρ<0.01Ωcm into sample silicon wafers of 1.5*1.5cm ² , and clean and dry them;

(2) Spin-coat a layer of photoresist on the <100> crystal plane of the sample silicon wafer to form a first mask;

(3) Form a circular window with a diameter of 160 μm by using the first mask of ultraviolet lithography;

(4) Utilize electron beam evaporation equipment to evaporate the tin dioxide evaporation material at room temperature, and deposit an amorphous SnO semiconductor layer on the circular window to obtain a Si-SnO composite body; wherein, the deposition thickness of the SnO semiconductor layer is 80nm;

(5) utilizing acetone and deionized water to clean the Si-SnO complex obtained in step (4);

(6) Place the cleaned Si-SnO composite in a rapid annealing furnace, and anneal at 400°C for 10 minutes under an argon atmosphere;

(7) Spin-coat a layer of photoresist on the surface of the Si-SnO composite body after annealing to form a second mask;

(8) Utilize the second mask of ultraviolet lithography to form an annular window on the n-type Si surface, and at the same time form a circular window with a diameter of 140 μm on the SnO semiconductor layer, and the annular window surrounds the SnO semiconductor layer in its inner ring ;

(9) Utilize electron beam evaporation equipment to evaporate the metal evaporation material at room temperature, and deposit a Ni-Au double-layer electrode on the circular window and the circular window with a diameter of 140 μm obtained in step (8), and the deposition thickness is Ni: 50nm, Au: 20nm, the deposition sequence is, deposit Ni first, then deposit Au;

(10) The sample obtained in step (9) was washed with acetone and deionized water, and dried with dry _N2 to obtain p-SnO/n-Si heterojunction.

Example 3

(1) Cut n-type single-polished silicon wafers with ρ=(2～3)*10 ^-3 Ωcm into 1.5*1.5cm ² sample silicon wafers, and wash and dry them;

(2) Spin-coat a layer of photoresist on the <111> crystal plane of the sample silicon wafer to form a first mask;

(3) Form a circular window with a diameter of 160 μm by using the first mask of ultraviolet lithography;

(4) Utilize electron beam evaporation equipment to evaporate the tin dioxide evaporation material at room temperature, and deposit an amorphous SnO semiconductor layer on the circular window to obtain a Si-SnO composite body; wherein, the deposition thickness of the SnO semiconductor layer is 80nm;

(5) utilizing acetone and deionized water to clean the Si-SnO complex obtained in step (4);

(6) Place the cleaned Si-SnO composite in a rapid annealing furnace, and anneal at 350° C. for 10 minutes under an argon atmosphere;

(7) Spin-coat a layer of photoresist on the surface of the Si-SnO composite body after annealing to form a second mask;

(8) Utilize the second mask of ultraviolet lithography to form an annular window on the n-type Si surface, and at the same time form a circular window with a diameter of 140 μm on the SnO semiconductor layer, and the annular window surrounds the SnO semiconductor layer in its inner ring ;

(9) Utilize electron beam evaporation equipment to evaporate the metal evaporation material at room temperature, and deposit a Ni-Au double-layer electrode on the circular window and the circular window with a diameter of 140 μm obtained in step (8), and the deposition thickness is Ni: 50nm, Au: 20nm, the deposition sequence is, deposit Ni first, then deposit Au;

(10) The sample obtained in step (9) was washed with acetone and deionized water, and dried with dry _N2 to obtain p-SnO/n-Si heterojunction.

Example 4

(1) Cut the n-type single-polished silicon wafer with ρ<0.01Ωcm into sample silicon wafers of 1.5*1.5cm ² , and clean and dry them;

(2) Spin-coat a layer of photoresist on the <100> crystal plane of the sample silicon wafer to form a first mask;

(3) Form a circular window with a diameter of 160 μm by using the first mask of ultraviolet lithography;

(4) Utilize electron beam evaporation equipment to evaporate the tin dioxide evaporation material at room temperature, and deposit an amorphous SnO semiconductor layer on the circular window to obtain a Si-SnO composite body; wherein, the deposition thickness of the SnO semiconductor layer is 80nm;

(5) utilizing acetone and deionized water to clean the Si-SnO complex obtained in step (4);

(6) Place the cleaned Si-SnO composite in a rapid annealing furnace, and anneal at 350° C. for 10 minutes under a nitrogen atmosphere;

(7) Spin-coat a layer of photoresist on the surface of the Si-SnO composite body after annealing to form a second mask;

(8) Utilize the second mask of ultraviolet lithography to form an annular window on the n-type Si surface, and at the same time form a circular window with a diameter of 140 μm on the SnO semiconductor layer, and the annular window surrounds the SnO semiconductor layer in its inner ring ;

(9) Utilize electron beam evaporation equipment to evaporate the metal evaporation material at room temperature, and deposit Ni-Au double-layer electrodes on the circular window and the circular window with a diameter of 140 μm obtained in step (8), and the deposition thickness is Ni: 20nm, Au: 20nm, the deposition sequence is, deposit Ni first, then deposit Au;

(10) The sample obtained in step (9) was washed with acetone and deionized water, and dried with dry _N2 to obtain p-SnO/n-Si heterojunction.

Example 5

(1) Cut the n-type single-polished silicon wafer with ρ<0.01Ωcm into sample silicon wafers of 1.5*1.5cm ² , and clean and dry them;

(2) Spin-coat a layer of photoresist on the <100> crystal plane of the sample silicon wafer to form a first mask;

(3) Form a circular window with a diameter of 160 μm by using the first mask of ultraviolet lithography;

(4) Utilize electron beam evaporation equipment to evaporate the tin dioxide evaporation material at room temperature, and deposit an amorphous SnO semiconductor layer on the circular window to obtain a Si-SnO composite body; wherein, the deposition thickness of the SnO semiconductor layer is 80nm;

(5) utilizing acetone and deionized water to clean the Si-SnO complex obtained in step (4);

(6) Place the cleaned Si-SnO composite in a rapid annealing furnace, and anneal at 400° C. for 10 minutes under a nitrogen atmosphere;

(7) Spin-coat a layer of photoresist on the surface of the Si-SnO composite body after annealing to form a second mask;

(8) Utilize the second mask of ultraviolet lithography to form an annular window on the n-type Si surface, and at the same time form a circular window with a diameter of 140 μm on the SnO semiconductor layer, and the annular window surrounds the SnO semiconductor layer in its inner ring ;

(9) Utilize electron beam evaporation equipment to evaporate the metal evaporation material at room temperature, and deposit a Ni-Au double-layer electrode on the circular window and the circular window with a diameter of 140 μm obtained in step (8), and the deposition thickness is Ni: 50nm, Au: 50nm, the deposition sequence is, deposit Ni first, then deposit Au;

(10) The sample obtained in step (9) was washed with acetone and deionized water, and dried with dry _N2 to obtain p-SnO/n-Si heterojunction.

Example 6

(1) Cut the n-type single-polished silicon wafer with ρ<0.01Ωcm into sample silicon wafers of 1.5*1.5cm ² , and clean and dry them;

(2) Spin-coat a layer of photoresist on the <100> crystal plane of the sample silicon wafer to form a first mask;

(3) Form a circular window with a diameter of 160 μm by using the first mask of ultraviolet lithography;

(4) Utilize electron beam evaporation equipment to evaporate the tin dioxide evaporation material at room temperature, and deposit an amorphous SnO semiconductor layer on the circular window to obtain a Si-SnO composite; wherein, the deposition thickness of the SnO semiconductor layer is 50nm;

(5) utilizing acetone and deionized water to clean the Si-SnO complex obtained in step (4);

(6) Place the cleaned Si-SnO composite in a rapid annealing furnace, and anneal at 350° C. for 10 minutes under an argon atmosphere;

(7) Spin-coat a layer of photoresist on the surface of the Si-SnO composite body after annealing to form a second mask;

(8) Utilize the second mask of ultraviolet lithography to form an annular window on the n-type Si surface, and at the same time form a circular window with a diameter of 140 μm on the SnO semiconductor layer, and the annular window surrounds the SnO semiconductor layer in its inner ring ;

(9) Utilize electron beam evaporation equipment to evaporate the metal evaporation material at room temperature, and deposit a Ni-Au double-layer electrode on the circular window and the circular window with a diameter of 140 μm obtained in step (8), and the deposition thickness is Ni: 50nm, Au: 20nm, the deposition sequence is, deposit Ni first, then deposit Au;

(10) The sample obtained in step (9) was washed with acetone and deionized water, and dried with dry _N2 to obtain p-SnO/n-Si heterojunction.

Example 7

(1) Cut the n-type single-polished silicon wafer with ρ<0.01Ωcm into sample silicon wafers of 1.5*1.5cm ² , and clean and dry them;

(2) Spin-coat a layer of photoresist on the <100> crystal plane of the sample silicon wafer to form a first mask;

(3) Form a circular window with a diameter of 160 μm by using the first mask of ultraviolet lithography;

(4) Utilize electron beam evaporation equipment to evaporate the tin dioxide evaporation material at room temperature, and deposit an amorphous SnO semiconductor layer on the circular window to obtain a Si-SnO composite; wherein, the deposition thickness of the SnO semiconductor layer is 60nm;

(5) utilizing acetone and deionized water to clean the Si-SnO complex obtained in step (4);

(6) Place the cleaned Si-SnO composite in a rapid annealing furnace, and anneal at 350° C. for 10 minutes under an argon atmosphere;

(7) Spin-coat a layer of photoresist on the surface of the Si-SnO composite body after annealing to form a second mask;

(8) Utilize the second mask of ultraviolet lithography to form an annular window on the n-type Si surface, and at the same time form a circular window with a diameter of 140 μm on the SnO semiconductor layer, and the annular window surrounds the SnO semiconductor layer in its inner ring ;

(9) Utilize electron beam evaporation equipment to evaporate the metal evaporation material at room temperature, and deposit a Ni-Au double-layer electrode on the circular window and the circular window with a diameter of 140 μm obtained in step (8), and the deposition thickness is Ni: 50nm, Au: 20nm, the deposition sequence is, deposit Ni first, then deposit Au;

(10) The sample obtained in step (9) was washed with acetone and deionized water, and dried with dry _N2 to obtain p-SnO/n-Si heterojunction.

Example 8

(1) Cut the n-type single-polished silicon wafer with ρ<0.01Ωcm into sample silicon wafers of 1.5*1.5cm ² , and clean and dry them;

(2) Spin-coat a layer of photoresist on the <100> crystal plane of the sample silicon wafer to form a first mask;

(3) Form a circular window with a diameter of 160 μm by using the first mask of ultraviolet lithography;

(4) Utilize electron beam evaporation equipment to evaporate the tin dioxide evaporation material at room temperature, and deposit an amorphous SnO semiconductor layer on the circular window to obtain a Si-SnO composite body; wherein, the deposition thickness of the SnO semiconductor layer is 80nm;

(5) utilizing acetone and deionized water to clean the Si-SnO complex obtained in step (4);

(6) Place the cleaned Si-SnO composite in a rapid annealing furnace, and anneal at 350° C. for 15 minutes under an argon atmosphere;

(7) Spin-coat a layer of photoresist on the surface of the Si-SnO composite body after annealing to form a second mask;

(8) Utilize the second mask of ultraviolet lithography to form an annular window on the surface of n-type Si, which surrounds the SnO semiconductor layer in its inner ring; utilize electron beam evaporation equipment to evaporate the metal evaporation material at room temperature, and Deposit Ag-Au double-layer electrodes on the annular window and clean the remaining photoresist, wherein, the deposition thickness of the electrodes is: Ag: 50nm, Au: 20nm, and the deposition sequence is: first deposit Ag, then deposit Au;

(9) coating a layer of photoresist on the surface of the Si-SnO composite deposited with Ag-Au double-layer electrodes to form a third mask;

(10) Utilize the third mask of ultraviolet lithography to form a circular window with a diameter of 140 μm on the SnO semiconductor layer; use electron beam evaporation equipment to evaporate the metal evaporation material at room temperature, and deposit Ni on the circular window with a diameter of 140 μm -Au double-layer electrode, wherein, the deposition thickness of the electrode is: Ni: 50nm, Au: 20nm, and the deposition sequence is: Ni is deposited first, and then Au is deposited;

(11) Wash the sample obtained in step (10) with acetone and deionized water, and blow dry with dry _N2 to obtain p-SnO/n-Si heterojunction.

Example 9

(1) Cut the n-type single-polished silicon wafer with ρ<0.01Ωcm into sample silicon wafers of 1.5*1.5cm ² , and clean and dry them;

(2) Spin-coat a layer of photoresist on the <100> crystal plane of the sample silicon wafer to form a first mask;

(3) Form a circular window with a diameter of 160 μm by using the first mask of ultraviolet lithography;

(4) Utilize electron beam evaporation equipment to evaporate the tin dioxide evaporation material at room temperature, and deposit an amorphous SnO semiconductor layer on the circular window to obtain a Si-SnO composite body; wherein, the deposition thickness of the SnO semiconductor layer is 80nm;

(5) utilizing acetone and deionized water to clean the Si-SnO complex obtained in step (4);

(6) Place the cleaned Si-SnO composite in a rapid annealing furnace, and anneal at 300° C. for 20 minutes under an argon atmosphere;

(7) Spin-coat a layer of photoresist on the surface of the Si-SnO composite body after annealing to form a second mask;

(8) Utilize the second mask of ultraviolet lithography to form an annular window on the surface of n-type Si, which surrounds the SnO semiconductor layer in its inner ring; utilize electron beam evaporation equipment to evaporate the metal evaporation material at room temperature, and Deposit a Cu-Au double-layer electrode on the annular window and clean the remaining photoresist, wherein, the deposition thickness of the electrode is: Cu: 40nm, Au: 20nm, and the deposition sequence is: first deposit Cu, then deposit Au;

(9) coating a layer of photoresist on the surface of the Si-SnO composite deposited with Cu-Au double-layer electrodes to form a third mask;

(10) Utilize the third mask of ultraviolet lithography to form a circular window with a diameter of 140 μm on the SnO semiconductor layer; use electron beam evaporation equipment to evaporate the metal evaporation material at room temperature, and deposit Ag on the circular window with a diameter of 140 μm -Au double-layer electrode, wherein, the deposition thickness of the electrode is: Ag: 40nm, Au: 20nm, and the deposition sequence is: first deposit Ag, then deposit Au;

(11) Wash the sample obtained in step (10) with acetone and deionized water, and blow dry with dry _N2 to obtain p-SnO/n-Si heterojunction.

Figures 3 to 11 are respectively the characteristic curves obtained from the current and voltage tests of the p-SnO/n-Si heterojunctions prepared in Examples 1 to 9 using a semiconductor parameter instrument, and Table 1 shows the statistical results of the rectification ratio at ±2V . From Fig. 3 to Fig. 11 and Table 1, it can be seen that the p-SnO/n-Si heterojunction prepared by the present invention has obvious rectifying effect.

Table 1 The rectification ratio of p-SnO/n-Si heterojunction in Example 1-Example 9

The above-mentioned embodiments only express several implementation modes of the present invention, and the description thereof is relatively specific and detailed, but should not be construed as limiting the patent scope of the present invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

1. a pn knot, is characterized in that, comprise

N-shaped Si semiconductor layer, described N-shaped Si semiconductor layer is provided with the first electrode; And

Be positioned at the p-type SnO semiconductor layer of described N-shaped Si semiconductor layer central region, described p-type SnO semiconductor layer is provided with the second electrode.

2. pn knot according to claim 1, is characterized in that, the cross section of described p-type SnO semiconductor layer is circular;

The cross section of described first electrode is annular, and described p-type SnO semiconductor layer to be around in it in annulus by the first electrode of described annular;

The cross section of described second electrode is circular, and the cross-sectional area of described second electrode is less than the cross-sectional area of described p-type SnO semiconductor layer.

3. pn knot according to claim 1, it is characterized in that, the thickness of described p-type SnO semiconductor layer is 50nm ~ 80nm;

The thickness of described first electrode and described second electrode is 40nm ~ 100nm.

4. pn knot according to claim 1, it is characterized in that, described first electrode and described second electrode are Ni-Au two-layer electrode, Cu-Au two-layer electrode or Ag-Au two-layer electrode.

5. a preparation method for pn knot, is characterized in that, comprise the following steps:

S100: deposit one deck p-type SnO semiconductor on Si semiconductor, obtain Si-SnO complex;

S200: deposition of first electrode on the N-shaped Si semiconductor in described Si-SnO complex, the SnO semiconductor in described Si-SnO complex deposits the second electrode, obtains p-SnO/n-Si heterojunction.

6. the preparation method of pn knot according to claim 5, it is characterized in that, described S100 comprises the following steps:

At N-shaped Si semiconductor surface coating photoresist, form the first mask;

First mask described in ultraviolet photolithographic, described N-shaped Si semiconductor forms first window;

Utilize electron-beam vapor deposition method at surface deposition one deck p-type SnO semiconductor of described first window, obtain Si-SnO complex.

7. the preparation method of pn knot according to claim 6, it is characterized in that, described S200 comprises the following steps:

At described Si-SnO complex surfaces coating photoresist, form the second mask;

Second mask described in ultraviolet photolithographic, the N-shaped Si semiconductor in described Si-SnO complex forms Second Window, and the SnO semiconductor simultaneously in described Si-SnO complex forms the 3rd window;

Utilize electron-beam vapor deposition method deposition of first electrode on described Second Window, on described 3rd window, deposit the second electrode simultaneously;

Remove the remaining photoresist of Si-SnO complex surfaces after described depositing electrode, obtain p-SnO/n-Si heterojunction.

8. the preparation method of the pn knot according to claim 6 or 7, is characterized in that, before S200, further comprising the steps of:

Remove the remaining photoresist of described Si-SnO complex surfaces and heat-treat described Si-SnO complex, described heat treated condition is: under protective atmosphere, is incubated 10min ~ 20min at 300 DEG C ~ 400 DEG C.

9. the preparation method of pn knot according to claim 7, it is characterized in that, described first window is circular window;

Described Second Window is annular window, and described SnO semiconductor layer to be around in it in annulus by described annular window;

Described 3rd window is circular window, and the area of described circular window is less than the area of described first window.

10. the preparation method of pn knot according to claim 5, it is characterized in that, the thickness of the p-type SnO semiconductor of described deposition is 50nm ~ 80nm;

First electrode of described deposition and the thickness of described second electrode are 40nm ~ 100nm.