CN104576595B - Integrated circuit and operation method thereof - Google Patents

Abstract

The invention discloses an integrated circuit and an operation method thereof, wherein the integrated circuit comprises a laminated structure and a conductive structure; the laminated structure comprises a conductive stripe; the conductive structure is positioned above the laminated structure and is electrically connected to the conductive stripes; the conductive structures and the conductive stripes have different gap distances between corresponding points of different groups according to the base axis.

Description

Integrated circuit and method of operation thereof

technical field

The present invention relates to an integrated circuit and its operating method, and more particularly to an integrated circuit with a conductive structure and its operating method.

Background technique

As the critical dimensions of devices in integrated circuits shrink to the limits of conventional memory cell technology, designers turn to multi-overlapping memory cell planar technology to achieve higher storage density and lower cost per bit. For example, thin film transistor technology has been used in charge trapping memory. In addition, rendezvous point array technology has also been applied in antifuse memory.

In a three-dimensional array, structural electrical characteristics in different levels (1evel) can lead to different dynamics of programming, erasing, and charge storage, including changes in the threshold voltages corresponding to storage states of these memory cells at different levels. Therefore, in order to achieve an optimized read/write quality of memory cells in each layer, the programming and erasing processes must to some extent adapt to the variation between different layers of the target memory cell. These variations can also lead to memory cell endurance issues and other complications.

In a three-dimensional array, the access lines, such as master bit lines, are arranged to access the different levels of the array such that their characteristics, such as capacitance or inductance, vary with the circuit to which they are coupled The variation between layers varies accordingly. For example, the main bit line is usually extended to the sensing circuit used to read and write the memory cell. The vertical connectors between different layers and other different characteristics will cause the capacitance value to vary between the main bit lines. Differences in these capacitance values affect the main bit line voltage during read, program, or erase operations, and affect specification requirements, such as larger read intervals between programmed and erased states.

It is therefore desirable to provide an integrated circuit that reduces the complexity caused by differences between different layers.

Contents of the invention

The present invention relates to an integrated circuit and its operating method, with average inductive capacitance.

According to an embodiment, an integrated circuit is provided, including a laminated structure and a conductive structure; the laminated structure includes a conductive stripe; the conductive structure is located above the laminated structure and is electrically connected to the conductive stripe; the conductive structure and the conductive stripe There are different gap distances between corresponding points of different groups according to the base axis.

According to another embodiment, a method for operating an integrated circuit is provided. The integrated circuit includes a three-dimensional memory stack and a conductive structure; the three-dimensional memory stack includes a dummy part and a memory part adjacent to each other, the dummy part and the The memory parts all include a laminated structure, a dielectric layer, a first conductive layer and a second conductive layer; the laminated structure includes a conductive stripe; the first conductive layer is electrically insulated from the conductive stripe by the dielectric layer; The opposite ends of the stripes are respectively electrically connected to the second conductive layer and the conductive structure; the first conductive layer is disposed between the opposite ends of the conductive stripes; the operation method includes the following steps: providing a first voltage to the conductive portion of the dummy portion Structure; providing a second voltage to the second conductive layer of the dummy part; the first voltage is equal to the second voltage.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the preferred embodiments are specifically cited below, together with the attached drawings, and are described in detail as follows:

Description of drawings

FIG. 1 is a schematic diagram of an integrated circuit according to an embodiment.

FIG. 2 is a schematic diagram of an integrated circuit according to an embodiment.

3 is a top view of an integrated circuit according to an embodiment.

4 is a top view of an integrated circuit according to an embodiment.

FIG. 5 is a schematic diagram of an integrated circuit according to a comparative example.

【Symbol Description]

102: Laminated structure

104: Dielectric layer

106, 106A, 106B, 106C, 106D: first conductive layer

108: second conductive layer

110, 210: conductive structure

112: Substrate

114: Conductive stripes

116: Dielectric stripes

118: guide elevator

119: Conductive plug

120, 220: conductive thread

122: Conductive plate

124: virtual part

126: memory part

D1, D2, D3, D4: Distance

detailed description

1 is a schematic diagram of an integrated circuit according to one embodiment. The integrated circuit includes a three-dimensional (3D) memory stack including a stack structure 102, a dielectric layer 104, first conductive layers 106A, 106B, 106C, 106D, and a second conductive layer. The conductive layer 108 ; the integrated circuit also includes a conductive structure 110 .

Referring to FIG. 1 , stacked structures 102 in different rows (for example extending in the Z direction) are separately disposed on a substrate 112 . The stacked structures 102 each include a plurality of cross-stacked and straight conductive stripes 114 and dielectric stripes 116 . The dielectric stripes 116 are similar to the conductive stripes 114 and are straight and continuously extending structures. In order to clearly show the structure of the integrated circuit of the embodiment, FIG. 1 does not show the dielectric stripes 116 interposed between the first conductive layer 106A, 106B, 106C, 106D and the portion between the second conductive layer 108 .

The opposite ends of the conductive stripes 114 are electrically connected to the conductive structure 110 and the second conductive layer 108 respectively. The first conductive layers 106A, 106B, 106C, 106D between opposite ends of the conductive stripes 114 are electrically insulated from the conductive stripes 114 by the dielectric layer 104 . The first conductive layers 106A, 106B, 106C, 106D and the second conductive layer 108 of different pages whose extension directions (eg X direction) are parallel to each other can be separated from each other by a dielectric structure (not shown).

The conductive structure 110 is located above the laminated structure 102 and is electrically connected to the conductive stripe 114 through a conductive elevator 118 and a conductive plug 119 . In this example, the conductive structure 110 includes conductive lines 120 separated from each other, which are electrically connected to the conductive stripes 114 of the same level in different rows of the stacked structure 102 . The conductive stripes 114 have a zigzag shape or a stepped shape as shown in FIG. 1 , or other suitable shapes.

In one embodiment, the conductive stripes 114 of the stacked structure 102 are used as bit lines (BL). The first conductive layer 106A disposed on the sidewall of the stack structure 102 and adjacent to the conductive elevator 118 is used as a series select line (SSL), wherein the adjacent conductive stripes can be controlled by applying a voltage to the first conductive layer 106A. 114 is a selected state (or an on state), or an unselected (unselected) state (or an off state). The second conductive layer 108 away from the conductive elevator 118 is used as a common source line (CSL), electrically connected to the conductive stripes 114 of the stacked structures 102 in different rows. The first conductive layer 106D adjacent to the second conductive layer 108 is used as a ground select line (GSL). The first conductive layers 106B, 106C between the first conductive layer 106A and the first conductive layer 106D are used as word lines (WL).

The number of pages of the first conductive layers 106B, 106C (WL), the number of rows of the laminated structure 102, the number of levels of the conductive stripes 114, the number of conductive lines 120, etc. in the embodiment are not limited to the numbers shown in FIG. The situations are respectively designed as a greater or lesser number. In embodiments, the conductive material may include metal, polysilicon, metal silicide, or other suitable materials. The dielectric material may include oxide or silicide, such as silicon oxide, silicon nitride, or silicon oxynitride, or other suitable materials.

FIG. 2 is a schematic diagram of an integrated circuit according to an embodiment, and its differences from FIG. 1 are explained as follows. The conductive structure 110 includes a conductive plate 122 whose long axis extends in a direction not parallel to the extending direction of each stacked structure 102 (or conductive stripe 114 ). The conductive plate 122 is electrically connected to the conductive stripes 114 at the same level of different stacked structures 102 , and is also electrically connected to the conductive stripes 114 at different levels of each stacked structure 102 .

Please refer to FIG. 3 , which is a top view of an integrated circuit according to an embodiment, wherein, for simplicity, only the conductive stripes 114 , the first conductive layer 106 and the conductive structure 110 are shown. The conductive structure 110 includes a conductive plate 122 and a conductive line 120 that are separated from each other, and are disposed at the same level (eg, a third-level metal layer (M3)). The extending direction (eg, X direction) of the first conductive layer 106 and the second conductive layer 108 ( FIG. 1 ) is intersected with the extending direction (eg, Z direction) of the conductive stripes 114 of the stacked structure 102 ( FIG. 1 ).

The three-dimensional memory stack includes adjacent dummy portions 124 and memory portions 126 . In one embodiment, for example, the dummy part 124 is disposed between the memory parts 126 . The conductive stripes 114 of the memory portion 126 and the adjacent dummy portion 124 are electrically connected to the conductive lines 120 of the conductive structure 110 , and the three-dimensional memory stack of this portion is similar to the structure shown in FIG. 1 . The conductive stripes 114 of the dummy portion 124 away from the memory portion 126 are electrically connected to the conductive plate 122 of the conductive structure 110 , and the three-dimensional memory stack at this portion is similar to the structure shown in FIG. 2 . In one embodiment, the dummy portion 124 and the memory portion 126 share a single second conductive layer 108 (or a common source line) ( FIGS. 1 and 2 ).

In an embodiment, the extending directions of the conductive structure 110 and the conductive stripe 114 are not parallel to each other, or the integrated circuit is configured with a dummy portion 124, thereby compensating for different bit structures (such as the upper surface area of the conductive lift 118 in FIG. 1 ) caused by the difference in capacitance, and makes the integrated circuit have a more average inductive capacitance. For example, from the top view shown in FIG. 3 , the conductive wire 120 is gradually away from the conductive strip 114 electrically connected to it from the end portion to the middle portion. The long edge of the conductive plate 122 is the edge row of conductive stripes 114 gradually away from its electrical connection from the end portion to the middle portion. Alternatively, the conductive structures 110 and the conductive stripes 114 have different gap distances between different sets of corresponding points according to the base axis. For example, the conductive plate 122 and the conductive stripes 114 have different gap distances (eg, the distance D1 is greater than the distance D2) between different groups of corresponding points according to the base axis (eg, the Z axis). Alternatively, the conductive lines 120 and the conductive stripes 114 have different gap distances (eg, the distance D3 is greater than the distance D4 ) between corresponding points of different groups according to the base axis (eg, the Z axis).

In one embodiment, the method of operating the integrated circuit includes programming, reading, and erasing the memory portion 126 (FIG. 3) of the three-dimensional memory stack. In the process of operating the memory portion 126, a first voltage is provided to the conductive structure 110 of the dummy portion 124, and a second voltage is provided to the second conductive layer 108 of the dummy portion 124 ( FIG. 1 ), wherein the first voltage is equal to second voltage.

Please refer to Figure 1 to Figure 3 at the same time. For example, the method for programming the memory portion 126 includes the following steps: providing a voltage (such as 0V) to the conductive line 120; providing a voltage to the first conductive layer 106A (connected in series with the selection line) to select (or turn on) the conductive stripes 114: Provide a pass voltage (Vpass) or programming voltage (Vpgm) to the first conductive layer 106B, 106C (word line) of different pages; provide a voltage to the first conductive layer 106D (ground selection line) to turn off the conductive stripe 114: Provide a voltage (such as a power supply voltage Vcc) to the second conductive layer 108 (common source line).

While performing the programming step on the memory portion 126, the dummy portion 124 is not programmed, and the method is described as follows: provide the same (first) voltage (such as a power supply voltage Vcc) to the first conductive layer 106A and the first conductive layer 106A of the dummy portion 124. Conductive structure 110 (conductive wire 120 or conductive plate 122 ). In one embodiment, for example, the first conductive layer 106A of the dummy portion 124 and the portion of the conductive stripe 114 adjacent to the conductive structure 110 are short-circuited through a conductive element (such as a metal layer, not shown), so it can be (from the conductive A common (first) voltage of the structure 110 is provided to the first conductive layer 106A and the conductive stripes 114 simultaneously. The first conductive layers 106B, 106C (word lines) of the dummy portion 124 are shared with the memory portion 126 , and thus provide the same voltage as the memory portion 126 . The same (second) voltage (eg power supply voltage Vcc) is provided to the first conductive layer 106D and the second conductive layer 108 of the dummy portion 124 . In one embodiment, for example, the first conductive layer 106D and the second conductive layer 108 of the dummy portion 124 are short-circuited through a conductive element (such as a metal layer, not shown), so a shared (second) voltage can be achieved. It is provided to the first conductive layer 106D and the second conductive layer 108 at the same time.

The method for reading the memory portion 126 includes the following steps: providing a voltage (such as 1V) to the conductive line 120; providing a voltage (such as a power supply voltage Vcc) to the first conductive layer 106A (series selection line) to turn on the conductive stripe 114 ; Provide a pass voltage (Vpass) to the first conductive layer 106B, 106C (word line); provide a voltage (such as a power supply voltage Vcc) to the first conductive layer 106D (ground selection line) to turn on the conductive strip 114; provide a Voltage (eg, ground) to the second conductive layer 108 (common source line).

While performing the reading step on the memory portion 126, the dummy portion 124 is not sensed. The method is described as follows: provide the same (first) voltage (such as 0V) to the first conductive layer 106A of the dummy portion 124 and The conductive structure 110 (the conductive line 120 or the conductive plate 122 ); providing the same (second) voltage (eg, 0V, or ground) to the first conductive layer 106D and the second conductive layer 108 of the dummy portion 124 .

The method for erasing the memory portion 126 includes the following steps: providing a voltage (such as 14V) to the conductive line 120; providing a voltage to the first conductive layer 106A (connected in series with the selection line) to turn on the conductive stripe 114; providing a voltage (such as 0V) to the first conductive layer 106B, 106C (word line); provide a voltage to the first conductive layer 106D (ground selection line) to turn on the conductive stripe 114; provide a voltage (such as 14V) to the second conductive layer 108 ( common source line).

While performing the erasing step on the memory portion 126, the dummy portion 124 is erased, and the method is described as follows: provide the same erasing bias (for example, 14V) to the first conductive portion of the dummy portion 124 Layer 106A and conductive structure 110 (conductive line 120 or conductive plate 122 ); provide the same (second) voltage (eg 14V, or ground) to first conductive layer 106D and second conductive layer 108 of dummy portion 124 .

FIG. 4 is a top view of an integrated circuit according to an embodiment, and the differences in FIG. 3 are explained as follows: the extending direction of the first conductive layer 106 (for example, the X direction) and the extending direction of the conductive lines 120 (for example, the Z direction) are staggered. The conductive stripes 114 of the stacked structure 102 have a zigzag or stepped shape, and the extending direction is not parallel to the conductive lines 120 .

FIG. 5 shows an integrated circuit of a comparative example, which differs from the integrated circuit of the embodiment in that the conductive structure 210 is a conductive line 220 extending parallel to the conductive stripe 114 . Compared with the comparative example, the embodiment of the present invention (the extending directions of the conductive structure 110 and the conductive stripes 114 are not parallel to each other) has a more average inductive capacitance.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (9)

1. a kind of integrated circuit, including a three-dimensional storage lamination, the three-dimensional storage lamination are deposited including a dummy part with one Reservoir portion, the dummy part respectively includes with the memory portion：

One laminated construction, including multiple conductive stripes；And

One conductive structure, above the laminated construction, and is electrically connected to the plurality of conductive stripe, wherein the conductive structure bag Multiple conductor wires and a conductive plate are included, the plurality of conductive stripe system of the laminated construction of the memory portion is electrically connected to this A part for multiple conductor wires, the plurality of conductive stripe system of the laminated construction of the dummy part is electrically connected to the conductive plate Or another part of the plurality of conductor wire, the conductive structure and the plurality of conductive stripe are between different groups of corresponding points according to base Axle has different clearance distances, and the conductive structure and the bearing of trend of the plurality of conductive stripe are not parallel to each other.

2. integrated circuit according to claim 1, the wherein conductive plate are configured between these conductor wires, wherein the conduction Plate and these conductor wires are separated from each other and all configure in same stratum.

3. integrated circuit according to claim 1, the wherein conductive plate and the conductive stripe different groups corresponding points it Between there are different clearance distances according to standard shaft.

4. multiple conductive stripes in integrated circuit according to claim 1, the wherein laminated construction are separated from each other, this is led Conductive plate in electric structure, is electrically connected to these conductive stripes of the identical stratum of each laminated construction, and is electrically connected with simultaneously To these conductive stripes of the different estate of each laminated construction.

5. integrated circuit according to claim 1, the wherein conductor wire and the conductive stripe different groups corresponding points it Between there are different clearance distances according to standard shaft.

6. multiple conductive stripes in integrated circuit according to claim 1, the wherein laminated construction are separated from each other, this is led Conductor wire in electric structure, is electrically connected to these conductive stripes of the identical stratum of each laminated construction.

7. integrated circuit according to claim 1, wherein the three-dimensional storage lamination also include：

One dielectric layer；

One ground connection selection line (GSL)；

One common source line (common source line, CSL)；And

Connect selection line for a string, configure on the side wall of the laminated construction, and by the dielectric layer be divided in the laminated construction should Conductive stripe,

Wherein the ground connection selection line is electrically insulated from the conductive stripe of the laminated construction by the dielectric layer, and the wherein ground connection is selected Select line and the conductive stripe is interlaced with each other, the ground connection selection line and the mutual short circuit of the common source line, the concatenation selection line is with being somebody's turn to do The mutual short circuit of conductive stripe.

8. a kind of operating method of integrated circuit, the wherein integrated circuit include：

One three-dimensional storage lamination, including a neighbouring dummy part and a memory portion, the dummy part and the memory Part includes：

One laminated construction, including a conductive stripe；

One dielectric layer；

One first conductive layer, the conductive stripe is electrically insulated from by the dielectric layer；And

One second conductive layer；And

The opposing end portions of one conductive structure, the wherein conductive stripe are respectively and electrically connected to second conductive layer and tied with the conduction Structure, first conductive layer is configured between these opposing end portions of the conductive stripe；

The operating method includes：

A first voltage is provided to the conductive structure of the dummy part；And

A second voltage is provided to second conductive layer of the dummy part, the wherein first voltage is equal to the second voltage.

9. the operating method of integrated circuit according to claim 8, further includes programming, reads and wipes the three-dimensional storage Memory portion of lamination, wherein during the programming, the reading and the erasing, the first voltage is equal to second electricity Pressure.