CN104576375B - LDMOS and its manufacture method - Google Patents
LDMOS and its manufacture method Download PDFInfo
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- CN104576375B CN104576375B CN201310473815.7A CN201310473815A CN104576375B CN 104576375 B CN104576375 B CN 104576375B CN 201310473815 A CN201310473815 A CN 201310473815A CN 104576375 B CN104576375 B CN 104576375B
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- 238000000034 method Methods 0.000 title claims abstract description 34
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- 230000015572 biosynthetic process Effects 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 150000002500 ions Chemical class 0.000 description 106
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229920005591 polysilicon Polymers 0.000 description 14
- 229910052785 arsenic Inorganic materials 0.000 description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
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- 235000007164 Oryza sativa Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention provides a kind of LDMOS and its manufacture method, the LDMOS is LDNMOS, and this method comprises the following steps：After STI, p-type trap, N drift regions, grid structure and source electrode and drain electrode are sequentially formed in substrate, this method also includes：After formation of the gate structure, the optical resistance glue layer of patterning is formed in substrate surface, the opening of the optical resistance glue layer of the patterning manifests grid structure, source electrode and drain electrode；Using the optical resistance glue layer of the patterning as mask, the ion implanting that desired depth is carried out to symmetrically arranged two N drift regions forms P transoid ion floating areas, and the P transoids ion floating area is located in N drift regions, has predetermined space with STI.Present invention also offers a kind of LDMOS and its manufacture method, the LDMOS is LDPMOS.Breakdown voltage can be improved using the present invention.
Description
Technical field
The present invention relates to semiconductor devices and its manufacturing field, more particularly to a kind of LDMOS (lateral diffused metal oxides
Semiconductor transistor) and its manufacture method.
Background technology
LDMOS transistor（Laterally Diffused Metal Oxide
Semiconductor, LDMOS）Power integrated circuit is mainly used in, such as is amplified towards the radio-frequency power of mobile telephone base station
Device, high frequency, superfrequency and hyperfrequency broadcast transmitter and microwave radar and navigation system etc. can also be applied to.LDMOS skills
Art is that base station of new generation brings higher power PAR, more high-gain and the linearity, while is multimedia service band
Carry out higher data transmission rate.
Existing horizontal proliferation N-type metal oxide semiconductor transistor（Laterally Diffused N type Metal
Oxide semiconductor, LDNMOS）Structure as shown in figure 1, LDNMOS has substrate 1, on the surface of substrate 1 successively shape
Into gate oxide 2 and polysilicon gate 3, gate oxide 2 and polysilicon gate 3 are referred to as grid structure.P-type is formed in substrate 1
Trap 8, p-type trap 8 is interior to be had in the symmetrically arranged N- drift regions 4 in grid structure both sides（N-Drift1 and N-Drift2）, p-type trap 8
Shallow trench isolation is provided between N- drift regions 4（Shallow Trench Isolation, STI）Set in 5, N- drift regions 4
It is equipped with source electrode 6 and drain electrode 7.Wherein, p-type trap 8 can be formed by the ion implanting of any p-type element of such as boron；N- drift regions 4
It is to be formed by the ion implanting of similar arsenic element；Source electrode 6 is with drain electrode 7 and by the ion implanting of similar arsenic element come shape
Into simply both ion implantation concentrations are different.
For LDMOS, it is used under the operating voltage higher than 50V, breakdown voltage（BV, Breakdown Voltage）It is
Weigh one of important indicator of device performance.A kind of method of existing raising LDNMOS breakdown voltages is：Expand N- drift regions
Area, it so may result in number of devices in unit area and reduce.Therefore, how to improve LDMOS breakdown voltage be at present urgently
The problem of to be solved.
The content of the invention
The invention provides a kind of LDMOS and its manufacture method, present invention solves the technical problem that being：How breakdown is improved
Voltage.
In order to solve the above technical problems, what technical scheme was specifically realized in：
It is described the invention provides a kind of LDMOS transistor LDMOS manufacture method
LDMOS is LDNMOS, and this method comprises the following steps：
A, formed in substrate in LDNMOS areas and be used for the STI of isolated p-well and N- drift regions；
B, carry out ion implanting in LDNMOS areas and form p-type trap；
C, ion implanting formation is located at the symmetrically arranged N- drift regions in grid structure both sides in the p-type trap；
D, the substrate surface between N- drift regions forms grid structure；
E, N+ is carried out in N- drift regions to adulterate to form source electrode and drain electrode；
This method also includes：In step D-shaped into after grid structure, the optical resistance glue layer of patterning is formed in substrate surface,
The opening of the optical resistance glue layer of the patterning manifests grid structure, source electrode and drain electrode；Using the optical resistance glue layer of the patterning as
Mask, the ion implanting that desired depth is carried out to symmetrically arranged two N- drift regions form P transoid ion floating areas, institute
State P transoid ions floating area to be located in N- drift regions, there is predetermined space with STI.
It is described in step D-shaped into after grid structure, forming P transoid ion floating areas, including：Between step D and E,
Or after step E, form P transoid ion floating areas.
The P transoids ion floating area is integral part, or is multiple parts kept apart.
The ion implantation dosage of the P transoids ion floating area is 1013-1015Atom per square centimeter.
Present invention also offers a kind of LDMOS transistor LDMOS, the LDMOS is
LDNMOS, include the grid structure of substrate surface, and in p-type trap, and in the symmetrically arranged N- drifts in grid structure both sides
Area is moved, STI is provided between the p-type trap and N- drift regions, source electrode and drain electrode are provided with the N- drift regions；Described right
Claim set two N- drift regions in set with desired depth P transoid ion floating areas, the P transoids ion floating area with
STI has predetermined space.
It is described present invention also offers a kind of LDMOS transistor LDMOS manufacture method
LDMOS is LDPMOS, and this method comprises the following steps：
A, formed in substrate and be used for isolating n-type trap and the STI of P- drift regions in LDPMOS areas；
B, carry out ion implanting in LDPMOS areas and form N-type trap；
C, ion implanting formation is located at the symmetrically arranged P- drift regions in grid structure both sides in the N-type trap；
D, the substrate surface between P- drift regions forms grid structure；
E, P+ is carried out in P- drift regions to adulterate to form source electrode and drain electrode；
This method also includes：In step D-shaped into after grid structure, the optical resistance glue layer of patterning is formed in substrate surface,
The opening of the optical resistance glue layer of the patterning manifests grid structure, source electrode and drain electrode；Using the optical resistance glue layer of the patterning as
Mask, the ion implanting that desired depth is carried out to symmetrically arranged two P- drift regions form N transoid ion floating areas, institute
State N transoid ions floating area to be located in P- drift regions, there is predetermined space with STI.
It is described in step D-shaped into after grid structure, forming N transoid ion floating areas, including：Between step D and E,
Or after step E, form N transoid ion floating areas.
The N transoids ion floating area is integral part, or is multiple parts kept apart.
The ion implantation dosage of the N transoids ion floating area is 1013-1015Atom per square centimeter.
Present invention also offers a kind of LDMOS transistor LDMOS, the LDMOS is
LDPMOS, include the grid structure of substrate surface, and in N-type trap, and in the symmetrically arranged P- drifts in grid structure both sides
Area is moved, STI is provided between the N-type trap and P- drift regions, source electrode and drain electrode are provided with the P- drift regions；Described right
N transoid ion floating areas are provided with two P- drift regions for claiming to set, the N transoids ion floating area has predetermined with STI
Interval.
As seen from the above technical solutions, LDNMOS of the invention, made a reservation in symmetrically arranged two N- drift regions
The intersection of the ion implanting formation P transoid ion floating areas of depth, P transoid ion floating areas and N- drift regions, which can produce, to be exhausted
Layer, there is no electrically conductive ion in depletion layer, form space-charge region, so as to reach the purpose for improving breakdown voltage.Similarly, this hair
Bright LDPMOS, is provided with N transoid ion floating areas in symmetrically arranged two P- drift regions, N transoid ion floating areas with
The intersection of P- drift regions can produce depletion layer, not have electrically conductive ion in depletion layer, form space-charge region, carried so as to reach
The purpose of high-breakdown-voltage.Compared with prior art, in the case where drift region area need not be expanded, it is possible to effectively improve
Breakdown voltage.
Brief description of the drawings
Fig. 1 is prior art LDNMOS structural representations.
Fig. 2 is the schematic flow sheet of one embodiment of the present invention LDNMOS preparation methods.
Fig. 2 a to Fig. 2 f are the diagrammatic cross-section of LDNMOS manufacturing process of the present invention.
Fig. 3 is LDNMOS diagrammatic cross-sections of the embodiment of the present invention.
Fig. 4 is the schematic flow sheet of another preferred embodiment LDPMOS preparation methods of the present invention.
Fig. 5 is LDPMOS diagrammatic cross-sections of the embodiment of the present invention.
Embodiment
For the purpose of the present invention, technical scheme and advantage is more clearly understood, develop simultaneously embodiment referring to the drawings,
The present invention is described in more detail.
The present invention is described in detail using schematic diagram, when the embodiment of the present invention is described in detail, for convenience of description, is represented
The schematic diagram of structure can disobey general proportion and make partial enlargement, should not be in this, as limitation of the invention, in addition, in reality
In making, the three-dimensional space of length, width and depth should be included.
The method of the present invention is applied to LDNMOS and LDPMOS.
The schematic flow sheets of one embodiment of the present invention LDNMOS preparation methods as shown in Fig. 2 it comprises the following steps,
It is described in detail with reference to Fig. 2 a to Fig. 2 f.
Step 21, Fig. 2 a are referred to, formed on the base 1 in LDNMOS areas for isolated p-well 8 and N- drift regions 4
STI5；
Wherein, substrate 1 is generally monocrystalline silicon.
Step 22, Fig. 2 b are referred to, carrying out ion implanting in LDNMOS areas forms p-type trap 8；
P-type trap 8 can be formed by the ion implanting of any p-type element of such as boron, ion concentration 1013-1014Atom
It is every square centimeter, median dose, medium energy vertical wafer ion implanting.
Step 23, Fig. 2 c are referred to, ion implanting is formed and is symmetrical arranged positioned at grid structure both sides in the p-type trap 8
N- drift regions 4（N-Drift1 and N-Drift2）, ion concentration 1012-1013Atom per square centimeter, median dose are high
Energy, vertical wafer ion implanting；
Step 24, Fig. 2 d are referred to, the surface of substrate 1 between N- drift regions 4 forms grid structure；
Wherein, grid structure includes gate oxide 2 and polysilicon gate 3.Specifically, first, give birth to successively on the base 1
Long gate oxide and deposit polycrystalline silicon layer, then in the surface coating photoresist layer of polysilicon layer（Do not shown in figure）, expose aobvious
Shadow patterns photoresist layer, defines the position of grid, using photoetching offset plate figure as mask, is sequentially etched polysilicon layer and gate oxidation
Layer, form gate oxide 2 and polysilicon gate 3.
Step 25, Fig. 2 e are referred to, N+ is carried out in N- drift regions 4 and adulterates to form source electrode 6 and drain electrode 7；
Step 26, Fig. 2 f are referred to, the optical resistance glue layer 10 of patterning, the photoresistance of the patterning are formed on the surface of substrate 1
The opening of glue-line manifests grid structure, source electrode and drain electrode；Using the optical resistance glue layer of the patterning as mask, symmetrically set to described
The ion implanting that the two N- drift regions 4 put carry out desired depth forms P transoid ions floating area 9, the P transoids ion floating
Area 9 is located in N- drift regions 4, has predetermined space with STI5.
Wherein, source electrode 6 and the depth of drain electrode 7 are necessarily more shallow than STI5, so ion implanting forms P transoid ions floating area 9
When, control is injected into STI5 lower section.The ion implantation dosage of P transoid ions of embodiment of the present invention floating area 9 is
1013-1015Atom per square centimeter.In addition, P transoids ion floating area 9 is an integral part in figure.Certainly, P transoids ion
Floating area 9 can also be multiple parts kept apart, and forming method can be：Under the blocking of the optical resistance glue layer of raster fashion,
The P transoid ions floating area 9 that ion implanting is formed is exactly to be made up of multiple parts kept apart.P transoid ions floating area 9 is
Multiple parts kept apart, the advantages of being integral part compared to P transoid ions floating area 9, are, add P transoid ions
Contact area between floating area 9 and N- drift regions 4, so as to add depletion layer area, and then further increase breakdown potential
Pressure.
So far, LDNMOS of the embodiment of the present invention is formed and terminated.
Embodiments of the present invention P transoid ions floating area 9 is formed after source-drain electrode is formed.Need what is illustrated
It is, as long as the formation of P transoids ion floating area 9 of the present invention is after grid structure formation.That is, P transoid ions
Floating area 9 can also be formed between step 24 and step 25.The opening that the optical resistance glue layer of patterning is can be seen that from Fig. 2 f shows
Expose grid structure, source electrode and drain electrode, opening size is bigger.Wafer is divided into due to generally multiple with repetitive structure
Chip, multiple LDMOS are regularly arranged on each chip, so, multiple LDMOS are formed simultaneously, therefore can shape on each LDMOS
Into the opening of the optical resistance glue layer of patterning, the grating pattern interval that the optical resistance glue layer so patterned is formed can reach 2 microns,
Such large-sized grating spacings cause alignment precision so high, and the requirement to board, can be efficiently also than relatively low
Complete LDMOS making.
Fig. 3 is the LDNMOS diagrammatic cross-sections formed according to the above method.
LDNMOS has substrate 1, and gate oxide 2 and polysilicon gate 3, the He of gate oxide 2 are sequentially formed on the surface of substrate 1
Polysilicon gate 3 is referred to as grid structure.P-type trap 8 is formed in substrate 1, has in p-type trap 8 and is symmetrically set in grid structure both sides
The N- drift regions 4 put（N-Drift1 and N-Drift2）, shallow trench isolation STI 5 is provided between p-type trap 8 and N- drift regions 4,
Source electrode 6 and drain electrode 7 are provided with N- drift regions 4.In symmetrically arranged two N- drift regions 4（N-Drift1 and N-
Drift2）Middle to set the P transoid ions floating area 9 with desired depth, the P transoids ion floating area 9 has pre- with STI5
Fixed interval.
Wherein, p-type trap 8 can be formed by the ion implanting of any p-type element of such as boron；N- drift regions 4 are to pass through class
Formed like the ion implanting of arsenic element；Source electrode 6 is formed with drain electrode 7 and by the ion implanting of similar arsenic element, simply
Both ion implantation concentrations are different.The ion implanting for any p-type element that P transoid ions floating area 9 passes through such as boron is formed.
Because P transoid ions floating area 9 is located in N- drift regions 4, there is predetermined space with STI5, so P transoid ions
Floating area 9 and the intersection of N- drift regions 4 can produce depletion layer, not have electrically conductive ion in depletion layer, form space-charge region,
So as to cause punch through voltage rise.
Equally, the method for improving breakdown voltage is equally applicable to LDPMOS.
The schematic flow sheet of another preferred embodiment LDPMOS preparation methods of the present invention is as shown in figure 4, it includes following step
Suddenly：
Step 41, formed in substrate 1 ' in LDPMOS areas for isolating n-type trap 8 ' and the STI5 ' of P- drift regions 4 '；
Wherein, substrate 1 ' is generally monocrystalline silicon.
Step 42, ion implanting formation N-type trap 8 ' is carried out in LDPMOS areas；
N-type trap 8 ' can be formed by the ion implanting of similar arsenic element, ion concentration 1013-1014Atom per square li
Rice, median dose, medium energy vertical wafer ion implanting.
Step 43, ion implanting forms and is located at the symmetrically arranged P- drift regions in grid structure both sides in the N-type trap 8 '
4 ', ion concentration 1012-1013Atom per square centimeter, median dose, high energy, vertical wafer ion implanting；
Step 44, the surface of substrate 1 ' between P- drift regions 4 ' form grid structure；
Wherein, grid structure includes gate oxide 2 ' and polysilicon gate 3 '.Specifically, first, in substrate 1 ' according to
Secondary growth gate oxide and deposit polycrystalline silicon layer, then in the surface coating photoresist layer of polysilicon layer（Do not shown in figure）, expose
Photodevelopment patterns photoresist layer, defines the position of grid, using photoetching offset plate figure as mask, is sequentially etched polysilicon layer and grid
Oxide layer, form gate oxide 2 ' and polysilicon gate 3 '.
Step 45, progress P+ adulterates to form source electrode 6 ' and drain electrode 7 ' in P- drift regions 4 '；
Step 46, the optical resistance glue layer patterned is formed on the surface of substrate 1, the opening of the optical resistance glue layer of the patterning appears
Go out grid structure, source electrode and drain electrode；Using the optical resistance glue layer of the patterning as mask, symmetrically arranged two N- are drifted about
The ion implanting that area 4 ' carries out desired depth forms N transoid ions floating area 9 ', and the N transoids ion floating area 9 ' is located at N- drifts
Move in area 4 ', there is predetermined space with STI5 '.
Wherein, source electrode 6 ' and the depth of drain electrode 7 ' are necessarily more shallow than STI5, so ion implanting forms N transoid ion floating areas
When 9 ', control is injected into STI5 ' lower section.The ion implanting agent of N transoid ions of embodiment of the present invention floating area 9 '
Measure as 1013-1015Atom per square centimeter.In addition, N transoids ion floating area 9 ' is an integral part in figure.Certainly, N is anti-
Type ion floating area 9 ' can also be multiple parts kept apart, and forming method can be：In the optical resistance glue layer of raster fashion
Block down, the N transoid ions floating area 9 ' that ion implanting is formed is exactly to be made up of multiple parts kept apart.N transoid ions
Floating area 9 ' is multiple parts kept apart, and the advantages of being integral part compared to N transoid ions floating area 9 ' is, is increased
Contact area between N transoid ions floating area 9 ' and P- drift regions 4 ', so as to add depletion layer area, and then further
Add breakdown voltage.
So far, LDPMOS of the embodiment of the present invention is formed and terminated.
Embodiments of the present invention N transoid ions floating area 9 ' is formed after source-drain electrode is formed.Need what is illustrated
It is, as long as the formation of N transoids ion floating area 9 ' of the present invention is after grid structure formation.That is, P transoid ions
Floating area 9 can also be formed between step 44 and step 45.
Fig. 5 is the LDPMOS diagrammatic cross-sections formed according to the above method.
LDPMOS has substrate 1 ', and gate oxide 2 ' and polysilicon gate 3 ', gate oxidation are sequentially formed on the surface of substrate 1 '
Layer 2 ' and polysilicon gate 3 ' are referred to as grid structure.N-type trap 8 ' is formed in substrate 1 ', is had in N-type trap 8 ' in grid structure
The symmetrically arranged P- drift regions 4 ' in both sides（P-Drift1 and P-Drift2）, it is provided between N-type trap 8 ' and P- drift regions 4 ' shallow
Source electrode 6 ' and drain electrode 7 ' are provided with trench isolations STI5 ', P- drift regions 4 '.In symmetrically arranged two P- drift regions 4 '
（P-Drift1 and P-Drift2）It is middle that the N transoid ions floating area 9 ' with desired depth, the N transoids ion floating area are set
9 ' and STI5 ' has predetermined space.
Wherein, N-type trap 8 ' can be formed by the ion implanting of similar arsenic element；P- drift regions 4 ' are appointing by such as boron
The ion implanting of what p-type element is formed；Source electrode 6 ' and the ion implanting of drain electrode 7 ' and any p-type element for passing through such as boron
To be formed, simply both ion implantation concentrations are different.The ion implanting shape that N transoid ions floating area 9 ' passes through similar arsenic element
Into.
Because N transoid ions floating area 9 ' is located in P- drift regions 4 ', there is predetermined space with STI5 ', thus N transoids from
Sub- floating area 9 ' and the intersection of P- drift regions 4 ' can produce depletion layer, not have electrically conductive ion in depletion layer, form space electricity
He Qu, so as to cause punch through voltage rise.
The LDNMOS or LDPMOS made using the method for the present invention, by being formed in symmetrically arranged two drift regions
Transoid ion floating area, the intersection in transoid ion floating area and drift region produce space-charge region, hit so as to reach raising
Wear the purpose of voltage.On the other hand, because the present invention carries out the ion note of transoid ion floating area after grid structure is formed
Enter, the channel location below such grid has blocking for grid, avoids the need for worrying by transoid ion implanting, therefore Fig. 2 f
In, carry out transoid ion implanting when, the opening of the optical resistance glue layer of patterning can do more, manifest grid structure,
Source electrode and drain electrode.So, in the case of forming multiple LDMOS at the same time, the grating that can form the optical resistance glue layer of patterning
Pattern spacing reaches 2 microns, and such large-sized grating spacings cause alignment precision so high, the requirement to board
Than relatively low, LDMOS making can be efficiently completed.Further, because the opening of the optical resistance glue layer of patterning manifests grid
Pole structure, source electrode and drain electrode, so the embodiment of the present invention can all form transoid ion floating area in two drift regions, and only
Transoid ion floating area is formed in a drift region to compare, and can further improve breakdown voltage.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
God any modification, equivalent substitution and improvements done etc., should be included within the scope of protection of the invention with principle.
Claims (10)
1. a kind of LDMOS transistor LDMOS manufacture method, the LDMOS is LDNMOS, should
Method comprises the following steps：
A, formed in substrate in LDNMOS areas and be used for the STI of isolated p-well and N- drift regions；
B, carry out ion implanting in LDNMOS areas and form p-type trap；
C, ion implanting formation is located at the symmetrically arranged N- drift regions in grid structure both sides in the p-type trap；
D, the substrate surface between N- drift regions forms grid structure；
E, N+ is carried out in N- drift regions to adulterate to form source electrode and drain electrode；
Characterized in that, this method also includes：In step D-shaped into after grid structure, the light of patterning is formed in substrate surface
Glue-line is hindered, the opening of the optical resistance glue layer of the patterning manifests grid structure, source electrode and drain electrode；With the photoresistance of the patterning
Glue-line is mask, and the ion implanting that desired depth is carried out to symmetrically arranged two N- drift regions forms the drift of P transoids ion
Floating region, the P transoids ion floating area are located in N- drift regions, have predetermined space with STI.
2. the method as described in claim 1, it is characterised in that it is described in step D-shaped into after grid structure, form P transoids
Ion floating area, including：Between step D and E, or after step E, P transoid ion floating areas are formed.
3. the method as described in claim 1, it is characterised in that the P transoids ion floating area is integral part, Huo Zhewei
Multiple parts kept apart.
4. method as claimed in claim 3, it is characterised in that the ion implantation dosage of the P transoids ion floating area is
1013-1015Atom per square centimeter.
5. a kind of LDMOS transistor LDMOS, the LDMOS are LDNMOS, including substrate surface
Grid structure, and in p-type trap, and in the symmetrically arranged N- drift regions in grid structure both sides, p-type trap and the N- drift
Shifting is provided with STI between area, and source electrode and drain electrode are provided with the N- drift regions；Characterized in that, described symmetrically arranged
P transoid ion floating areas with desired depth are set in two N- drift regions, and the P transoids ion floating area has with STI
Predetermined space.
6. a kind of LDMOS transistor LDMOS manufacture method, the LDMOS is LDPMOS, should
Method comprises the following steps：
A, formed in substrate and be used for isolating n-type trap and the STI of P- drift regions in LDPMOS areas；
B, carry out ion implanting in LDPMOS areas and form N-type trap；
C, ion implanting formation is located at the symmetrically arranged P- drift regions in grid structure both sides in the N-type trap；
D, the substrate surface between P- drift regions forms grid structure；
E, P+ is carried out in P- drift regions to adulterate to form source electrode and drain electrode；
Characterized in that, this method also includes：In step D-shaped into after grid structure, the light of patterning is formed in substrate surface
Glue-line is hindered, the opening of the optical resistance glue layer of the patterning manifests grid structure, source electrode and drain electrode；With the photoresistance of the patterning
Glue-line is mask, and the ion implanting that desired depth is carried out to symmetrically arranged two P- drift regions forms the drift of N transoids ion
Floating region, the N transoids ion floating area are located in P- drift regions, have predetermined space with STI.
7. method as claimed in claim 6, it is characterised in that it is described in step D-shaped into after grid structure, form N transoids
Ion floating area, including：Between step D and E, or after step E, N transoid ion floating areas are formed.
8. method as claimed in claim 6, it is characterised in that the N transoids ion floating area is integral part, Huo Zhewei
Multiple parts kept apart.
9. method as claimed in claim 8, it is characterised in that the ion implantation dosage of the N transoids ion floating area is
1013-1015Atom per square centimeter.
10. a kind of LDMOS transistor LDMOS, the LDMOS are LDPMOS, including substrate surface
Grid structure, and in N-type trap, and in the symmetrically arranged P- drift regions in grid structure both sides, the N-type trap and P- drifts
Shifting is provided with STI between area, and source electrode and drain electrode are provided with the P- drift regions；Characterized in that, described symmetrically arranged
N transoid ion floating areas are provided with two P- drift regions, the N transoids ion floating area has predetermined space with STI.
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| CN116344623B (en) * | 2023-05-30 | 2023-08-22 | 粤芯半导体技术股份有限公司 | High-voltage MOS device and preparation method thereof |
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|---|---|---|---|---|
| US5514608A (en) * | 1991-05-06 | 1996-05-07 | Siliconix Incorporated | Method of making lightly-doped drain DMOS with improved breakdown characteristics |
| CN101312211A (en) * | 2007-05-25 | 2008-11-26 | 东部高科股份有限公司 | Semiconductor device and its manufacture method |
| CN101562195A (en) * | 2008-04-15 | 2009-10-21 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
| CN101800247A (en) * | 2010-03-12 | 2010-08-11 | 上海宏力半导体制造有限公司 | LDMOS device capable of improving breakdown voltage and manufacturing method thereof |
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| US6800903B2 (en) * | 1996-11-05 | 2004-10-05 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
| US7851857B2 (en) * | 2008-07-30 | 2010-12-14 | Freescale Semiconductor, Inc. | Dual current path LDMOSFET with graded PBL for ultra high voltage smart power applications |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5514608A (en) * | 1991-05-06 | 1996-05-07 | Siliconix Incorporated | Method of making lightly-doped drain DMOS with improved breakdown characteristics |
| CN101312211A (en) * | 2007-05-25 | 2008-11-26 | 东部高科股份有限公司 | Semiconductor device and its manufacture method |
| CN101562195A (en) * | 2008-04-15 | 2009-10-21 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
| CN101800247A (en) * | 2010-03-12 | 2010-08-11 | 上海宏力半导体制造有限公司 | LDMOS device capable of improving breakdown voltage and manufacturing method thereof |
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