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CN104518023A - 高压ldmos器件 - Google Patents

高压ldmos器件 Download PDF

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CN104518023A
CN104518023A CN201310460839.9A CN201310460839A CN104518023A CN 104518023 A CN104518023 A CN 104518023A CN 201310460839 A CN201310460839 A CN 201310460839A CN 104518023 A CN104518023 A CN 104518023A
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voltage
withstand voltage
ldmos device
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CN104518023B (zh
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祁树坤
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CSMC Technologies Corp
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Wuxi CSMC Semiconductor Co Ltd
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Abstract

一种高压LDMOS（横向双扩散金属氧化物半导体）器件，包括P型沟道区、N型漂移区、耐压层以及位于底部的P型衬底，所述耐压层位于P型衬底及N型漂移区之间。本发明高压LDMOS器件通过引入耐压层，使得工艺上降低了推阱时间，提高了电流通道截面面积，改善导通电阻，同时通过提高纵向耐压提升横向耐压。

Description

高压LDMOS器件
技术领域
本发明涉及集成电路领域，尤其涉及一种高压LDMOS器件。 
背景技术
由于BCD（bipolar-CMOS-DMOS）技术的高压、低功耗、集成度高的优势，由BCD技术制成的HVIC(高压集成电路)、SPIC（智能功率集成电路）等集成电路越来越多的应用于马达驱动、大功率LED照明以及白色家电的IPM（智能功率模块）变频模块中。BCD技术的核心器件UHV-NLDMOS（超高压-N型横向双扩散金属氧化物半导体）更以耐压高、低导通电阻占据开发难度之首，各大公司竞相推出各具特色的器件结构。为了获得低导通电阻而形成深结、浓度高的N型（电子型）漂移区，但只能获得低耐压值；通过在N型漂移区表面形成沿沟道方向带状分布的P型（空穴型）降场层，经过推阱形成一定结深，以达到与N型深结内的电荷平衡来增强漂移区耗尽，提高耐压；而经过热过程后，N型漂移区杂质浓度受到P型降场层杂质的影响而降低，有效电流截面通道减小，削弱电流流经的路径，相反地提高了导通电阻。因此为获得高耐压、低导通电阻，必须通过其它途径降低P型降场层杂质对N型漂移区杂质浓度的负面影响，扩展有效电流通道，降低导通电阻并获得高耐压值。 
由于现有技术无法同时兼顾高耐压及低导通电阻的正向需求，同时由于N型漂移区推阱时间长，带来成本和能耗的负面影响，需要提出新的器件以进行工艺和器件两方面的优化、改善。 
发明内容
本发明要解决的技术问题是提供一种可增加耐压且降低导通电阻高压LDMOS器件。 
本发明的技术方案为一种高压LDMOS器件，包括P型沟道区、N型漂移区、耐压层以及位于底部的P型衬底，所述耐压层位于P型衬底及N型漂移区之间。 
如上所述的高压LDMOS器件，所述耐压层包括交错排列的P型埋层及N型埋层。 
如上所述的高压LDMOS器件，所述耐压层延伸至LDMOS器件的水平两端侧。 
如上所述的高压LDMOS器件，所述耐压层垂直邻接N型漂移区。 
如上所述的高压LDMOS器件，所述P型沟道区与N型漂移区呈水平排列，且P型沟道区与N型漂移区均位于耐压层的正上方。 
如上所述的高压LDMOS器件，所述P型衬底位于耐压层下方，而未延伸至耐压层的两端。 
如上所述的高压LDMOS器件，所述P型埋层及N型埋层均垂直于N型漂移区。 
如上所述的高压LDMOS器件，所述耐压层在形成外延前成型。 
如上所述的高压LDMOS器件，所述耐压层由掩膜版光刻注入推结成型。 
如上所述的高压LDMOS器件：所述耐压层包括至少两个N型埋层及位于N型埋层之间的若干P型埋层。 
本发明高压LDMOS器件通过引入耐压层，使得工艺上降低了推阱时间，提高了电流通道截面面积，降低导通电阻，同时通过提高纵向耐压提升横向耐压。 
附图说明
附图1为发明第一实施例中高压LDMOS器件的结构示意图； 
附图2为发明第一实施例中高压LDMOS器件的部分示意图。 
具体实施方式
下面结合附图所示的各实施方式对本发明进行详细说明，但应当说明的是，这些实施方式并非对本发明的限制，本领域普通技术人员根据这些实施方式所作的功能、方法、或者结构上的等效变换或替代，均属于本发明的保护范围之内。 
图1是本发明第一实施例中高压LDMOS器件100的示意图，其包括P型衬底10、位于P型衬底上方的耐压层20、位于耐压层20上方的P型沟道区30、N型漂移区40及位于N型漂移区上方P型降场层50。 
所述P型衬底10作为高压LDMOS器件100的基底，P型衬底设置于耐压 层20的下方，而未延伸至耐压层20两侧及上方。P型沟道区30与N型漂移区40则呈水平排列，且两者均位于耐压层20的正上方。所述耐压层20在形成外延之前，采用掩膜版光刻注入推结成型，经过外延及后续的热过程，减缓浓度梯度，纵向上可与高压漂移区相连，使电势分布更为均匀。 
所述耐压层包括P型埋层21与N型埋层22，P型埋层21与N型埋层22呈水平交错排列，所述P型埋层21及N型埋层22均垂直于N型漂移区40。耐压层20水平延伸至高压LDMOS器件的两端侧，其与位于其上方的N型漂移区在竖直方向上至少部分对齐，耐压层中的N型埋层22可实现电流路径更大、导通电阻更小的功效。在较佳实施例中，耐压层20垂直邻接N型漂移区。 
当漏端外加高压从而引入的高电位时，P型埋层21与N型埋层22可削弱电场的横向及纵向矢量，并将一部分耗尽层推向P型衬底10深处，从而降低N型漂移区40及P型沟道区30表面的电场，提高器件整体耐压水平。同时，N型埋层22还可实现增大电流通道及降低导通电阻目的；P型埋层21的设置，则降低了P型降场层50的杂质注入剂量，可得到最大化的纵向耐压，使其大于由P型降场层及N型漂移区的横向可耐受电压，实现横向可变P型降场层尺寸，最终降低导通电阻同时提高耐压，降低栅漏电容，改善其开关特性。另外，雪崩击穿首先发生在N型埋层而不是P型衬底表面，增强了高压LDMOS器件100的可靠性。 
图2为本发明的第二实施例，图2为高压LDMOS器件500的部分示意图（省略元件请参见图1），本实施例中除耐压层的结构外，其他结构与第一实施 例相同，在此不再赘述。本实施中的耐压层50包括N型埋层51以及位于N型埋层之间的多个P型埋层52构成，藉由N型埋层51及P型埋层52同样可实现降低导通电阻及提高耐压的功效（具体原理请参考第一实施例）。 
综上所述，本发明通过高压LDMOS器件引入耐压层，使得工艺上降低了推阱时间，提高了电流通道截面面积，改善导通电阻，同时通过提高纵向耐压藉以提升横向耐压。 

Claims (10)

1.一种高压LDMOS器件，其特征在于：包括P型沟道区、N型漂移区、耐压层以及位于底部的P型衬底，所述耐压层位于P型衬底及N型漂移区之间。
2.如权利要求1所述的高压LDMOS器件，其特征在于：所述耐压层包括交错排列的P型埋层及N型埋层。
3.如权利要求2所述的高压LDMOS器件，其特征在于：所述耐压层延伸至高压LDMOS器件的水平两端侧。
4.如权利要求2所述的高压LDMOS结构，其特征在于：所述耐压层垂直邻接N型漂移区。
5.如权利要求3所述的高压LDMOS器件，其特征在于：所述P型沟道区与N型漂移区呈水平排列，且P型沟道区与N型漂移区均位于耐压层的正上方。
6.如权利要求2所述的高压LDMOS器件，其特征在于：所述P型衬底位于耐压层下方，而未延伸至耐压层的两端。
7.如权利要求第2项所述的高压LDMOS器件，其特征在于：所述P型埋层及N型埋层均垂直于N型漂移区。
8.如权利要求2至7项中任一项所述的高压LDMOS器件，其特征在于：所述耐压层在形成外延前成型。
9.如权利要求8所述的高压LDMOS器件，其特征在于：所述耐压层由掩膜版光刻注入推结成型。
10.如权利要求1所述的高压LDMOS器件，其特征在于：所述耐压层包括至少两个N型埋层及位于N型埋层之间的若干P型埋层。
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Cited By (8)

* Cited by examiner, † Cited by third party
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CN105679831A (zh) * 2016-03-16 2016-06-15 上海华虹宏力半导体制造有限公司 横向扩散场效应晶体管及其制造方法
CN106231213A (zh) * 2016-09-29 2016-12-14 北方电子研究院安徽有限公司 一种可消除smear效应的带快门ccd像元结构
CN107180856A (zh) * 2017-05-26 2017-09-19 电子科技大学 一种pmos器件结构
CN108346696A (zh) * 2017-01-22 2018-07-31 中芯国际集成电路制造(上海)有限公司 Ldmos器件及其制造方法
TWI695434B (zh) * 2018-05-25 2020-06-01 大陸商矽力杰半導體技術（杭州）有限公司 橫向擴散金屬氧化物半導體結構和其形成方法
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