CN104508641B - Many groups attribute field in single page table entry - Google Patents

Abstract

First processing unit (110) and the second processing unit (120) can access system storage (130), the shared page table (132) that described system storage (130) stores described first processing unit and described second processing unit is shared.Described shared page table can store the mapping for the virtual memory address of the memory block by the effort access applied to physical memory address.Page entry in described shared page table can comprise define described first processing unit to first group of attribute position of the accessibility of described memory block, define described second processing unit second group of attribute position to the accessibility of described the same memory block, and define the physical address bits of the physical address of described memory block.

Description

Many groups attribute field in single page table entry

Technical field

The present invention relates generally to calculate, and more precisely, relate to virtual memory address space is mapped to physics The technology of memory address space.

Background technology

Typical calculating system comprises multiple processing unit, such as CPU (CPU) and Graphics Processing Unit (GPU), it is read out from physical storage and writes physical storage.The various processing units of device can be real Execute virtual solution so that can to just by the adjacent virtual address space of the assigned applications of client executing without guarantor Stay adjacent physical memory space.Each processing unit is generally of MMU (MMU) to be deposited by virtual Memory address is translated as the physical address in physical storage.In order to perform required virtual address reflecting to physical address Penetrating, each MMU maintains the size of each in single page table, and these single page tables in the system memory Can be several Mbytes.

Summary of the invention

In general, the technology described in the present invention relates to the calculating device implementing virtual address to the mapping of physical address. According to the technology of the present invention, two or more processing units can be shared for mapping virtual address to being total to of physical address Use page table.The page table entries of described shared page table can comprise organizes attribute field more, such as the attribute of the first processing unit Group, set of properties for the second processing unit, and other set of properties.Use and described organize attribute field more, can be individually Management is for the attribute of two or more processing units.For example, the technology described in the present invention can allow first The individual management accessed with the read/write of the second processing unit, so that the read/write for a processing unit is deposited Take the read/write that may differ from for the second processing unit to access.

According to an example, a kind of equipment comprises the first processing unit, the second processing unit and memorizer.Described memorizer Store shared page table that described first processing unit and described second processing unit share and storage for being accessed by operation The virtual memory address of memory block is to the mapping of physical memory address.Described memorizer is also in described shared page table Store described first processing unit and described second processing unit in order to access the page of a memory block of multiple memory block Entry, wherein said page entry includes defining first group to the accessibility of described memory block of described first processing unit Attribute position, define described second processing unit second group of attribute position to the accessibility of described the same memory block, and boundary The physical address bits of the physical address of fixed described memory block.

According to another example, a kind of method comprises the shared page table being stored in memorizer by the first processing unit use by void Plan memory address translation is physical memory address；Accessed by described physical memory address by described first processing unit The memory block identified；Used the described shared page table being stored in described memorizer by described virtual by the second processing unit Memory address translation is described physical memory address；And accessed by described physical storage by described second processing unit The described memory block of Address Recognition.Described shared page table is total to by described first processing unit and described second processing unit With and storage for the virtual memory address of memory block that accessed by operation to the mapping of physical memory address.Described Shared page table include described first processing unit and described second processing unit in order to access the page entry of described memory block, And described page entry include defining described first processing unit to first group of attribute position of the accessibility of described memory block, Define described second processing unit second group of attribute position to the accessibility of described the same memory block, and deposit described in defining The physical address bits of the physical address of reservoir block.

According to another example, a kind of equipment comprises the first processing means, the second processing means and memorizer.At described first Reason device includes that virtual memory address is translated as physics and deposits by the shared page table being stored in described memorizer for use The device of memory address；And for access by the device of memory block of described physical memory address identification, and described the Two processing meanss include for using the described shared page table being stored in described memorizer by described virtual memory address It is translated as the device of described physical memory address；And for access by the described storage of described physical memory address identification The device of device block.Described shared page table shared by described first processing means and second processing means the second processing means and Storage for the virtual memory address of memory block that accessed by operation to the mapping of physical memory address.Described shared Page table include described first processing means and described second processing means in order to access the page entry of described memory block, and institute State page entry include defining described first processing means to first group of attribute position of the accessibility of described memory block, define Described second processing means second group of attribute position to the accessibility of described the same memory block, and define described memorizer The physical address bits of the physical address of block.

According to another example, a kind of computer-readable storage medium storage instruction, described instruction causes first when executed Processing unit and the second processing unit: used the shared page table being stored in memorizer by virtual by described first processing unit Memory address translation is physical memory address；Known by described physical memory address by described first processing unit access Other memory block；Used the described shared page table being stored in described memorizer by described void by described second processing unit Intending memory address translation is described physical memory address；And accessed by described physical store by described second processing unit The described memory block of device Address Recognition.Described shared page table is described first processing unit and described second processing unit institute Share and storage for the virtual memory address of memory block that accessed by operation to the mapping of physical memory address.Institute State shared page table and include that described first processing unit and described second processing unit are in order to access the page entry of memory block.Institute State page entry include defining described first processing unit to first group of attribute position of the accessibility of described memory block, define Described second processing unit second group of attribute position to the accessibility of described the same memory block, and define described memorizer The physical address bits of the physical address of block.

Accompanying drawing explanation

Fig. 1 displaying is configured to the mapping skill to physical memory address of the virtual memory address described in the enforcement present invention The example calculating device of art.

Fig. 2 displaying is configured to the mapping skill to physical memory address of the virtual memory address described in the enforcement present invention Another example calculating device of art.

Fig. 3 shows have the shared page organizing attribute field in single page table entries according to the technology described in the present invention more The concept map of table.

Fig. 4 shows the flow process to the mapping techniques of physical memory address of the virtual memory address described in the present invention Figure.

Detailed description of the invention

In general, the technology described in the present invention relate to implement virtual address to physical address mapping (in the present invention and also Be referred to as virtual to physical mappings) calculating device.More particularly, be directed to can be by two for the technology described in the present invention Or the shared page table that more processing unit is shared.The page table entries of described shared page table can comprise organizes attribute field more, example Such as the set of properties for the first processing unit, the set of properties for the second processing unit, and other set of properties.Use institute State and organize attribute field more, can individually manage the attribute for two or more processing units.For example, for one The read/write access of individual processing unit may differ from accessing for the read/write of the second processing unit.

The such as processing unit such as CPU (CPU) and Graphics Processing Unit (GPU) needs to access physical storage (that is, be read from data and it write data).In order to read or write data, in processing unit uses memorizer The physical address of position access and will be read from data or the described physical storage to its write data described in Position.But, processing unit can be difficult to manage all memory blocks and (that is, it can be write data or be read from data The position of physical storage) physical address.In order to overcome this difficulty, processing unit can use virtual addressing.Seek virtual In location, assign adjacent virtual memory address to the application (that is, client) performed on a processing unit.Application can be wrapped Including multiple operation, wherein different work performs in different processing units.Each in processing unit comprises deposits accordingly Reservoir administrative unit (MMU).The MMU of each in processing unit has and determines actual depositing from virtual memory address The task of memory address (being also called physical memory address).

For example, MMU comprises the cache memory being referred to as Translation Look side Buffer (TLB).TLB stores use Virtual to physics in selected memory block (such as, the memory block of access recently or the memory block of frequent access) Map.In order to access memory block, the virtual memory address being used for memory block is fed to MMU by processing unit. MMU transfers access TLB to identify the physical memory address for described memory block.It is mapped in TLB described In available time (being referred to as TLB hit), MMU uses physical memory address to access memory block subsequently.Or, MMU Physical memory address is fed to different units or the module of processing unit, and it uses physical memory address to access subsequently Memory block.

In some cases, TLB can not comprise the mapping (being referred to as TLB miss) for virtual memory address.Lift For example, processing unit may need to access the memorizer in the page entry that its physical address is not included in being stored by TLB Block, because described memory block is not to access recently or the memory block of frequent access.When occurring at this, processing unit is deposited Take the page table being stored in system storage.

Page table part similar with TLB is, both stores and map virtual memory address is arrived physical memory address Page entry.A page table entries in page table or in TLB is by a map virtual memory address to physical storage Address.But, compared with the TLB in the MMU being locally stored in processing unit, page table is stored in system storage In.And, because page table storage has to physical address map rather than such as TLB etc. for the whole virtual of processing unit Limited number page entry, so the size of page table typically size than TLB is much bigger.For example, the big I of page table In the range of several Mbytes.

In some technology, the corresponding page table of system storage storage each in processing unit.For example, System storage storage is used for a page table of CPU and stores another the single page table for GPU.But, at some In the case of, these different page tables comprise identical page table entries.Therefore, can likely multiple page tables in CPU page table Entry is equal to the page table entries in GPU page table.For example, the page table entries in CPU page table can be virtual by one Storage address is mapped to the page table entries in physical memory address, and GPU page table can be by identical virtual memory Address is mapped to identical physical memory address.

As an example, the operating system performed on CPU can have the virtual memory address that will abut against and be assigned to The task of application.Described application can comprise multiple operation or task, and some of them operation performs on CPU and some are made Industry performs on GPU.Mapping between virtual memory address and physical memory address also can be stored by operating system In page table.Because operating system has assigns virtual memory address and these are virtual for both CPU and GPU Storage address is mapped to the task of physical address, so operating system can create storage institute for both CPU and GPU State the virtual shared page table to physical mappings.

Benefit can be there is in CPU and GPU sharing this shared page table.For example, system storage no longer stores The page table entries repeated, system storage can store the identical page table entries in CPU page table and GPU page table Single page entry, it facilitates memory savings.Additionally, because there is a page entry for these same page table clauses, So updating single page table entries rather than two identical page table entries can be the most more effective.

Have been developed over some prior aries and share to realize page table.In these techniques, CPU MMU and GPU MMU Each the pointer pointing to the position sharing page table is stored in the system memory.Memory block is accessed at CPU and GPU Time, their corresponding MMU uses their pointer with from shared page table retrieval physical memory address.But, These technology for shared page table can suffer the different access energy not identifying different processing units to memory block sometimes The problem of power.

Different access capabilities can be associated with different processing units.For example, page entry is being conventionally 32. First 12 are left attribute position, and remaining 20 identify physical memory address.These attribute position identifying processing lists The access capability of unit.As an example, can be appointed as some in memory block can read and writable, and can be by Other memory block is appointed as only can read.One or more position of attribute position is enforced this accessibility and is limited.Except inciting somebody to action Memory block is appointed as can read and outside the writable or position that only can read, there is other example of position in attribute position. For example, attribute position one or more other may indicate that the data in some memory block also should be stored in speed buffering In memorizer (such as, the L2 cache memory of processing unit).In this way, the attribute position of page entry can describe by The memory block of the address bit addressing in page entry.

In some cases, the attribute position for a processing unit can need to be different from the attribute for another processing unit Position.For example, some blocks can be appointed as can entering and read by described CPU write by the operating system performed on CPU, And be appointed as these same blocks only to be read by GPU.For example, CPU and GPU comprises they oneself wherein In the examples described above of the corresponding page table of body, being mapped in each in page table of virtual address to physical address May be identical, but attribute position can differ.Wherein CPU and GPU share shared page table as described above other In example, attribute position can be shared by both CPU and GPU.This forces operating system to define for CPU or GPU It is not intended to both attribute positions.

For example, in the above example, attribute position is to define the accessibility of CPU but is not necessarily depositing of GPU The attribute position of taking property.This can potentially result in is not good at managing block.For example, it may be desired to by memory block can Accessibility is limited to can read only for GPU.But, because this block can be read by CPU and write, and attribute position is not Distinguishing between CPU and GPU, so using in the example of the pointer in shared page table wherein, GPU can be not intended to Memory block is write by ground.

The technology of the present invention is directed to specifically specify the attribute position for different processing units.For example, GPU attribute The accessibility of GPU is defined in position and the accessibility of CPU is defined in CPU attribute position.In this way, different processing units Shared page table can be shared, and describe GPU to the accessibility of memory block and for CPU for the attribute position of GPU Attribute position the CPU accessibility to memory block is described.Because specifically for CPU and GPU specified attribute position, So the probability that memory block is write by GPU improperly can reduce, simultaneously because need not for CPU and The different page tables of GPU and memorizer can be realized and save.

The various technology specifying the attribute position for different processing units can be there are.For example, as described above, Generally 12 in 32 in page entry reserved for attribute position.The value of the many persons in these 12 is for GPU And can be identical both CPU.CPU and GPU of remaining bit can be different for to(for) its value, operating system can specifically refer to Which position fixed is used for GPU for CPU and which position.For example, the first two position in 12 attribute positions can be reserved Whether can be entered by CPU write, read or write with instruction memory block and read, following in described 12 attribute positions Two positions can reserved with instruction memory block whether can be write, read or write by GPU and be read, and be remaining Eight positions can share for both GPU and CPU.

As another example, page entry can comprise more than 32 positions (such as, 40).In this example, last 20 May be reserved for address map, and front 20 can be reserved for attribute position.In these 20 front 10 can be through Be preserved in CPU, and these 20 last 10 can be reserved for GPU.Or, its six positions can be through It is preserved for CPU.Ensuing six positions can be reserved for GPU, and ensuing 8 can be by CPU and GPU Share.These distribution of position are set is example.The technology of the present invention should not be considered as limited to above example.Although for solution The purpose released, describes some technology in the technology of the present invention, it should be appreciated that the present invention's with reference to CPU and GPU Technology it be also possible to use other type of processing unit and implements.

Fig. 1 shows the example calculation device of the technology that can implement the present invention, calculates device 100.Calculate the reality of device 100 Example is including (but not limited to) mobile radiotelephone, personal digital assistant (PDA), video game console, handheld games list Unit, mobile video session unit, laptop computer, desktop PC, TV set-top box, digital media player, Smart phone, tablet PC, camera and fellow.Although being not merely limited to the device of resource-constrained, but the present invention Technology can be particularly advantageous for the device comprising the resource-constrained of battery powered device.The technology of the present invention can (such as) be led to Cross and more efficiently use limited device memory to improve single unit system performance, and can drop by maintaining less page table Low computation complexity, it can transfer improve the response of device and reduce power consumption.

Calculate device 100 and comprise the first processing unit the 110, second processing unit 120 and system storage 130.First Processing unit 110 comprises MMU 112, and the second processing unit 120 comprises MMU 122.MMU 110 can comprise TLB 114, and MMU 122 can comprise TLB 124.First processing unit 110 can (such as) be the CPU of device 100. Second processing unit 120 can (such as) be the operable GPU with the output graph data for presenting over the display.The One processing unit 110 and the second processing unit 120 can additionally represent that other type of processing unit (is such as used for comprising display Device controller, the processing unit of various peripheral units of interconnection device), or from processor unloadings such as such as CPU or GPU Any kind of Digital Signal Processing (DSP) core of signal processing.First processing unit 110 and the second processing unit 120 Example can including (but not limited to) digital signal processor (DSP), general purpose microprocessor, special IC (ASIC), Field programmable logic array (FPGA) or the integrated or discrete logic of other equivalence.Although typically will be with reference at two Reason unit describes the technology of the present invention, but two or more processing unit can be used to implement described technology.

System storage 130 can be the example of computer-readable storage medium.System storage 130 can (such as) be a class The random access memory (RAM) of type, such as dynamic ram, static RAM, IGCT RAM, zero capacitor RAM, Pair transistor RAM, or some other type of volatile memory.System storage 130 can be also non-volatile depositing Reservoir, such as flash memory or other type of non-volatile ram.System storage 130 can store and cause process Unit 110 and processing unit 120 perform the instruction of the function of each being attributed in the present invention.In this way, system is deposited Reservoir 130 can be considered to include the computer-readable storage medium of instruction, described instruction cause such as processing unit 110 and Processing unit 120 one or more processor such as grade performs various functions.But, in some instances, this type of instruction can store (Fig. 1 does not shows) in the memorizer in addition to system storage 130.

First processing unit 110 and the second processing unit 120 are configured to read data and to being from system storage 130 System memorizer 130 writes data.In order to read or write data, the first processing unit 110 and the second processing unit 120 It is configured to access the specific physical location in system storage 130.These ad-hoc locations can (such as) be the block of 4KB, And each piece of unique physical location can with himself.But, as introduced above, the first processing unit 110 and Two processing units 120 can implement virtual addressing, to the left on the first processing unit 110 or the second processing unit 120 The virtual memory address that the assigned applications performed is adjacent.But, corresponding to the thing of these adjacent virtual memory addresses Reason storage address may be segmented and be non-adjacent.Therefore, processing unit 110 and processing unit 120 can use this The non-adjacent physical memory address of some adjacent virtual memory addresses and non-corresponding processes data.But, at place When reason unit 110 and processing unit 120 need to access system storage 130 (that is, be read from or write it), need These virtual memory addresses are translated as physical memory address.

MMU 112 is configured to map virtual memory address to physical storage ground for the first processing unit 110 Location, and MMU 122 is configured to map virtual memory address for the second processing unit 120 to physical storage Address.The complete page table with whole group of page entry is stored in shared page table 132.Every in TLB 114 and TLB 124 One storage is stored in the subset of the page entry in shared page table 132.Described subset can (such as) be the page bar accessed recently Mesh, the page entry of frequent access, or based on the page entry selected by some other criterions.It is stored in the page in TLB 114 The subset of entry may differ from the subset of the page entry being stored in TLB 124.For example, by the first processing unit 110 Access recently via MMU 112 or the page table entries of frequent access may differ from by the second processing unit 120 via MMU The 122 nearest or page table entries of frequent access.Therefore, TLB 114 can store page table entries different from TLB 124 Collection.

If the (such as) first processing unit 110 needs virtual memory address is translated as physical memory address, TLB 114 stores when the page entry of described virtual memory address, then MMU 112 can use TLB 114 true The fixed physical memory address corresponding to particular virtual memory address.Physical memory address determined by use, processes Unit 110 can be read out from the specific physical location of system storage 130 or write it.Similarly, if second Processing unit 120 needs virtual memory address is translated as physical memory address, in TLB 124 storage for described During the page entry of virtual memory address, then MMU 122 can use TLB 124 virtual to deposit corresponding to specific to determine The physical memory address of memory address.Physical memory address determined by use, processing unit 120 can be deposited from system Reservoir 130 reads or writes it.

As introduced above, TLB 114 and TLB 124 can be the virtual of the storage subset for only virtual memory address Cache memory to physical mappings.Therefore, what TLB 114 can not store for processing unit 110 is whole virtual To physical mappings, and similarly, it is whole virtual to physical mappings that TLB 124 can not store for processing unit 120. In some cases, MMU 112 can it needs to be determined that do not have the mapping that is stored in TLB 114 for virtual memory The corresponding physical memory address of device address.In order to determine be not included in TLB 114 for virtual memory address Mapping, the first processing unit 110 can access the shared page table 132 being stored in system storage 130.Share page table 132 Comprise for processing unit 110 is whole virtual to physical mappings, and therefore, big than TLB 114 and TLB 124 Many.

Such as MMU 112, in some cases, MMU 122 can be it needs to be determined that do not have and be stored in TLB 124 The corresponding physical memory address for virtual memory address mapped.In order to determine the use being not included in TLB 124 In the mapping of virtual memory address, the second processing unit 120 can access the shared page being stored in system storage 130 Table 132.In this way, MMU 122 can work in the way of being substantially similar to MMU 112.Share page table 132 Comprise for processing unit 120 and whole virtual to physical mappings for processing unit 110.In this way, first Processing unit 110 and the second processing unit 120 share identical page table (shared page table 132 i.e., in the example of fig. 1). If maintenance is used for the single page table of processing unit 110 and processing unit 120 by MMU 112 and MMU 122, that The shared page table 132 shared by processing unit 110 and processing unit 120 is smaller than the combined size of two page tables.Altogether Be smaller than the combined size of two single page tables with page table 132 because share page table 132 some page table entries by Both MMU 112 and MMU 122 share.

Share page table 132 and can comprise multiple pages of the physical memory address by map virtual memory address to memory block Entry.Memory block can be a part for the system storage 130 that individually can access via its physical memory address. Every one page entry can comprise first group of attribute position and second group of attribute position.First group of attribute position can set and process list for first The control of unit 110, such as authority and access rights, and second group of attribute position sets the control for the second processing unit 120 System.Every one page entry optionally comprises the attribute position of one or more additional set, such as, set for the first processing unit 110 And one group of attribute position of the shared control that second both processing unit 120.

First group of attribute position and second group of attribute position for sharing the page entry of page table 132 can make the first processing unit 110 and second processing unit 120 can have different authorities and access rights sharing to share while page table.As One example, first group of attribute position can be set to so that the first processing unit 110 has the spy to system storage 130 Determine both reading and the write access of memory block, and the second processing unit 120 can only have identical particular memory block Reading access.Certainly, other configuration is also possible, and the such as second processing unit 120 has reading and write access Both, and the first processing unit 110 only has reading access, or the first processing unit 110 and the second processing unit 120 In one have reading and write access both, and another one neither have reading access the most do not have write access.

Fig. 2 shows another example calculation device (calculating device 200) of the technology that can implement the present invention.Calculate device 200 Example including (but not limited to) mobile radiotelephone, personal digital assistant (PDA), video game console, hand-held trip Programme unit, mobile video session unit, laptop computer, desktop PC, TV set-top box, Digital Media are broadcast Put device, smart phone, tablet PC, camera and fellow.Calculate device 200 comprise the first processing unit 210, Second processing unit the 220, the 3rd processing unit 240, input/output MMU (IOMMU) 222 and system Memorizer 230.First processing unit 210 comprises MMU 212.Second processing unit 220 and the 3rd processing unit 240 Each not there is special MMU, but share and share MMU (that is, the IOMMU 222 in Fig. 2).First processes Unit 210 can (such as) be the CPU of device 200.Second processing unit 120 can (such as) be operable with output for The GPU of the graph data presented over the display.3rd processing unit 240 can (such as) be the processing unit of the 3rd type, The processing unit of such as peripheral unit.First processing unit the 210, second processing unit 220 and the 3rd processing unit 240 Example can including (but not limited to) digital signal processor (DSP), general purpose microprocessor, special IC (ASIC), Field programmable logic array (FPGA) or the integrated or discrete logic of other equivalence.

System storage 230 can be the example of computer-readable storage medium.System storage 230 can (such as) be a class The random access memory (RAM) of type, such as dynamic ram, static RAM, IGCT RAM, zero capacitor RAM, Pair transistor RAM, or some other type of volatile memory.System storage 230 can be also non-volatile depositing Reservoir, such as flash memory or other type of non-volatile ram.System storage 230 can store and cause process Unit 210 and processing unit 220 perform the instruction of the function of each being attributed in the present invention.In this way, system is deposited Reservoir 230 can be considered to include the computer-readable storage medium of instruction, described instruction cause such as processing unit 210, One or more processors such as processing unit 220 and/or processing unit 240 perform various functions.But, in some instances, This type of instruction can be stored in the memorizer in addition to system storage 230 (not to be shown in Fig. 2).

First processing unit the 210, second processing unit 220 and the 3rd processing unit 240 are configured to from system storage 230 read data and it are write data.In order to read or write data, the first processing unit 210, second processes single Unit 220 and the 3rd processing unit 240 are configured to access the specific physical location in system storage 230.These are specific Position can (such as) be the block of 4KB, and each piece of unique physical location can with himself.As introduced above, so And, first processing unit the 210, second processing unit 220 and the 3rd processing unit 240 can implement virtual addressing, so that Must be to the work of the application performed on first processing unit the 210, second processing unit 220 and/or the 3rd processing unit 240 Industry assigns adjacent virtual memory address.But, corresponding to the physical storage of these adjacent virtual memory addresses Address may be segmented and be non-adjacent.Therefore, processing unit 210, processing unit 220 and the 3rd processing unit 240 Can use these adjacent virtual memory addresses and the non-adjacent physical memory address of non-corresponding processes data.So And, need to access system storage 230 (that is, from it at processing unit 210, processing unit 220 and processing unit 240 Read or it write) time, need these virtual memory addresses are translated as physical memory address.

MMU 212 is configured to map virtual memory address to physical storage ground for the first processing unit 210 Location.IOMMU 222 is configured to virtual memory for both the second processing unit 220 and the 3rd processing unit 230 Device address is mapped to physical memory address.The complete page table with whole group of page entry is stored in shared page table 232.TLB Each storage in 214 and TLB 224 is stored in the subset of the page entry in shared page table 232.Described subset can (example As) it is page entry, the page entry of frequent access accessed recently, or based on the page entry selected by some other criterions.

If the (such as) first processing unit 210 needs virtual memory address is translated as physical memory address, TLB 214 stores when the page entry of described virtual memory address, then MMU 212 can use TLB 214 true The fixed physical memory address corresponding to particular virtual memory address.Physical memory address determined by use, processes Unit 210 can read from system storage 230 or write it.Similarly, if the second processing unit 220 or the 3rd Processing unit 240 needs virtual memory address is translated as physical memory address, in TLB 224 storage for described During the page entry of virtual memory address, then MMU 222 can use TLB 224 virtual to deposit corresponding to specific to determine The physical memory address of memory address.Physical memory address determined by use, the second processing unit 220 and the 3rd Processing unit 240 can read from system storage 230 or write it.

As introduced above, TLB 214 and TLB 224 can be the virtual of the storage subset for only virtual memory address Cache memory to physical mappings.Therefore, what TLB 214 can not store for the first processing unit 210 is whole Virtual to physical mappings, and similarly, TLB 224 can not store for the second processing unit 220 and the 3rd processing unit 240 whole virtual to physical mappings.In some cases, MMU 212 can be it needs to be determined that do not have and be stored in TLB 214 In the corresponding physical memory address for virtual memory address of mapping.It is not included in TLB 214 to determine The mapping for virtual memory address, MMU 212 is stored in the shared page table 232 in system storage 230. Share that page table 232 comprises for processing unit 210 is whole virtual to physical mappings, and therefore, big than TLB 214 Much.

Such as the first processing unit 210, in some cases, the second processing unit 220 can be it needs to be determined that do not have storage The corresponding physical memory address for virtual memory address of the mapping in TLB 224.It is not included in determine The mapping for virtual memory address in TLB 224, MMU 222 is stored in being total in system storage 230 With page table 232.Share page table 232 to comprise for the first processing unit 210 and for the second processing unit 220 and the Three processing units 240 whole virtual to physical mappings.In this way, first processing unit the 210, second processing unit 220 and the 3rd processing unit 240 share identical page table (shared page table 232 i.e., in the example of figure 2).

Share page table 232 and can comprise multiple pages of the physical memory address by map virtual memory address to memory block Entry.Every one page entry can comprise first group of attribute position and second group of attribute position.First group of attribute position can set for first The control of processing unit 210, such as authority and access rights, and second group of attribute position sets for the second processing unit 220 And the 3rd control of processing unit 240.Every one page entry optionally comprises the attribute position of one or more additional set, such as Set for first processing unit the 210, second processing unit 220 and the whole shared control of the 3rd processing unit 240 One group of attribute position.

In some instances, second group of attribute can set the control of all processing units for sharing IOMMU 222. Therefore, in this example, second group of attribute position is defined for both the second processing unit 220 and the 3rd processing unit 240 Control.But, in other example, the second processing unit 220 and the 3rd processing unit 240 can each have one group Special attribute position.In this example, second group of attribute can set the control for the second processing unit 220, and the 3rd group Attribute position can set the control for the 3rd processing unit 240.

First group of attribute position and second group of attribute position for sharing the page entry of page table 232 can make the first processing unit 210 have and the second process list while sharing shared page table with the second processing unit 220 and the 3rd processing unit 240 Unit 220 and the 3rd different authority of processing unit 240 and access rights.As an example, first group of attribute position can be through It is set so that the first processing unit 210 has reading and the write access of the particular memory block to system storage 230 Both power, and the second processing unit 220 and the 3rd processing unit 240 can only have the reading to identical particular memory block Access right.Certainly, other configuration is also possible, and the such as second processing unit 220 and the 3rd processing unit 240 have Read and write both access rights, and the first processing unit 210 only has reading access right, or the second processing unit 220 And the 3rd processing unit 240 there is reading and write both access rights, and the first processing unit 210 neither has reading and deposits Weighting does not the most have write access right.

Fig. 3 is the concept map that explanation shares each side of page table 332.Shared page table can represent the shared page table 132 of Fig. 1 Or the shared page table 232 of Fig. 2.Fig. 3 is set is conceptual for the purpose explained, and is not necessarily to be construed as representing Actual data structure.Share page table 332 and comprise multiple pages of entries.Every one page entry comprise first group of attribute position 352A-N, Second group of attribute position 354A-N, the 3rd group of attribute position 356A-N and physical memory address position 358A-N.Therefore first Group attribute position 352A, second group of attribute position 354A, the 3rd group of attribute position 356A and physical memory address position 358A are altogether Constitute together page entry A.First group of attribute position 352B, second group of attribute position 354B, the 3rd group of attribute position 356B and Physical memory address position 358B collectively constitutes page entry B, by that analogy.As discussed above, page entry 356A-N In each can be 32,40 or other size a certain.Physical memory address position 358A-N can be respectively 20 Position or other size a certain, and can be for first group of attribute position 352A-N, second group of attribute position 354A-N and the 3rd group of genus Property position 356A-N in each use all size.

System storage 334 in Fig. 3 represents the physical storage with memory block 134A-N.System storage 334 Can (such as) corresponding to the system storage 230 of system storage 130 or Fig. 2 of Fig. 1.Memory block 134A-N is set Represent non-adjacent piece of memorizer 334, it is meant that the physical memory address of memory block 334A-N can be non-adjacent. The physical address of the one in memory block 334A-N is included in physical memory address by each in page entry A-N In the 358A-N of position.

Page entry A-N in each correspond to virtual memory address.Such as Fig. 1 the first processing unit 110 or When second processing unit 120 processing unit such as grade needs to access system storage, it can use page table 332 to find for void Intend the corresponding physical memory address of storage address.If the (such as) first processing unit 110 needs virtual to deposit specific Memory address is translated as physical memory address, then the first processing unit 110 reads corresponding to described specific virtual memory The page entry of device address.

In this example, it is assumed that page entry A corresponds to particular virtual memory address.Therefore first processing unit 110 can be Read page entry A to determine the corresponding physical memory address being stored in the 358A of physical memory address position.At figure In the example of 3, entry A is mapped to the physical memory address wherein storing blocks of physical memory 334B.Therefore, thing Physical address is stored memory block 334B ground residing in system storage 334 by reason storage address position 358A Side.First attribute position 352A sets first processing unit 110 authority when accessing blocks of physical memory 334B.Citing For, first may determine that whether the first processing unit 110 has the privilege of the reading to memory block 334B.Second Position may determine that whether the first processing unit 110 has the privilege of the write to memory block 334B.

In some cases, the second processing unit 120 can need translate by the first processing unit 110 translate identical specific Virtual memory address.Virtual deposit to this end, the second processing unit 120 can read the first processing unit 110 translation is specific The same page entry corresponding to described particular virtual memory address read during memory address.

In this example, assume again that page entry A is corresponding to described particular virtual memory address.Second processing unit Therefore 120 can read page entry A to determine the corresponding physical memory address being stored in the 358A of physical storage position. In the example of fig. 3, entry A is mapped to blocks of physical memory 334B.Therefore, physical memory address position 358A deposits The physical address of storage memory block 334B.Second attribute position 354A defines the second processing unit 120 in access physical store Authority during device block 334B.For example, first of the second attribute position 356A may determine that the second processing unit 120 Whether there is the privilege of the reading to memory block 334B.The second of the second attribute position 356A may determine that the second process list Whether unit 120 has the privilege of the write to memory block 334B.In this way, though the first processing unit 110 and Two processing units 120 same page entry in accessing identical page table is to be translated as physical storage by virtual memory address Address, the first processing unit 110 and the second processing unit 120 also can have the different privilege to the same memory block, The most different readings and write access.

In another example, the second processing unit 220 or the 3rd at the such as first processing unit 210 or Fig. 2 processes list When the processing units such as the one in unit 240 need to access system storage, it can use page table 332 to find for virtual The corresponding physical memory address of storage address.In this example, the first attribute position 352A-N can define the first process The authority of unit 210, and the second attribute position 354A-N can define the second processing unit 220 and the 3rd processing unit 240 Both authorities.Therefore, when the second processing unit 220 needs the blocks of physical memory accessing memorizer 334, second Attribute position 354A-N defines the authority of the second processing unit 220.Similarly, access is needed at the 3rd processing unit 240 During the blocks of physical memory of memorizer 334, the second attribute position 354A-N also defines the authority of the 3rd processing unit 240.

Fig. 4 shows the virtual flow chart to physical mappings technology described in the present invention.The technology of Fig. 4 can be by using The calculating device (the calculating device 200 calculating device 100 or Fig. 2 of such as Fig. 1) of two or more processing units is held OK.The technology of Fig. 4 will be described with reference to calculating device 100, it should be appreciated that the technology of Fig. 4 is applicable to calculate widely dress Put and be not merely limited to the device being configured as calculating device 100.

First processing unit 110 uses the shared page table being stored in memorizer by virtual memory ground via MMU 112 Location is translated as physical memory address (410).Described shared page table is the first processing unit 110 and the second processing unit 120 Shared and stored the mapping for the virtual memory address of memory block accessed by application to physical memory address. Described application can perform on both the first processing unit 110 and the second processing unit 120.Described shared page table comprises One processing unit 110 and the second processing unit 120 are in order to access the page entry of memory block.Described page entry also comprises boundary Determine the physical address bits of the physical address of memory block.

First processing unit 120 accesses by the memory block (420) of physical memory address identification.Described page entry comprises boundary Fixed first processing unit, first group of attribute position to the accessibility of memory block.Second processing unit 120 uses and is stored in Virtual memory address is translated as physical memory address (430) by the shared page table in described memorizer.In this way, One processing unit 110 and the second processing unit 120 access when virtual memory address is translated as physical memory address Identical shared page table.Second processing unit 120 accesses by the memory block (440) of physical memory address identification.Described Page entry comprises the second group of attribute position defining the second processing unit to the accessibility of the same memory block.At this example In, particular virtual memory address translation is being physical storage by the first processing unit 110 and the second processing unit 120 Access identical page entry during address, but described page entry can be for the first processing unit 110 and the second processing unit 120 There is single attribute position.Described page entry also can comprise and defines the first processing unit 110 and the second processing unit 120 liang 3rd group of attribute position of the attribute that person shares.

In the example in figure 4, the first processing unit 110 can be CPU, and the second processing unit 120 can be GPU.The One group of attribute position can define whether the first processing unit 110 has the write access right to memory block, and defines at first Whether reason unit 110 has the reading access right to memory block.The second processing unit 120 can be defined in second group of attribute position Whether have to write memory block to access and define for the time being whether the second processing unit 120 has the reading to memory block Access right.First processing unit 110 may differ from the second processing unit 120 to memorizer to the accessibility of memory block The accessibility of block.For example, based on described first group of attribute, the first processing unit 110 can have memory block Reading access right and write access right, and based on second group of attribute, the second processing unit 120 has memory block Read-only access right.

First processing unit 110 can comprise a MMU (such as, MMU 112), and the second processing unit 120 can wrap Containing the 2nd MMU (such as, MMU 122).Oneth MMU may be configured to access shared page table, and the 2nd MMU Also can be configured to access described identical shared page table.

The example of system storage 26 is including but not limited to random access memory (RAM), read only memory (ROM), electricity Erasable Programmable Read Only Memory EPROM (EEPROM), CD-ROM or other optical disk storage apparatus, disk storage device or Other magnetic storage device, flash memory, or can be used for carrying or store desired with the form of instruction or data structure Program code and other media any that can be accessed by computer or processor.In some instances, system storage 26 Non-transitory storage media can be considered.Term " non-transitory " may indicate that storage media are not embodied in carrier wave or propagate letter In number.But, term " non-transitory " should not be construed as and means that system storage 26 is immovable.As one Individual example, from device 10 removal system memorizer 26, and can move to another device by system storage 26.As separately One example, the storage device being substantially similar to system storage 26 can be plugged in device 10.In some instances, Non-transitory storage media can store the data (such as, in RAM) that can change over.

In one or more example, described function can be implemented with hardware, software, firmware or its any combination.As The most implemented in software, the most described function can store on computer-readable media as one or more instruction or code or pass Defeated, and performed by hardware based processing unit.Computer-readable media can comprise computer-readable storage medium, It corresponds to tangible medium, such as data storage medium, or includes that computer program is sent to separately at one by any promotion The communication medium of the media (such as, according to communication protocol) at.In this way, computer-readable media typically can be corresponding Tangible computer readable memory medium or (2) such as communication medium such as signal or carrier wave in (1) non-transitory.Data storage matchmaker Body can be can be accessed with retrieval for implementing described in the present invention by one or more computer or one or more processor Any useable medium of the instruction of technology, code and/or data structure.Computer program can comprise computer-readable Media.

For example unrestricted, this type of computer-readable storage medium can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage apparatus, disk storage device or other magnetic storage device, flash memory or available Store in instruction or data structure form desired program code and can be by other matchmaker any of computer access Body.Equally, any connection can properly be referred to as computer-readable media.For example, if using coaxial cable, light Fine cable, twisted-pair feeder, numeral subscriber's line (DSL) or such as the wireless technology such as infrared ray, radio and microwave from website, Server or the instruction of other remote source, then coaxial cable, Connectorized fiber optic cabling, twisted-pair feeder, DSL or such as infrared ray, The wireless technology such as radio and microwave is included in the definition of media.However, it should be understood that computer-readable storage medium and Data storage medium does not comprise connection, carrier wave, signal or other temporary media, but is actually directed to nonvolatile Property tangible storage medium.As used herein, disk and CD comprise compact disk (CD), laser-optical disk, optical compact disks, Digital versatile disc (DVD), floppy discs and Blu-ray Disc, wherein disk the most magnetically reappears data, and Usage of CD-ROM laser reappears data optically.The combination of above-mentioned each also should be included in the scope of computer-readable media In.

Instruction can be performed by one or more processor, at one or more processor described e.g. one or more digital signal Reason device (DSP), general purpose microprocessor, special IC (ASIC), field programmable logic array (FPGA) or other Integrated or the discrete logic of equivalence.Therefore, as used herein, the term " processor " can refer to said structure or It is adapted for carrying out any one in other structure arbitrary of technology described herein.It addition, in certain aspects, this Described in literary composition functional can be configured for coding and decoding specialized hardware and/or software module in provide, or Person is incorporated in combination codec.Further, described technology can be fully implemented in one or more circuit or logic element.

The technology of the present invention may be implemented in extensive multiple device or equipment, comprise wireless handset, integrated circuit (IC) or One group of IC (such as, chipset).Described in the present invention, various assemblies, module or unit are to emphasize to be configured to perform The function aspects of the device of disclosed technology, but be not necessarily required to be realized by different hardware unit.It practice, such as institute the most above Describing, various unit in conjunction with suitable software and/or firmware combinations in coding decoder hardware cell, or can pass through The incompatible offer of collection of interoperability hardware cell, described hardware cell comprises one or more processor as described above.

Have described that various example.These and other example is within the scope of the appended claims.

Claims (24)

1. the equipment mapped for storage address, comprising:

First processing unit, wherein said first processing unit includes central processing unit CPU；

Second processing unit, wherein said second processing unit includes Graphics Processing Unit GPU；And

Memorizer, its storage:

Share described first processing unit in page table and described second processing unit in order to access the page of memory block Entry, wherein said shared page table is shared by described first processing unit and described second processing unit and is stored For the mapping of the virtual memory address of the memory block by the effort access applied to physical memory address, Wherein said page entry includes defining described first processing unit first to the accessibility of described memory block Group attribute position, define described second processing unit to second group of attribute position of the accessibility of the same memory block and Define the physical address bits of the physical address of described memory block in described memorizer, wherein by as described in first Described first processing unit that defines of group attribute position the described accessibility of described memory block is different from as by Described second processing unit that described second group of attribute position the is defined described accessibility to described memory block；

Wherein said first group of attribute position is defined described first processing unit and is had the reading to described memory block and deposit Weighting and write access right, and wherein said second group of attribute position define described second processing unit and have described The read-only access right of memory block.

Equipment the most according to claim 1, wherein said page entry includes defining described first processing unit and described 3rd group of attribute position of the attribute that both two processing units are shared.

Equipment the most according to claim 1, wherein said first processing unit includes first memory administrative unit MMU and described second processing unit include that the 2nd MMU, a wherein said MMU are configured to access institute State shared page table and described 2nd MMU is configured to access described shared page table.

Equipment the most according to claim 1, it farther includes:

First memory administrative unit MMU, wherein said first processing unit includes a described MMU；

3rd processing unit；

Input/output MMU IOMMU, wherein said IOMMU are by described second processing unit and the described 3rd Reason unit is shared；

A wherein said MMU is configured to access described shared page table and described IOMMU is configured to access institute State shared page table.

Equipment the most according to claim 1, wherein said application processes single at described first processing unit and described second Both upper execution of unit.

6. the equipment mapped for storage address, comprising:

First processing unit, wherein said first processing unit includes central processing unit CPU；

Second processing unit, wherein said second processing unit includes Graphics Processing Unit GPU；And

Memorizer, its storage:

Share described first processing unit in page table and described second processing unit in order to access the page of memory block Entry, wherein said shared page table is shared by described first processing unit and described second processing unit and is stored For the mapping of the virtual memory address of the memory block by the effort access applied to physical memory address, Wherein said page entry includes defining described first processing unit first to the accessibility of described memory block Group attribute position, define described second processing unit to second group of attribute position of the accessibility of the same memory block and Define the physical address bits of the physical address of described memory block in described memorizer, wherein by as described in first Described first processing unit that defines of group attribute position the described accessibility of described memory block is different from as by Described second processing unit that described second group of attribute position the is defined described accessibility to described memory block；

Whether wherein said first group of attribute position is defined described first processing unit and is had and write described memory block Enter access right, and define whether described first processing unit has the reading access right to described memory block, and Wherein said second group of attribute position defines whether described second processing unit has the write to described memory block Access defines for the time being whether described second processing unit has the reading access right to described memory block.

7. the method mapped for storage address, comprising:

Used the shared page table being stored in memorizer that virtual memory address is translated as physics by the first processing unit Storage address, wherein said first processing unit includes central processing unit CPU；

By described first processing unit access by the memory block of described physical memory address identification；

Used the described shared page table being stored in described memorizer by described virtual memory ground by the second processing unit Location is translated as described physical memory address, and wherein said second processing unit includes Graphics Processing Unit GPU；

By described second processing unit access by the described memory block of described physical memory address identification；

Wherein said shared page table is shared by described first processing unit and described second processing unit, and storage is used for Mapping by the virtual memory address of the memory block of the effort access applied to physical memory address；And

Wherein said shared page table includes that described first processing unit and described second processing unit are deposited described in accessing The page entry of reservoir block, wherein said page entry include defining described first processing unit to described memory block can First group of attribute position of accessibility, define described second processing unit second to the accessibility of the same memory block Group attribute position and define the physical address bits of physical address of described memory block, wherein by as described in first group of attribute Described first processing unit that defines of position the described accessibility of described memory block is different from by as described in second Described second processing unit that group attribute position the is defined described accessibility to described memory block；And

Wherein based on described first group of attribute, described first processing unit has the reading access right to described memory block And write access right, and wherein based on described second group of attribute, described second processing unit has described memorizer The read-only access right of block.

Method the most according to claim 7, wherein said page entry includes defining described first processing unit and described 3rd group of attribute position of the attribute that both two processing units are shared.

Method the most according to claim 7, wherein said first processing unit includes first memory administrative unit MMU and described second processing unit include that the 2nd MMU, a wherein said MMU are configured to access institute State shared page table and described 2nd MMU is configured to access described shared page table.

Method the most according to claim 7, it farther includes:

Used the described shared page table being stored in described memorizer by the second virtual memory ground by the 3rd processing unit Location is translated as the second physical memory address；

By described 3rd processing unit access by the memory block of described second physical memory address identification；

Wherein said second processing unit and described 3rd processing unit share input/output MMU IOMMU, and its Described in IOMMU be configured to access described shared page table.

11. methods according to claim 7, wherein said application processes single at described first processing unit and described second Both upper execution of unit.

12. 1 kinds of methods mapped for storage address, comprising:

Used the shared page table being stored in memorizer that virtual memory address is translated as physics by the first processing unit Storage address, wherein said first processing unit includes central processing unit CPU；

By described first processing unit access by the memory block of described physical memory address identification；

Used the described shared page table being stored in described memorizer by described virtual memory ground by the second processing unit Location is translated as described physical memory address, and wherein said second processing unit includes Graphics Processing Unit GPU；

By described second processing unit access by the described memory block of described physical memory address identification；

Wherein said shared page table is shared by described first processing unit and described second processing unit, and storage is used for Mapping by the virtual memory address of the memory block of the effort access applied to physical memory address；And

Wherein said shared page table includes that described first processing unit and described second processing unit are deposited described in accessing The page entry of reservoir block,

Wherein said page entry includes defining described first processing unit first to the accessibility of described memory block Group attribute position, define described second processing unit to second group of attribute position of the accessibility of the same memory block and boundary The physical address bits of the physical address of fixed described memory block,

Wherein by as described in first group of attribute position define as described in the first processing unit to as described in can as described in memory block Accessibility be different from by as described in second group of attribute position define as described in the second processing unit to as described in memory block Described accessibility；And

Wherein said first group of attribute position defines whether described first processing unit has the write to described memory block Access right, and define whether described first processing unit has the reading access right to described memory block；And, Wherein said second group of attribute position is defined described second processing unit and whether is had the write to described memory block and deposit Weighting, and define whether described second processing unit has the reading access right to described memory block.

13. 1 kinds of equipment mapped for storage address, comprising:

First processing means；

Second processing means；

Memorizer；

Wherein said first processing means includes

For using the shared page table being stored in described memorizer that virtual memory address is translated as physical store The first device of device address；

For access by the first device of the memory block of described physical memory address identification,

Wherein said first processing means includes central processing unit CPU；

Wherein said second processing means includes

For using the described shared page table being stored in described memorizer to be translated as described virtual memory address Second device of described physical memory address；

For access by the second device of the described memory block of described physical memory address identification,

Wherein said second processing means includes Graphics Processing Unit GPU；

Wherein said shared page table by described first processing means and described second processing means shared and stored for Mapping by the virtual memory address of the memory block of the effort access applied to physical memory address；

Wherein said shared page table includes that described first processing means and described second processing means are deposited described in accessing The page entry of reservoir block, wherein said page entry include defining described first processing means to described memory block can First group of attribute position of accessibility, define described second processing means second to the accessibility of the same memory block Group attribute position and define the physical address bits of physical address of described memory block, wherein by as described in first group of attribute The first processing unit of defining of position the described accessibility of described memory block is different from by as described in second group of genus The second processing unit that property position the is defined described accessibility to described memory block；And

Wherein based on described first group of attribute, described first processing means has the reading access right to described memory block And write access right, and wherein based on described second group of attribute, described second processing means has described memorizer The read-only access right of block.

14. equipment according to claim 13, wherein said page entry includes defining described first processing means and described 3rd group of attribute position of the attribute that both the second processing meanss are shared.

15. equipment according to claim 13, wherein said first processing means includes first memory administrative unit MMU and described second processing means include that the 2nd MMU, a wherein said MMU are configured to access institute State shared page table and described 2nd MMU is configured to access described shared page table.

16. equipment according to claim 13, it farther includes:

3rd processing means, wherein said 3rd processing means includes

For using the described shared page table being stored in described memorizer to be translated as the second virtual memory address The device of the second physical memory address；

For access by the device of the described memory block of described second physical memory address identification.

17. equipment according to claim 13, wherein said application processes in described first processing means and described second Both devices are upper to be performed.

18. 1 kinds of equipment mapped for storage address, comprising:

First processing means；

Second processing means；

Memorizer；

Wherein said first processing means includes

For using the shared page table being stored in described memorizer that virtual memory address is translated as physical store The first device of device address；

For access by the first device of the memory block of described physical memory address identification,

Wherein said first processing means includes central processing unit CPU；

Wherein said second processing means includes

For using the described shared page table being stored in described memorizer to be translated as described virtual memory address Second device of described physical memory address；

For access by the second device of the described memory block of described physical memory address identification,

Wherein said second processing means includes Graphics Processing Unit GPU；

Wherein said shared page table by described first processing means and described second processing means shared and stored for Mapping by the virtual memory address of the memory block of the effort access applied to physical memory address；

Wherein said shared page table includes that described first processing means and described second processing means are deposited described in accessing The page entry of reservoir block,

Wherein said page entry includes defining described first processing means first to the accessibility of described memory block Group attribute position, define described second processing means to second group of attribute position of the accessibility of the same memory block and boundary The physical address bits of the physical address of fixed described memory block,

Wherein by as described in the first processing unit of defining of first group of attribute position to as described in can access as described in memory block Property be different from by as described in the second processing unit of defining of second group of attribute position to as described in can deposit as described in memory block Taking property；And

Wherein said first group of attribute position defines whether described first processing means has the write to described memory block Access right, and define whether described first processing means has the reading access right to described memory block；And, Wherein said second group of attribute position is defined described second processing means and whether is had the write to described memory block and deposit Weighting, and define whether described second processing means has the reading access right to described memory block.

19. 1 kinds of equipment mapped for storage address, comprising:

For being used the shared page table being stored in memorizer to be translated as virtual memory address by the first processing unit The device of physical memory address, wherein said first processing unit includes central processing unit CPU；

For being accessed by the device of the memory block of described physical memory address identification by described first processing unit；

For being used the described shared page table being stored in described memorizer by described virtual memory by the second processing unit Device address translation is the device of described physical memory address, and wherein said second processing unit includes graphics process list Unit GPU；

For being accessed by the dress of the described memory block of described physical memory address identification by described second processing unit Put；

Wherein said shared page table by described first processing unit and described second processing unit shared and stored for Mapping by the virtual memory address of the memory block of the effort access applied to physical memory address；

Wherein said shared page table includes that described first processing unit and described second processing unit are deposited described in accessing The page entry of reservoir block, wherein said page entry include defining described first processing unit to described memory block can First group of attribute position of accessibility, define described second processing unit second to the accessibility of the same memory block Group attribute position and define the physical address bits of physical address of described memory block, wherein by as described in first group of attribute Described first processing unit that defines of position the described accessibility of described memory block is different from by as described in second Described second processing unit that group attribute position the is defined described accessibility to described memory block；And

Wherein based on described first group of attribute, described first processing unit has the reading access right to described memory block And write access right, and wherein based on described second group of attribute, described second processing unit has described memorizer The read-only access right of block.

20. equipment according to claim 19, wherein said page entry includes defining described first processing unit and described 3rd group of attribute position of the attribute that both the second processing units are shared.

21. equipment according to claim 19, wherein said first processing unit includes first memory administrative unit MMU and described second processing unit include that the 2nd MMU, a wherein said MMU are configured to access institute State shared page table and described 2nd MMU is configured to access described shared page table.

22. equipment according to claim 19, it farther includes:

For being used the described shared page table being stored in described memorizer by the second virtual memory by the 3rd processing unit Device address translation is the device of the second physical memory address；

For being accessed by the dress of the memory block of described second physical memory address identification by described 3rd processing unit Put；

Wherein said second processing unit and described 3rd processing unit share input/output MMU IOMMU, and its Described in IOMMU be configured to access described shared page table.

23. equipment according to claim 19, wherein said application processes at described first processing unit and described second Both unit are upper to be performed.

24. 1 kinds of equipment mapped for storage address, comprising:

For being used the shared page table being stored in memorizer to be translated as virtual memory address by the first processing unit The device of physical memory address, wherein said first processing unit includes central processing unit CPU；

For being accessed by the device of the memory block of described physical memory address identification by described first processing unit；

For being used the described shared page table being stored in described memorizer by described virtual memory by the second processing unit Device address translation is the device of described physical memory address, and wherein said second processing unit includes graphics process list Unit GPU；

For being accessed by the dress of the described memory block of described physical memory address identification by described second processing unit Put；

Wherein said shared page table by described first processing unit and described second processing unit shared and stored for Mapping by the virtual memory address of the memory block of the effort access applied to physical memory address；

Wherein said shared page table includes that described first processing unit and described second processing unit are deposited described in accessing The page entry of reservoir block,

Wherein said page entry includes defining described first processing unit first to the accessibility of described memory block Group attribute position, define described second processing unit to second group of attribute position of the accessibility of the same memory block and boundary The physical address bits of the physical address of fixed described memory block,

Wherein by as described in first group of attribute position define as described in the first processing unit to as described in can as described in memory block Accessibility be different from by as described in second group of attribute position define as described in the second processing unit to as described in memory block Described accessibility；And

Wherein said first group of attribute position defines whether described first processing unit has the write to described memory block Access right, and define whether described first processing unit has the reading access right to described memory block；And, Wherein said second group of attribute position is defined described second processing unit and whether is had the write to described memory block and deposit Weighting, and define whether described second processing unit has the reading access right to described memory block.