CN104465427A - Packaging structure and semiconductor process - Google Patents
Packaging structure and semiconductor process Download PDFInfo
- Publication number
- CN104465427A CN104465427A CN201310418550.0A CN201310418550A CN104465427A CN 104465427 A CN104465427 A CN 104465427A CN 201310418550 A CN201310418550 A CN 201310418550A CN 104465427 A CN104465427 A CN 104465427A
- Authority
- CN
- China
- Prior art keywords
- substrate
- conductive junction
- junction point
- crystal grain
- spacer element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
The invention relates to a packaging structure and a semiconductor process. The packaging structure comprises a first substrate, a second substrate, a grain, a plurality of electrical connection elements, at least one spacer element and a sealing compound. The grain is located between the first substrate and the second substrate; the at least one spacer element is arranged between the grain and the second substrate and is in contract with the grain and the second substrate. The electrical connection elements are electrically connected to the first substrate and the second substrate. The at least one spacer element is employed to support the second substrate, allowing a setting distance between the first substrate and the second substrate. The electrical connection elements do not require high intensity materials so as to reduce material cost. The at least one spacer element can control a distance and a space between the grain and the second substrate, allowing the sealing compound to smoothly flow into the space, avoiding generating air or gap in the space and increasing a product yield rate.
Description
Technical field
The invention relates to a kind of encapsulating structure and semiconductor technology.
Background technology
In known package structure, utilize several electrical connection element to be electrically connected two substrates, and in order to keep the distance between two substrates, the electrical connection element of high structural strength (such as: copper) must be utilized to be supported between two substrates, cause material cost to increase.And; when the crystal grain of infrabasal plate and the distance of upper substrate too little time; sealing is difficult to flow into; cause air or the space crystal grain in infrabasal plate and the space of upper substrate; product defect may be produced; such as because the skewness of sealing between crystal grain and upper substrate, cause the mechanical strength of sealing significantly to reduce, reduce the reliability of sealing itself and the sealing bonding strength to crystal grain or upper substrate.
In addition, when utilizing B-stage (B-stage) glue material to be clad material, pressing upper substrate is when this clad material, and because B-stage glue material solidifies not yet completely, therefore the crystal grain of infrabasal plate and the distance of upper substrate are difficult to control, if distance is too large, then electrical connection element cannot contact electrical contact and then can cause short circuit electrically, if when this distance is too little, in the process of pressing upper substrate, this crystal grain may be damaged, cause product yield to decline.
Summary of the invention
The one side of this exposure is about a kind of encapsulating structure.In one embodiment, this encapsulating structure comprises: a first substrate, a second substrate, a crystal grain, several electrical connection element, at least one spacer element and sealing.This first substrate has a first surface and several first conductive junction point, and wherein these first conductive junction points are exposed to this first surface of this first substrate.This second substrate has a second surface and several second conductive junction point, and wherein these second conductive junction points are exposed to this second surface of this second substrate, and this second surface is this first surface in the face of this first substrate.This crystal grain is between this first substrate and this second substrate, and wherein this crystal grain has one the 3rd surface, and the 3rd surface is this second surface in the face of this second substrate, has a clearance space between this second surface and the 3rd surface.These electrical connection element between this first substrate and this second substrate, and with these first conductive junction points and these the second conductive junction point physical bonds and electric connection.This at least one spacer element is arranged at this clearance space, is the first part in this clearance space, and contacts this crystal grain and this second substrate.The part first surface of this first substrate of sealant covers and the portion second surface of this second substrate, the some of wherein this sealing is the Part II in this clearance space.
The another aspect of this exposure is about a kind of semiconductor technology.In one embodiment, this semiconductor technology comprises the following steps: (a) provides a first substrate, and this first substrate has a first surface and several first conductive junction point, and wherein these first conductive junction points are exposed to this first surface of this first substrate; B () arranges a crystal grain in this first surface of this first substrate, wherein this crystal grain has one the 3rd surface; C () provides a second substrate, this second substrate has a second surface and several second conductive junction point, wherein these second conductive junction points are exposed to this second surface of this second substrate, and this second surface is the 3rd surface in the face of this first surface of this first substrate and this crystal grain; D () arranges at least one spacer element between this crystal grain and this second substrate, and several electrical connection element is set between this first substrate and this second substrate, and these electrical connection element and these the first conductive junction points and these the second conductive junction point physical bonds and electric connection, wherein form a clearance space between this second surface and the 3rd surface, this at least one spacer element is the first part in this clearance space, and this at least one spacer element contacts this crystal grain and this second substrate; And (e) injects sealing between this first substrate and this second substrate, the part first surface of this this first substrate of sealant covers and the portion second surface of this second substrate, the some of wherein this sealing is the Part II in this clearance space.
This at least one spacer element is utilized to support this second substrate, make, between this first substrate and this second substrate, there is a setpoint distance, and make these electrical connection element can be solder, and do not need to utilize these electrical connection element to support this second substrate, these electrical connection element must not use the material of high strength, to save material cost.And be arranged between this crystal grain and this second substrate because of this at least one spacer element, the distance between this crystal grain and this second substrate can be controlled, to avoid the distance between this crystal grain and this second substrate too little, make sealing can flow into this clearance space smoothly, therefore air or space can not be produced in this clearance space, can product yield be improved.
The another aspect of this exposure is about a kind of semiconductor technology.In one embodiment, this semiconductor technology comprises the following steps: (a) provides a first substrate, and this first substrate has a first surface and several first conductive junction point, and wherein these first conductive junction points are exposed to this first surface of this first substrate, b () arranges a crystal grain in this first surface of this first substrate, wherein this crystal grain has one the 3rd surface, c () arranges at least one spacer element on this crystal grain, and arrange several electrical connection element on this first substrate, d () applies a clad material this first surface in this first substrate with this crystal grain coated and these electrical connection element, wherein this clad material is B-stage (B-stage) glue material, e () forms several this clad material that is opened on to appear these electrical connection element, f () pressing one second substrate is on this clad material, this second substrate has a second surface and several second conductive junction point, wherein these second conductive junction points are exposed to this second surface of this second substrate, this second surface of this second substrate attaches on this clad material, wherein form a clearance space between this second surface and the 3rd surface, these electrical connection element and these the first conductive junction points and these the second conductive junction point physical bonds and electric connection, this second surface of this second substrate contacts this at least one spacer element, this at least one spacer element is the first part in this clearance space, and a part for this clad material is one second part in this clearance space, and (g) carries out a heating steps, this clad material is made to be solidified into the C stage.
Because at least one spacer element is arranged on this crystal grain, make this second substrate of pressing when this clad material, this second surface of this second substrate contacts this at least one spacer element, to control this second substrate and this intercrystalline distance, avoid in the process of this second substrate of pressing, damage this crystal grain, to improve product yield.
Accompanying drawing explanation
Fig. 1 shows the cross-sectional schematic of an embodiment of encapsulating structure of the present invention;
Fig. 2 shows the schematic diagram that at least one spacer element of the present invention is arranged at an embodiment of crystal grain;
Fig. 3 shows the schematic diagram that at least one spacer element of the present invention is arranged at another embodiment of crystal grain;
Fig. 4 to Fig. 8 shows the schematic diagram of an embodiment of semiconductor technology of the present invention; And
Fig. 9 to Figure 16 shows the schematic diagram of another embodiment of semiconductor technology of the present invention.
Embodiment
With reference to figure 1, show the cross-sectional schematic of an embodiment of encapsulating structure of the present invention.This encapsulating structure 10 comprises: first substrate 11, second substrate 12, crystal grain 13, several electrical connection element 14, at least one spacer element (spacer element) 15 and sealing 16.This first substrate 11 has a first surface 111 and several first conductive junction point 112, and wherein these first conductive junction points 112 are exposed to this first surface 111 of this first substrate 11.In one embodiment, first substrate 11 also comprises the first welding resisting layer (not shown), and the first surface 111 of first substrate 11 is surfaces of the first welding resisting layer, and exposes the first conductive junction point 112 by the opening of the first welding resisting layer.These first conductive junction points 112 can be conductive pad or conducting wire.
This second substrate 12 has a second surface 121 and several second conductive junction point 122, and wherein these second conductive junction points 122 are exposed to this second surface 121 of this second substrate 12, and this second surface 121 is these first surfaces 111 in the face of this first substrate 11.In one embodiment, second substrate 12 also comprises the second welding resisting layer (not shown), and the second surface 121 of second substrate 12 is surfaces of the second welding resisting layer, and exposes the second conductive junction point 122 by the opening of the second welding resisting layer.These second conductive junction points 122 can be conductive pad or conducting wire.
In addition, this first substrate 11 and this second substrate 12 are not such as, containing any active member (as active chip or active lines), a printed circuit board (PCB) (Printed Circuit Board).
This crystal grain 13 is between this first substrate 11 and this second substrate 12, wherein this crystal grain 13 has one the 3rd surface 131,3rd surface 131 is these second surfaces 121 in the face of this second substrate 12, has a clearance space 17 between this second surface 121 and the 3rd surface 131.In the present embodiment, this crystal grain 13 is arranged at this first surface 111 of this first substrate 11, and this crystal grain 13 is electrically connected with this first substrate 11.In one embodiment, crystal grain 13 is located at the first surface 111 of first substrate 11 in orientation down with its active surface, and being electrically connected at first substrate 11 by least one projection (not shown), the juncture of this kind of crystal grain 13 is called and covers crystalline substance (flip chip).
These electrical connection element 14 between this first substrate 11 and this second substrate 12, and with this first conductive junction point 112 and this second conductive junction point 122 physical bonds and electric connection.This at least one spacer element 15 is arranged at this clearance space 17, is the first part in this clearance space 17, and contacts this crystal grain 13 and this second substrate 12.This at least one spacer element 15 can be cemented on this crystal grain 13 or on this second substrate 12, if this at least one spacer element 15 is cemented on this crystal grain 13, then and this second substrate 12 of its tip contact; If this at least one spacer element 15 is cemented on this second substrate 12, then its bottom contacts this crystal grain 13.This at least one spacer element 15 is thermosetting polymer or the fusing point metal higher than electrical connection element, there is this clearance space 17 between the 3rd surface 131 of this second surface 121 and this crystal grain 13 of making this second substrate 12, and utilize this at least one spacer element 15 to support this second substrate 12, also make, between this first substrate 11 and this second substrate 12, there is a setpoint distance, and make these electrical connection element 14 can be solder, and do not need to utilize these electrical connection element 14 to support this second substrate 12, these electrical connection element 14 must not use the material of high strength, to save material cost.
The part first surface 111 of sealing 16 this first substrate 11 coated and the portion second surface 121 of this second substrate 12, wherein the some of this sealing 16 is the Part II in this clearance space 17, that is the part of this sealing 16 flows in this clearance space 17, to fill this clearance space 17 beyond this at least one spacer element 15.And be arranged between this crystal grain 13 and this second substrate 12 because of this at least one spacer element 15, the distance between this crystal grain 13 and this second substrate 12 can be controlled, to avoid the distance between this crystal grain 13 and this second substrate 12 too little, make sealing 16 can flow into this clearance space 17 smoothly, therefore air or space can not be produced in this clearance space 17, can product yield be improved.
Clearance space 17 is between crystal grain 13 and second substrate 12, wherein the distance on the 3rd surface 131 of second surface 121 to the crystal grain 13 of second substrate 12 is the height of clearance space 17, according to one embodiment of the invention, the height of clearance space is 10 microns to 50 microns, the present invention comprises spacer element 15 and sealing 16 in clearance space 17 simultaneously, at least can have effect of above-mentioned spacer element 15 simultaneously, and sealing 16 can bind the surface of crystal grain 13 and second substrate 12, therefore the intensity of encapsulating structure can be strengthened, improve technologic yield, such as in the technique cutting into single encapsulating structure, the stress produced during the cutting of sealing 16 Absorbable rod, therefore the risk peeling off (peeling off) can be reduced between first substrate 11 and second substrate 12.
With reference to figure 2, at least one spacer element of its display the present invention is arranged at the schematic diagram of an embodiment of crystal grain.In the present embodiment, four spacer elements 15 are positioned at four corners on the 3rd surface 131 of this crystal grain 13, and four spacer elements 15 by sealing 16 institute around.Preferably, the total sectional area of four spacer elements 15 is less than 40% of the area on the 3rd surface 131 of this crystal grain 13, can flow into this clearance space 17(with reference to figure 1 to make this sealing 16).The design of four spacer elements 15 dispersibles the pressure to crystal grain in technique.
With reference to figure 3, at least one spacer element of its display the present invention is arranged at the schematic diagram of another embodiment of crystal grain.In the present embodiment, a spacer element 15 is positioned at the center on the 3rd surface 131 of this crystal grain 13, and spacer element 15 by sealing 16 institute around, the design of a spacer element can allow sealing more easily by clearance space 17.
Fig. 4 to Fig. 6 shows the schematic diagram of an embodiment of semiconductor technology of the present invention.With reference to figure 4, provide this first substrate 11, this first substrate 11 has a first surface 111 and several first conductive junction point 112, and wherein these first conductive junction points 112 are exposed to this first surface 111 of this first substrate 11.Then, arrange this crystal grain 13 in this first surface 111 of this first substrate 11, wherein this crystal grain 13 has the 3rd surface 131.
With reference to figure 5, provide this second substrate 12, this second substrate 12 has this second surface 121 and several second conductive junction point 122, and wherein these second conductive junction points 121 are exposed to this second surface 121 of this second substrate 12.Coordinate with reference to figure 4 and Fig. 5, this second surface 121 is down, and the 3rd surface 131 of this first surface 111 of this first substrate 11 and this crystal grain 13 is upward, therefore this second surface 121 is in the face of this first surface 111 of this first substrate 11 and the 3rd surface 131 of this crystal grain 13.
At least one spacer element is set between this crystal grain and this second substrate, and several electrical connection element is set between this first substrate and this second substrate, and these electrical connection element and these the first conductive junction points and these the second conductive junction point physical bonds and electric connection.With reference to figure 6, in the present embodiment, this at least one spacer element 15 is cemented arranges on the 3rd surface 131 of this crystal grain 13; And these electric connection materials 141 are arranged on the first conductive junction point 112 of this first substrate 11.With reference to figure 7, arranging this second substrate 12 is electrically connected on material 141 in this at least one spacer element 15 and these, this at least one spacer element 15 contacts this second substrate 12, these are electrically connected after material 141 engages with these first conductive junction points 112 and engage with these second conductive junction points 122, reflow oven can be used to heat for juncture or hot pressing mode reflow (reflow) forms these electrical connection element 14, and in the present embodiment, these are electrically connected material 141 is solder.Form this clearance space 17 between this second surface 121 and the 3rd surface 131, this at least one spacer element 15 is the first part in this clearance space 17, and this at least one spacer element 15 contacts this crystal grain 13 and this second substrate 12.Because solder in reflow process can soften, now this spacer element 15 maintains the height of clearance space 17, and after making, sealing 16 can flow into this clearance space 17 smoothly, therefore can not produce air or space in this clearance space 17, can improve product yield.
With reference to figure 8, be that display forms at least one spacer element 15 and is electrically connected material in another embodiment of this second substrate 12.In the present embodiment, cemented this second surface 121 that this second substrate 12 is set of this at least one spacer element 15; These are electrically connected the second conductive junction point 122 that material 142 is arranged at this second substrate 12.Then, referring again to Fig. 7, this second substrate 12 is set again on this first substrate 11, this at least one spacer element 15 contacts this crystal grain 13, these are electrically connected after material 142 engages with these second conductive junction points 122 and engage with these first conductive junction points 112, utilize reflow oven heating or the reflow of hot pressing mode to form these electrical connection element 14, these electrical connection element 14 and these first conductive junction points 112 and this second conductive junction point 122 physical bonds and electric connection, in the present embodiment, these are electrically connected material 142 is solder.
Refer again to Fig. 1, inject sealing 16 between this first substrate 11 and this second substrate 12, the part first surface 111 of this sealing 16 this first substrate 11 coated and the portion second surface 121 of this second substrate 12, the some of wherein this sealing 16 is the Part II in this clearance space 17.Then, several lower soldered ball 115 is formed under several first substrates of a lower surface 113 of this first substrate 11 on conductive junction point 114.
Fig. 9 to Figure 16 shows the schematic diagram of another embodiment of semiconductor technology of the present invention.With reference to figure 9, provide a first substrate 21, this first substrate 21 has a first surface 211 and several first conductive junction point 212, and wherein these first conductive junction points 212 are exposed to this first surface 211 of this first substrate 21.
With reference to Figure 10, arrange a crystal grain 22 in this first surface 211 of this first substrate 21, wherein this crystal grain 22 has one the 3rd surface 221.With reference to Figure 11, arrange at least one spacer element 23 on this crystal grain 22, and arrange several first electric connection material 241 on this first substrate 21, in the present embodiment, the first electric connection material 241 is solder.In the present embodiment, this at least one spacer element 23 is cemented is arranged on the 3rd surface 221 of this crystal grain 22.Preferably, four spacer elements 23 are four corners being distributed in this crystal grain 22, and the design of four spacer elements 23 dispersibles the pressure to crystal grain in technique.
With reference to Figure 12, apply the first surface 211 of a clad material 25 in this first substrate 21 with this crystal grain 22 coated and these the first electric connection materials 241, wherein this clad material 25 is B-stage (B-stage) glue material.In the present embodiment, be pressing or print this clad material 25 in this first surface 211 of this first substrate 21.
With reference to Figure 13, forming several opening 251 in this clad material 25 to appear these the first electric conducting materials 241, in the present embodiment, is utilize laser to form these openings 251.With reference to Figure 14, pressing one second substrate 26 is on this clad material 25, this second substrate 26 has a second surface 261, several second conductive junction point 262 and several second is electrically connected material 242, wherein these second conductive junction points 262 are exposed to this second surface 261 of this second substrate 26, this several second electric connection material 242 protrudes from the second surface 261 of second substrate 26, in the present embodiment, second electric connection material 242 is solder, this second surface 261 of this second substrate 26 attaches on this clad material 25, wherein form a clearance space 27 between this second surface 261 and the 3rd surface 221, this second surface 261 of this second substrate 26 contacts this at least one spacer element 23, this at least one spacer element 23 is the first part in this clearance space 27, and a part for this clad material 25 is one second part in this clearance space 27.
With reference to Figure 15, carry out a heating steps, this clad material 25 is made to be solidified into the C stage, and wait this first to be electrically connected material 241 and second to be electrically connected material 242 via reflow process with these and to form these electrical connection element 24, wherein these electrical connection element 24 and this first conductive junction point 212 and this second conductive junction point 262 physical bonds and electric connections.With reference to Figure 16, this first substrate 21 has more conductive junction point 214 under a lower surface 213 and several first substrate, and under these first substrates, conductive junction point 214 is revealed in this first substrate lower surface 213.Form several lower soldered ball 28 under these first substrates on conductive junction point 214.Then, reflow is carried out.Cut again, to form several semiconductor package 20.
Because at least one spacer element 23 is arranged on this crystal grain 22, make this second substrate 26 of pressing when this clad material 25, this second surface 261 of this second substrate 26 contacts this at least one spacer element 23, to control the distance between this second substrate 26 and this crystal grain 22, avoid in the process of this second substrate 26 of pressing, damage this crystal grain 22, to improve product yield.
Only above-described embodiment is only and principle of the present invention and effect thereof is described, and is not used to limit the present invention.Therefore, the personage practised in this technology modifies to above-described embodiment and changes still de-spirit of the present invention.Interest field of the present invention should listed by claims.
Claims (14)
1. an encapsulating structure, is characterized in that, comprising:
One first substrate, have a first surface and several first conductive junction point, wherein said first conductive junction point is exposed to this first surface of this first substrate;
One second substrate, have a second surface and several second conductive junction point, wherein said second conductive junction point is exposed to this second surface of this second substrate, and this second surface is this first surface in the face of this first substrate;
One crystal grain, between this first substrate and this second substrate, wherein this crystal grain has one the 3rd surface, and the 3rd surface is this second surface in the face of this second substrate, has a clearance space between this second surface and the 3rd surface;
Several electrical connection element, between this first substrate and this second substrate, and with described first conductive junction point and described second conductive junction point physical bonds and electric connection;
At least one spacer element, is arranged at this clearance space, is the first part in this clearance space, and contacts this crystal grain and this second substrate; And
Sealing, the part first surface of this first substrate coated and the portion second surface of this second substrate, the some of wherein this sealing is the Part II in this clearance space.
2. encapsulating structure as claimed in claim 1, is characterized in that, this at least one spacer element cemented on this crystal grain or on this second substrate both one of, and contact should both another.
3. encapsulating structure as claimed in claim 1, is characterized in that, this at least one spacer element is thermosetting polymer or the fusing point metal higher than described electrical connection element.
4. encapsulating structure as claimed in claim 1, it is characterized in that, the total sectional area of this at least one spacer element is less than 40% of the area on the 3rd surface of this crystal grain.
5. encapsulating structure as claimed in claim 1, it is characterized in that, this at least one spacer element is positioned at the center on the 3rd surface or four corners on the 3rd surface.
6. encapsulating structure as claimed in claim 1, it is characterized in that, described electrical connection element is solder.
7. a semiconductor technology, is characterized in that, comprises the following steps:
A () provides a first substrate, this first substrate has a first surface and several first conductive junction point, and wherein said first conductive junction point is exposed to this first surface of this first substrate;
B () arranges a crystal grain in this first surface of this first substrate, wherein this crystal grain has one the 3rd surface;
C () provides a second substrate, this second substrate has a second surface and several second conductive junction point, wherein said second conductive junction point is exposed to this second surface of this second substrate, and this second surface is the 3rd surface in the face of this first surface of this first substrate and this crystal grain;
D () arranges at least one spacer element between this crystal grain and this second substrate, and several electrical connection element is set between this first substrate and this second substrate, and described electrical connection element and described first conductive junction point and described second conductive junction point physical bonds and electric connection, wherein form a clearance space between this second surface and the 3rd surface, this at least one spacer element is the first part in this clearance space, and this at least one spacer element contacts this crystal grain and this second substrate; And
E () injects sealing between this first substrate and this second substrate, the part first surface of this this first substrate of sealant covers and the portion second surface of this second substrate, the some of wherein this sealing is the Part II in this clearance space.
8. semiconductor technology as claimed in claim 7, is characterized in that, in step (d), this at least one spacer element is cemented arranges the 3rd of this crystal grain the on the surface, and contacts this second substrate; Several electric connection material is set on described first conductive junction point of this first substrate, described electric connection material engages with described second conductive junction point after engaging with described first conductive junction point again, be utilize reflow oven heating or the reflow of hot pressing mode to form described electrical connection element, described electric connection material is solder.
9. semiconductor technology as claimed in claim 7, is characterized in that, in step (d), and cemented this second surface that this second substrate is set of this at least one spacer element, and contact this crystal grain; Several electric connection material is set on described second conductive junction point of this second substrate, described electric connection material engages with described first conductive junction point after engaging with described second conductive junction point again, be utilize reflow oven heating or the reflow of hot pressing mode to form described electrical connection element, described electric connection material is solder.
10. a semiconductor technology, is characterized in that, comprises the following steps:
A () provides a first substrate, this first substrate has a first surface and several first conductive junction point, and wherein said first conductive junction point is exposed to this first surface of this first substrate;
B () arranges a crystal grain in this first surface of this first substrate, wherein this crystal grain has one the 3rd surface;
C () arranges at least one spacer element on this crystal grain, and form several electric connection material on this first substrate;
D () applies a clad material this first surface in this first substrate with this crystal grain coated and described electric connection material, wherein this clad material is B-stage glue material;
E () forms several this clad material that is opened on to appear described electric connection material;
F () pressing one second substrate is on this clad material, this second substrate has a second surface and several second conductive junction point, wherein said second conductive junction point is exposed to this second surface of this second substrate, this second surface of this second substrate attaches on this clad material, wherein form a clearance space between this second surface and the 3rd surface, this second surface of this second substrate contacts this at least one spacer element, this at least one spacer element is the first part in this clearance space, and a part for this clad material is one second part in this clearance space, and
G () carries out a heating steps, this clad material is made to be solidified into the C stage, and described electric connection material forms several electrical connection element, described electrical connection element and described first conductive junction point and described second conductive junction point physical bonds and electric connection.
11., as the semiconductor technology of claim 10, is characterized in that, in step (a), this first substrate has more conductive junction point under a lower surface and several first substrate, and under described first substrate, conductive junction point is revealed in this first substrate lower surface; More comprise after step (g):
H () forms several lower soldered ball under described first substrate on conductive junction point;
I () carries out reflow; And
J () cuts, to form several semiconductor package.
12., as the semiconductor technology of claim 10, is characterized in that, in step (c), this at least one spacer element is cemented arranges the 3rd of this crystal grain the on the surface.
13. as the semiconductor technology of claim 10, and it is characterized in that, in step (c), this at least one spacer element is four corners being distributed in this crystal grain.
14. as the semiconductor technology of claim 10, and it is characterized in that, step (d) is pressing or prints this clad material in this first surface of this first substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310418550.0A CN104465427B (en) | 2013-09-13 | 2013-09-13 | Encapsulating structure and semiconductor technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310418550.0A CN104465427B (en) | 2013-09-13 | 2013-09-13 | Encapsulating structure and semiconductor technology |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104465427A true CN104465427A (en) | 2015-03-25 |
| CN104465427B CN104465427B (en) | 2018-08-03 |
Family
ID=52911279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310418550.0A Active CN104465427B (en) | 2013-09-13 | 2013-09-13 | Encapsulating structure and semiconductor technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104465427B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106558574A (en) * | 2016-11-18 | 2017-04-05 | 华为技术有限公司 | Chip-packaging structure and method |
| US9947642B2 (en) | 2015-10-02 | 2018-04-17 | Qualcomm Incorporated | Package-on-Package (PoP) device comprising a gap controller between integrated circuit (IC) packages |
| US10163871B2 (en) | 2015-10-02 | 2018-12-25 | Qualcomm Incorporated | Integrated device comprising embedded package on package (PoP) device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1661814A (en) * | 2004-02-27 | 2005-08-31 | 矽品精密工业股份有限公司 | Package of possessing support piece for packing light sensitive semiconductor |
| US20090273698A1 (en) * | 2008-05-02 | 2009-11-05 | Chi-Hsing Hsu | Image-sensing chip package module for reducing its whole thickness |
| US20110084405A1 (en) * | 2005-08-31 | 2011-04-14 | Canon Kabushiki Kaisha | Stacking semiconductor device and production method thereof |
| US8405230B2 (en) * | 2004-11-17 | 2013-03-26 | Stats Chippac Ltd. | Semiconductor flip chip package having substantially non-collapsible spacer and method of manufacture thereof |
-
2013
- 2013-09-13 CN CN201310418550.0A patent/CN104465427B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1661814A (en) * | 2004-02-27 | 2005-08-31 | 矽品精密工业股份有限公司 | Package of possessing support piece for packing light sensitive semiconductor |
| US8405230B2 (en) * | 2004-11-17 | 2013-03-26 | Stats Chippac Ltd. | Semiconductor flip chip package having substantially non-collapsible spacer and method of manufacture thereof |
| US20110084405A1 (en) * | 2005-08-31 | 2011-04-14 | Canon Kabushiki Kaisha | Stacking semiconductor device and production method thereof |
| US20090273698A1 (en) * | 2008-05-02 | 2009-11-05 | Chi-Hsing Hsu | Image-sensing chip package module for reducing its whole thickness |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9947642B2 (en) | 2015-10-02 | 2018-04-17 | Qualcomm Incorporated | Package-on-Package (PoP) device comprising a gap controller between integrated circuit (IC) packages |
| US10163871B2 (en) | 2015-10-02 | 2018-12-25 | Qualcomm Incorporated | Integrated device comprising embedded package on package (PoP) device |
| US10510733B2 (en) | 2015-10-02 | 2019-12-17 | Qualcomm Incorporated | Integrated device comprising embedded package on package (PoP) device |
| CN106558574A (en) * | 2016-11-18 | 2017-04-05 | 华为技术有限公司 | Chip-packaging structure and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104465427B (en) | 2018-08-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10879203B2 (en) | Stud bump structure for semiconductor package assemblies | |
| CN102446882B (en) | Semiconductor PiP (package in package) system structure and manufacturing method thereof | |
| CN103107272B (en) | The manufacture method of substrate, light-emitting device and substrate | |
| CN102543937B (en) | Flip chip on-chip package and manufacturing method thereof | |
| US9520374B2 (en) | Semiconductor device, substrate and semiconductor device manufacturing method | |
| JP2012009782A (en) | Method for manufacturing semiconductor package | |
| KR20120079325A (en) | Semiconductor package and methods of fabricating the same | |
| JP5881829B2 (en) | Method for packaging quad flat no-lead package body and package body | |
| JP2015188004A (en) | Package, semiconductor device, and semiconductor module | |
| CN104465427A (en) | Packaging structure and semiconductor process | |
| CN102208358A (en) | Method for soldering flip chip on base plate and packaging apparatus | |
| JP2009049248A (en) | Semiconductor device, and its manufacturing method | |
| US11145617B2 (en) | Semiconductor structure | |
| JP5560713B2 (en) | Electronic component mounting method, etc. | |
| JP4777692B2 (en) | Semiconductor device | |
| JP2009266972A (en) | Laminated semiconductor module and method of manufacturing the same | |
| JP2013110188A (en) | Semiconductor device and manufacturing method of the same | |
| JP2009099816A (en) | Semiconductor device, method of manufacturing the same and mounting method of semiconductor device | |
| JP2008270303A (en) | Multilayer semiconductor device | |
| JP4324773B2 (en) | Manufacturing method of semiconductor device | |
| CN102751203A (en) | Semiconductor encapsulation structure and manufacture method of semiconductor encapsulation structure | |
| JP4591715B2 (en) | Manufacturing method of semiconductor device | |
| CN202495443U (en) | Flip chip on chip packaging | |
| JP2005340451A (en) | Semiconductor device, its manufacturing method, circuit board, and electronic apparatus | |
| CN104347532A (en) | Semiconductor packaging piece and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |