CN104425486A - Double-spliced capacitor and manufacturing method thereof - Google Patents
Double-spliced capacitor and manufacturing method thereof Download PDFInfo
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- CN104425486A CN104425486A CN201310390259.7A CN201310390259A CN104425486A CN 104425486 A CN104425486 A CN 104425486A CN 201310390259 A CN201310390259 A CN 201310390259A CN 104425486 A CN104425486 A CN 104425486A
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Abstract
The application discloses a double-spliced capacitor. First silicon oxide is arranged on a heavily doped silicon substrate, silicon nitride is arranged on the first silicon oxide and second silicon oxide is arranged on part of the silicon nitride. Metal of a first portion is located above the silicon nitride. Metal of a second portion is located above the second silicon oxide. The heavily doped silicon substrate is used as a capacitor lower polar plate, the metal of the first portion is used as a capacitor upper polar plate, the total of the first silicon oxide and the silicon nitride is used as medium between the two polar plate, and thus a first capacitor region is formed. The heavily doped silicon substrate is used as a capacitor lower polar plate, the metal of the second portion is used as a capacitor upper polar plate, the total of the first silicon oxide and the silicon nitride is used as medium between the two polar plates and thus a second capacitor region is formed. The application further discloses a manufacturing method of the double-spliced capacitor. The double-spliced capacitor disclosed by the application can facilitate the improvement of the capacitor quality factor and can reduce the area of a device. The manufacturing process of the double-spliced capacitor is simplified and the cost is reduced.
Description
Technical field
The application relates to a kind of semiconductor device, particularly relates to a kind of Two bors d's oeuveres electric capacity.
Background technology
Two bors d's oeuveres electric capacity refers to a kind of semiconductor device with two capacitor area, and these two capacitor area have different capacitance densities.Capacitance density (capacitance density) refers to the capacitance of unit are.Two bors d's oeuveres electric capacity may be used for radio frequency LDMOS(laterally diffused MOS transistor) the interior coupling of device package, utilize multistage coupling to promote the output impedance of radio frequency LDMOS device.
Refer to Fig. 1, this is a kind of device architecture of existing Two bors d's oeuveres electric capacity.Heavily doped silicon substrate 1 has one deck first medium 2, first medium 2 has one deck second medium 3.There is the first metal 4 in second medium 3, contact with the upper surface of first medium 2 bottom it.In second medium 3, on the first metal 4, there is contact hole electrode 5, to contact with the upper surface of the first metal 4 bottom it.Second medium 3 has the second metal 6 that two parts are separate.Wherein the second metal 6 of Part I is directly over the first metal 4, and its bottom surface contacts with the end face of second medium 3, the end face of contact hole electrode 5 simultaneously.The below of the second metal 6 of Part II only has second medium 3, first medium 2 and heavy doping substrate 1, and its bottom surface only contacts with the end face of second medium 3.
In existing Two bors d's oeuveres electric capacity shown in Fig. 1, the region in vertical direction with the first metal 4 is called the first capacitor area.Second metal 6 of the part that namely the second metal 6(in vertical direction with Part II is not electrically connected with the first metal 4) region be called the second capacitor area.First capacitor area as electric capacity bottom crown, by the first metal 4 as electric capacity top crown, constitutes a plate condenser by first medium 2 as medium between two-plate by heavily doped silicon substrate 1.Second capacitor area as electric capacity bottom crown, by the second metal 6 as electric capacity top crown, constitutes a plate condenser by the summation of first medium 2 and second medium 3 as medium between two-plate by heavily doped silicon substrate 1.Due to two plate condensers two-plate between the thickness of medium inevitable different, material also may be different, and make the first capacitor area and the second capacitor area have different capacitance densities.
The manufacture method of existing Two bors d's oeuveres electric capacity comprises the steps:
1st step, refers to Fig. 2 a, deposit one deck first medium 2 on heavily doped silicon substrate 1, such as, be silica.
2nd step, refers to Fig. 2 b, first deposit one deck first metal 4 on first medium 2, then is got rid of by the first metal 4 of part by photoetching and etching technics.
3rd step, refers to Fig. 2 c, deposit second medium 3 on first medium 2 and the first metal 4, such as, be silica.
4th step, refers to Fig. 2 d, and adopt photoetching and etching technics to form one or more through hole on the first metal 4, the bottom of these through holes is the upper surface of the first metal 4.Then in these through holes, form the contact hole electrode 5 of metal material, such as, adopt tungsten plug technique.
5th step, refers to Fig. 1, first deposit one deck second metal 6, and then adopt photoetching and etching technics to be got rid of by the second metal 6 of part, remaining second metal 6 is separate two parts.Wherein the second metal 6 of Part I is directly over the first metal 4, and both are electrically connected by contact hole electrode 5, and this is the first capacitor area.Second metal 6 of Part II is only directly over second medium 3, first medium 2 and heavy doping substrate 1, and this is the second capacitor area.
In existing Two bors d's oeuveres electric capacity, first medium 2 and second medium 3 all adopt silica usually, and this makes the inter-level dielectric of two capacitor area be silica.The dielectric constant of silica is comparatively large, and using it as medium between the two-plate of capacity plate antenna, the area of capacity plate antenna will be made comparatively large, and energy loss is also comparatively large, and this is unfavorable for the lifting of electric capacity quality factor (qualityfactor).Existing Two bors d's oeuveres electric capacity have employed double layer of metal, and has three lithography steps (thus needing three lithography mask versions), and this makes its manufacturing process comparatively complicated and cost is higher.
Summary of the invention
Technical problems to be solved in this application are to provide a kind of Two bors d's oeuveres electric capacity of new structure, and its structure is comparatively simple.For this reason, the application also will provide the manufacture method of this Two bors d's oeuveres electric capacity.
For solving the problems of the technologies described above, the application's Two bors d's oeuveres electric capacity is on heavily doped silicon substrate, have one deck first silica, and the first silica has one deck silicon nitride, and the silicon nitride of part has the second silica; The metal of Part I is on silicon nitride, and its bottom surface only contacts with the end face of silicon nitride; The metal of Part II is on the second silica, and its bottom surface only contacts with the end face of the second silica;
By heavily doped silicon substrate as electric capacity bottom crown, by the metal of Part I as electric capacity top crown, by the summation of the first silica and silicon nitride as medium between two-plate, just constitute the first capacitor area;
By heavily doped silicon substrate as electric capacity bottom crown, by the metal of Part II as electric capacity top crown, by the summation of the first silica and silicon nitride and the second silica as medium between two-plate, just constitute the second capacitor area.
The manufacture method of the application's Two bors d's oeuveres electric capacity comprises the steps:
1st step, deposit first silica on heavily doped silicon substrate;
2nd step, deposit one deck silicon nitride on the first silica;
3rd step, deposit one deck second silica on silicon nitride layer;
4th step, adopts photoetching and etching technics to be got rid of by the second silica of part;
5th step, first deposit layer of metal, then adopts photoetching and etching technics to be fallen by the metal removal of part, and only retains separate two parts metal; The metal of Part I directly contacts the upper surface of silicon nitride, and this is the first capacitor area; The metal of Part II directly contacts the upper surface of the second silica, and this is the second capacitor area.
The Two bors d's oeuveres electric capacity of the application is conducive to the lifting of electric capacity quality factor, and can reduction of device area.Its manufacturing process is simplified and cost reduces.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing Two bors d's oeuveres electric capacity;
Fig. 2 a ~ Fig. 2 d is each step schematic diagram of the manufacture method of existing Two bors d's oeuveres electric capacity;
Fig. 3 is the structural representation of the Two bors d's oeuveres electric capacity of the application;
Fig. 4 a ~ Fig. 4 d is each step schematic diagram of the manufacture method of the Two bors d's oeuveres electric capacity of the application.
Description of reference numerals in figure:
1 attaches most importance to doped silicon substrate; 2 is first medium; 3 is second medium; 4 is the first metal; 5 is contact hole electrode; 6 is the second metal; 71 is the first silica; 72 is silicon nitride; 73 is the second silica; 8 is metal.
Embodiment
Refer to Fig. 3, the device architecture of the Two bors d's oeuveres electric capacity of the application is: on heavily doped silicon substrate 1, have one deck first silica 71, and the first silica 71 has one deck silicon nitride 72.The silicon nitride 72 of part has the second silica 73.First silica 71, silicon nitride 72, second silica 73 constitute ONO(oxidenitride oxide in vertical direction) layer.The metal 8 of Part I is on silicon nitride 72, and its bottom surface only contacts with the end face of silicon nitride 72.The metal 8 of Part II is on the second silica 73, and its bottom surface only contacts with the end face of the second silica 73.
In the Two bors d's oeuveres electric capacity of the application shown in Fig. 3, namely the metal 8(in vertical direction with Part I is positioned at the metal 8 on silicon nitride 72) region be called the first capacitor area.Namely the metal 8(in vertical direction with Part II is positioned at the metal 8 on the second silica 73) region be called the second capacitor area.First capacitor area as electric capacity bottom crown, by the metal 8 of Part I as electric capacity top crown, constitutes a plate condenser by the summation of the first silica 71 and silicon nitride 72 as medium between two-plate by heavily doped silicon substrate 1.Second capacitor area as electric capacity bottom crown, by the metal 8 of Part II as electric capacity top crown, constitutes a plate condenser by ONO layer as medium between two-plate by heavily doped silicon substrate 1.Due to two plate condensers two-plate between the material of medium all different with thickness, and make the first capacitor area and the second capacitor area have different capacitance densities.The capacitance density of the first capacitor area obtains by regulating the thickness of the first silica 71 and/or silicon nitride 72.The capacitance density of the second capacitor area obtains by regulating the thickness of the first silica 71, silicon nitride 72 and/or the second silica 73.
The manufacture method of the Two bors d's oeuveres electric capacity of the application comprises the steps:
1st step, refers to Fig. 4 a, and deposit one deck first silica 71 on heavily doped silicon substrate 1, its thickness is such as 0.6 ~ 2 μm.
2nd step, refers to Fig. 4 b, and deposit one deck silicon nitride 72 on the first silica 71, its thickness is such as 0.3 ~ 1 μm.
3rd step, refers to Fig. 4 c, and deposit one deck second silica 73 on silicon nitride 72, its thickness is such as 0.6 ~ 2 μm.The first silica 71 now, silicon nitride 72, second silica 73 just constitute the structure of ONO layer.
4th step, refers to Fig. 4 d, adopts photoetching and etching technics to be got rid of by the second silica 73 of part, and exposes the silicon nitride 72 of part.
5th step, refers to Fig. 3, first deposit layer of metal 8, and its thickness is such as 0.5 ~ 3 μm.Then adopt photoetching and etching technics to be got rid of by the metal 8 of part, and only retain separate two parts metal 8.Wherein, the metal 8 of Part I directly contacts the upper surface of silicon nitride 72, and this is the first capacitor area.The metal 8 of Part II directly contacts the upper surface of the second silica 73, and this is the second capacitor area.
ONO layer is newly introduced in the Two bors d's oeuveres electric capacity of the application, the inter-level dielectric of first capacitor area is two sublayers below this ONO layer, the inter-level dielectric of second capacitor area is three sublayers of this ONO layer, and this makes medium between the two-plate of two capacitor area be the combination of silica and silicon nitride.Because the dielectric constant of silicon nitride is greater than silica, therefore can improve capacitance under equal area, can reduce capacity area under identical capacitance values, this can reduce energy loss, thus is conducive to the lifting of electric capacity quality factor.The Two bors d's oeuveres electric capacity of the application use only layer of metal, and only has two lithography steps (thus only needing two lithography mask versions), and its manufacturing process is simplified for this and cost reduces.In addition, the silicon nitride 72 of ONO layer intermediate part-layer as the etching stop layer of sublayer second silica 73 above, can This further reduces process complexity.
These are only the preferred embodiment of the application, and be not used in restriction the application.For a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (7)
1. a Two bors d's oeuveres electric capacity, is characterized in that, heavily doped silicon substrate has one deck first silica, the first silica has one deck silicon nitride, and the silicon nitride of part has the second silica; The metal of Part I is on silicon nitride, and its bottom surface only contacts with the end face of silicon nitride; The metal of Part II is on the second silica, and its bottom surface only contacts with the end face of the second silica;
By heavily doped silicon substrate as electric capacity bottom crown, by the metal of Part I as electric capacity top crown, by the summation of the first silica and silicon nitride as medium between two-plate, just constitute the first capacitor area;
By heavily doped silicon substrate as electric capacity bottom crown, by the metal of Part II as electric capacity top crown, by the summation of the first silica and silicon nitride and the second silica as medium between two-plate, just constitute the second capacitor area.
2. Two bors d's oeuveres electric capacity according to claim 1, is characterized in that, the first silica, silicon nitride, the second silica constitute ONO layer.
3. a manufacture method for Two bors d's oeuveres electric capacity, is characterized in that, comprises the steps:
1st step, deposit first silica on heavily doped silicon substrate;
2nd step, deposit one deck silicon nitride on the first silica;
3rd step, deposit one deck second silica on silicon nitride layer;
4th step, adopts photoetching and etching technics to be got rid of by the second silica of part;
5th step, first deposit layer of metal, then adopts photoetching and etching technics to be fallen by the metal removal of part, and only retains separate two parts metal; The metal of Part I directly contacts the upper surface of silicon nitride, and this is the first capacitor area; The metal of Part II directly contacts the upper surface of the second silica, and this is the second capacitor area.
4. the manufacture method of Two bors d's oeuveres electric capacity according to claim 3, is characterized in that, in described method the 1st step, the thickness of the first silica is 0.6 ~ 2 μm.
5. the manufacture method of Two bors d's oeuveres electric capacity according to claim 3, is characterized in that, in described method the 2nd step, the thickness of silicon nitride is 0.3 ~ 1 μm.
6. the manufacture method of Two bors d's oeuveres electric capacity according to claim 3, is characterized in that, in described method the 3rd step, the thickness of the second silica is 0.6 ~ 2 μm.
7. the manufacture method of Two bors d's oeuveres electric capacity according to claim 3, is characterized in that, in described method the 5th step, the thickness of metal is 0.5 ~ 3 μm.
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| CN201310390259.7A CN104425486A (en) | 2013-08-30 | 2013-08-30 | Double-spliced capacitor and manufacturing method thereof |
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| CN201310390259.7A CN104425486A (en) | 2013-08-30 | 2013-08-30 | Double-spliced capacitor and manufacturing method thereof |
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Citations (8)
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| EP0893831A1 (en) * | 1997-07-23 | 1999-01-27 | STMicroelectronics S.r.l. | High voltage capacitor |
| KR20020045270A (en) * | 2000-12-08 | 2002-06-19 | 박종섭 | Method of manufacturing a capacitor in a semiconductor device |
| EP1359607A2 (en) * | 2002-04-25 | 2003-11-05 | Chartered Semiconductor Manufacturing Pte Ltd. | Adjustable 3D capacitor and method of manufacture |
| CN1485889A (en) * | 2002-09-24 | 2004-03-31 | 茂德科技股份有限公司 | Manufacturing method of dielectric layer |
| US20040248359A1 (en) * | 2002-10-28 | 2004-12-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US20070001261A1 (en) * | 2005-07-04 | 2007-01-04 | Koichi Tanaka | Substrate and manufacturing method thereof |
| US20070034989A1 (en) * | 2004-07-15 | 2007-02-15 | Fujitsu Limited | Capacitive element, method of manufacture of the same, and semiconductor device |
| CN101312011A (en) * | 2007-05-24 | 2008-11-26 | 统宝光电股份有限公司 | Image display system |
-
2013
- 2013-08-30 CN CN201310390259.7A patent/CN104425486A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0893831A1 (en) * | 1997-07-23 | 1999-01-27 | STMicroelectronics S.r.l. | High voltage capacitor |
| KR20020045270A (en) * | 2000-12-08 | 2002-06-19 | 박종섭 | Method of manufacturing a capacitor in a semiconductor device |
| EP1359607A2 (en) * | 2002-04-25 | 2003-11-05 | Chartered Semiconductor Manufacturing Pte Ltd. | Adjustable 3D capacitor and method of manufacture |
| CN1485889A (en) * | 2002-09-24 | 2004-03-31 | 茂德科技股份有限公司 | Manufacturing method of dielectric layer |
| US20040248359A1 (en) * | 2002-10-28 | 2004-12-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US20070034989A1 (en) * | 2004-07-15 | 2007-02-15 | Fujitsu Limited | Capacitive element, method of manufacture of the same, and semiconductor device |
| US20070001261A1 (en) * | 2005-07-04 | 2007-01-04 | Koichi Tanaka | Substrate and manufacturing method thereof |
| CN101312011A (en) * | 2007-05-24 | 2008-11-26 | 统宝光电股份有限公司 | Image display system |
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Application publication date: 20150318 |
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