CN104425448B - A kind of anti-fuse structures - Google Patents
A kind of anti-fuse structures Download PDFInfo
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- CN104425448B CN104425448B CN201310410836.4A CN201310410836A CN104425448B CN 104425448 B CN104425448 B CN 104425448B CN 201310410836 A CN201310410836 A CN 201310410836A CN 104425448 B CN104425448 B CN 104425448B
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Abstract
The present invention relates to a kind of anti-fuse structures, comprising: NMOS transistor, the channel length of edge is greater than the channel length at center in the NMOS transistor；Programming transistor, the source region in the NMOS transistor are connected with the programming transistor, and the drain region in the NMOS transistor is connected with programming power supply.Anti-fuse structures of the present invention include a MOS transistor, the channel length of marginal portion is greater than the length of the channel of central part in the MOS transistor, accordingly, the critical size at both ends is greater than the critical size at intermediate position in the gate structure, after applying program voltage on the drain region and programming transistor when the anti-fuse structures program, cause the breakdown of source region and drain region, forms access, play the role of antifuse.
Description
Technical field
The present invention relates to semiconductor fields, in particular it relates to a kind of anti-fuse structures.
Background technique
With the continuous development of semiconductor technology, antifuse (Anti-fuse) technology has attracted many inventors, collection
At the significant concern of circuit (integrated circuits, IC) designer and manufacturer.Antifuse is that conductive shape can be changed
The structure of state, or, in other words, antifuse is the electronic device that never conduction state changes into conduction state.Equally, two
First state can be in response to any one of the high resistance of electric stress (such as program voltage or program current) and low resistance.It is anti-molten
Silk device can be disposed in storage array, and generally known One Time Programmable (OTP) memory is consequently formed.
The programmable chip technology of antifuse (Anti-fuse) provides the conductive path between stable and transistor
Diameter, for the molten link method of conventional fuse (blowing fuses), anti-fuse technology is a kind of novel electricity
Device is learned, antifuse most starts have very high resistance, is in an off state, but electric when applying on the anti-fuse structures
Pressure, when voltage is more than that the anti-fuse structures described to a certain degree form permanent access.
Anti-fuse structures are widely used in the integrated circuit of permanent programming (permanently program)
In (integrated circuits, IC), such as certain programming drain device (Certain programmable logic
Devices), special purpose and design integrated circuit (Application Specific Integrated Circuit,
ASIC), the design of the logic circuit and IC design one customization of creation from a standard that are configured using anti-fuse structures, instead
Fuse-wires structure can be used in program read-only memory (programmable read-only memory, PROM).
The structure of antifuse (Anti-fuse) is as seen in figure la and lb in the prior art, wherein on the substrate 101
The interlayer structure of metal layer 102- dielectric layer 103- metal layer 104 is formed, wherein the dielectric layer is amorphous silicon
(amorphous silicon) carries out the sequencing of grid array using the antifuse, wherein as shown in Figure 1a, when in institute
It states when not applying voltage on anti-fuse structures, the middle dielectric layer is in "off" state, and the dielectric layer is non-conductive at this time,
When applying voltage on the fuse-wires structure, the dielectric layer amorphous silicon (amorphous silicon) becomes polysilicon
(polysilicon), it is in conduction state, the antifuse is in "open" state, as shown in Figure 1 b, carries out antifuse with this
Sequencing.Another anti-fuse structures, middle layer select metal alloy, such as tungsten alloy, titanium alloy and siliceous conjunction
Gold.
Anti-fuse structures are used widely in integrated circuits, but the long-time stability of anti-fuse structures become anti-molten
One major issue of silk structure, because with the extension of time, the anti-fuse structures have the tendency that performance degradation.
Therefore, although anti-fuse technology is widely developed and applies in semiconductor technology, with semiconductor
How the continuous development of technology and the continuous diminution of device size guarantee that the anti-fuse structures have good in a long time
Stability become problem to be solved, all there is described problem in various anti-fuse structures in the prior art, currently without
It is well solved, needs to be improved further the structure of antifuse, to eliminate the above problem.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention is in order to overcome the problems, such as that presently, there are provide a kind of anti-fuse structures, comprising:
NMOS transistor, the channel length of edge is greater than the channel length at center in the NMOS transistor；
Programming transistor, the source region in the NMOS transistor are connected with the programming transistor, the NMOS transistor
In drain region with programming power supply be connected.
Preferably, the grid of the NMOS transistor and body area are floating.
Preferably, the grid and source region of the NMOS transistor are connected to the programming transistor, the NMOS crystal
The area Guan Ti is floating.
Preferably, the grid of the NMOS transistor, source region and body area are connected to the programming transistor.
Preferably, the NMOS transistor includes:
Semiconductor substrate；
Gate structure is located in the semiconductor substrate, during the length of the channel below the gate structure both ends is greater than
Between channel length；
Source region and drain region are located at the two sides of the gate structure, and the source region is connected with programming transistor, the drain region with
Power supply is programmed to be connected.
Preferably, the critical size at the both ends of the gate structure is greater than intermediate critical size.
Preferably, the anti-fuse structures further include the LDD doped region being only located on the inside of the drain region.
Preferably, the anti-fuse structures further include the LDD doped region being located on the inside of the source region and are located at described
LDD doped region on the inside of drain region.
Preferably, the semiconductor substrate is P-type semiconductor substrate.
Preferably, being formed with p-well in the P-type semiconductor substrate, the anti-fuse structures are set in the p-well.
Preferably, the source region and the drain region are n-type doping.
Preferably, the anti-fuse structures further include P-doped zone, the P-doped zone is located in the p-well.
Preferably, the P-doped zone is connected with the programming transistor.
Anti-fuse structures of the present invention include a MOS transistor, the channel length of marginal portion in the MOS transistor
Greater than the length of the channel of central part, correspondingly, the critical size at both ends is greater than the pass at intermediate position in the gate structure
Key size, the anti-fuse structures program when on the drain region and programming transistor apply program voltage after, cause source region and
The breakdown in drain region forms access, plays the role of antifuse.
The biggish channel in NMOS transistor edge critical size described in the anti-fuse structures can guarantee the edge
Channel and the channel at intermediate position can be breakdown simultaneously, realize and meanwhile programming, facilitate the anti-fuse structures and obtain one
(uniform) blown state caused, realizes the fusing rate that can not be realized in PPM rank in the prior art.Pass through institute
The setting anti-fuse structures are stated to be able to solve in the prior art since amorphous silicon (amorphous silicon) and metal are closed
Anti-fuse structures caused by gold are difficult the problem of maintaining a long-term stability, and improved anti-fuse structures are able to maintain prolonged steady
It is qualitative, with good performance and yield.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 a-1b is in structural schematic diagram when off and on state for anti-fuse structures in the prior art；
Fig. 2 a-2c is the structural schematic diagram and circuit diagram of anti-fuse structures in the embodiment of the invention；
Fig. 3 is the structural schematic diagram of NMOS transistor described in the embodiment of the invention；
Fig. 4 is channel width in the embodiment of the invention to the schematic diagram of anti-fuse structures stability influence.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, it is of the present invention anti-to illustrate
Fuse-wires structure.Obviously, execution of the invention is not limited to the specific details that the technical staff of semiconductor field is familiar with.The present invention
Preferred embodiment be described in detail as follows, however in addition to these detailed description other than, the present invention can also have other embodiments.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singular
It is intended to include plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in the present specification
When, indicate that there are the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more
Other a features, entirety, step, operation, element, component and/or their combination.
Now, an exemplary embodiment of the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness of layer and region is exaggerated
Degree, and make that identical element is presented with like reference characters, thus description of them will be omitted.
The present invention is existing in the prior art various in order to solve the problems, such as, provides a kind of anti-fuse structures, comprising:
Semiconductor substrate；
Gate structure is located in the semiconductor substrate, and the length of the channel at the gate structure both ends is greater than intermediate sulcus
The length in road；
Source region and drain region are located at the two sides of the gate structure, and the source region is connected with programming transistor, the drain region with
Power supply is programmed to be connected.
Anti-fuse structures of the present invention include a MOS transistor, preferably NMOS transistor, channel in the NMOS
It is set to conventional NMOS transistor difference, the channel length of marginal portion is greater than the channel of central part in the NMOS transistor
Length, correspondingly, in the gate structure both ends critical size be greater than intermediate position critical size.
Wherein, the source region is connected with the drain electrode of the programming transistor, the source electrode ground connection of the programming transistor, described
The grid connection programming power supply of programming transistor.
The anti-fuse structures program when on the drain region and programming transistor apply program voltage after, cause source region and
The breakdown in drain region forms access, at this point, the gate structure becomes floating gate, is constantly in after the NMOS transistor is breakdown
The state of access ON, plays the role of antifuse.
The biggish channel in NMOS transistor edge critical size described in the anti-fuse structures can guarantee the edge
Channel and the channel at intermediate position can be breakdown simultaneously, realize and meanwhile programming, facilitate the anti-fuse structures and obtain one
(uniform) blown state caused, realizes the fusing rate that can not be realized in PPM rank in the prior art.Pass through institute
The setting anti-fuse structures are stated to be able to solve in the prior art since amorphous silicon (amorphous silicon) and metal are closed
Anti-fuse structures caused by gold are difficult the problem of maintaining a long-term stability, and improved anti-fuse structures are able to maintain prolonged steady
It is qualitative, with good performance and yield.
Wherein, the MOS transistor can be symmetrically, such as be formed simultaneously with LDD on the inside of the source region and drain region
The inside in doped region or the source region and drain region does not form LDD doped region；In addition, the MOS transistor can also be not
Symmetrically, such as only LDD doped region is formed in the inside of the source region doped region, does not form LDD doping in the drain region
Area.
Anti-fuse structures of the present invention are described in further detail with reference to the accompanying drawing.
Embodiment 1
With reference first to Fig. 2 a, Fig. 2 a is the anti-fuse structures of one specifically embodiment of the present invention, wherein the left side
Attempt for the schematic diagram of the anti-fuse structures, the right side attempts for the circuit diagram of the anti-fuse structures.
As shown in Figure 2 a, the anti-fuse structures include a NMOS transistor, and the NMOS transistor includes semiconductor lining
Bottom 201, gate structure 205 are located in the semiconductor substrate, and source region 204 and drain region 203 are located at the two of the gate structure
Side, the source region are connected with programming transistor, and the drain region is connected with programming power supply Vd.Further, the source region 204 with it is described
The drain electrode of programming transistor is connected, the source electrode ground connection of the programming transistor, the grid connection programming electricity of the programming transistor
Source Vd.
Wherein, silicon can be laminated on silicon, silicon-on-insulator (SOI), insulator in the semiconductor substrate 201
(SSOI), SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator are laminated on insulator
(GeOI) etc..It is P type substrate in semiconductor substrate 201.
Preferably, p-well 202 is formed in the semiconductor substrate 201, the gate structure 205, source region 204 and leakage
Area 203 is all set on the p-well 202, the forming method of the p-well 202 be in the semiconductor substrate 201 doped with
P-type admixture, such as boron, such as can then be utilized by ion implantation technology by boron injection and the semiconductor substrate 201
Heat treatment process drives in admixture, to form p-type admixture.
The gate structure 205 is located on the p-well 202, and the gate structure 205 can be conventional polysilicon gate
It extremely can also be metal gate structure, include the gate dielectric in the semiconductor substrate 201 in the gate structure 205
Layer, can also be comprising other conventional settings such as offset side wall and clearance wall, and details are not described herein, and those skilled in the art can
To be designed according to actual needs, it is not limited to a certain structure.
Setting of the gate structure 205 with conventional gate structure difference in the gate structure shape, the implementation
The top view of gate structure 205 described in example is as shown in figure 3, the gate structure 205 is whole in " dumbbell shaped ", the grid knot
The thick intermediate thin shape in the both ends that structure 205 is in, the critical size of the edges at two ends of the gate structure 205 is Lw, the grid
The critical size of 205 middle section of structure is Ln, the edges at two ends part of the gate structure 205 and the weight of the source region 204
The critical size of folded part is We, and wherein Lw is greater than Ln.
By the setting of the gate shapes, accordingly in the NMOS transistor available edge channel length
Spend larger, and the length of middle section channel is smaller, NMOS transistor edge critical size described in the anti-fuse structures compared with
Big channel can guarantee that the channel at the edge channels and intermediate position can be breakdown simultaneously, realize and meanwhile programming, have
Help the anti-fuse structures and obtain consistent (uniform) blown state, realizing in the prior art cannot in PPM rank
The fusing rate enough realized is able to maintain prolonged stability, with good performance and yield.Further, it is also possible to pass through
The length of further preferred described Lw, Ln and We, to obtain optimal programing effect and stability.
If Fig. 4 is that channel width, can be with by the figure to the schematic diagram of anti-fuse structures stability influence in the embodiment
Find out that the performance degradation of the reduction anti-fuse structures with channel width is continuously increased, and is arranged at marginal position wider
Channel width be because due at marginal position and shallow trench isolation intersection formed boundary defect (interface
Traps), lead to the transposition (modulation) of electric field, therefore can ensure itself and center after edge channel length is widened
Locating channel has consistent breakdown performance.
It is also formed with source region 204 and drain region 203 in the two sides of the gate structure, preferably, the source region 204 and leakage
Area 203 is formed by way of ion implanting after forming grid offset side wall and clearance wall, the N type dopant include P,
As, Sb, the ion energy of the injection are 1kev-10kev, and the ion dose of injection is 5 × 1014-5×1016Atom/cm2.?
It is preferably 400 DEG C in the present invention hereinafter, and can relatively be independent control Impurity Distribution (ion energy) by the method
And impurity concentration (ion current density and injection length), this method are easier to obtain the doping of high concentration, and are each to different
Property doping, can independent controlling depth and concentration.
The transistor of anti-fuse structures described in the embodiment is NMOS transistor, it should be understood that in order to more preferable
Ground illustrates that transistor is limited to NMOS by the structure of the transistor, but the transistor can also for PMOS transistor or other
Transistor, it is not limited to it is a certain, as long as there can be above structure, realize the effect of transistor.
As a further preference, the anti-fuse structures can also further include LDD doped region 206, and the LDD mixes
Miscellaneous area 206 can only be formed in the inside of source region 204, and the NMOS transistor is non-symmetric transistor at this time, and the LDD mixes
Miscellaneous area 206 can also be set to the inside in the source region 204 and drain region 203 simultaneously, at this point, the NMOS transistor is symmetrical
Transistor.
In order to simplify the preparation process of the antifuse, the LDD doped region 206 can not also be formed, relative to formation
LDD doped region 206 has when not forming LDD doped region 206 in the inside of the source region 204 and drain region 203 in drain region
There is higher electric field, while source region-drain region breakdown voltage is also lower.
The LDD doped region 206 is lightly doped for N-type, and the LDD doped region 206 can pass through ion implantation technology or expansion
Day labor skill is formed.The ionic type of LDD injection determines according to by the electrical property of semiconductor devices to be formed, that is, the device formed
Part is NMOS device, then the foreign ion mixed in LDD injection technology is one of phosphorus, arsenic, antimony, bismuth or combination.
The Programming Principle of anti-fuse structures in the embodiment are as follows: the drain region 204 is connect with programming power supply, the source region
204 are connected with the drain electrode of the programming transistor, and the source electrode ground connection of the programming transistor, the grid of the programming transistor connects
Programming power supply is connect, the anti-fuse structures apply program voltage on the grid of the drain region 204 and programming transistor when programming
Afterwards, cause the breakdown of source region and drain region, form access, at this point, the gate structure and the semiconductor substrate are floating, it is described
It is constantly in the state of access ON after NMOS transistor is breakdown, plays the role of antifuse.Wherein it is described it is floating be exactly not
Electric power loop ground connection, no matter positive and negative anodes, midpoint or any phase of exchange, neutral point etc., in this embodiment, the grid knot
Structure and the unearthed formation current loop of the semiconductor substrate.Unless otherwise specified, described in this application
It is floating referring to the explanation.
Embodiment 2
With reference first to Fig. 2 b, Fig. 2 b is the anti-fuse structures of one specifically embodiment of the present invention, wherein the left side
Attempt for the schematic diagram of the anti-fuse structures, the right side attempts for the circuit diagram of the anti-fuse structures.
As shown in Figure 2 b, the anti-fuse structures include a NMOS transistor, and the MOS transistor includes semiconductor substrate
201, gate structure 205 is located in the semiconductor substrate, and source region 204 and drain region 203 are located at the two sides of the gate structure,
The source region and the gate structure 205 are connected with programming transistor, and the drain region is connected with programming power supply Vd.
Wherein, the semiconductor substrate 201 is P type substrate, preferably, forming p-well in the semiconductor substrate 201
202, the gate structure 205, source region 204 and drain region 203 are all set on the p-well 202.
The semiconductor substrate 201 can select substrate commonly used in the art, and the forming method of the p-well can be selected often
The doping method of rule, the ionic species of the doping and concentration etc. can be designed according to device, it is not limited to certain
A kind of or a certain range, details are not described herein.
The gate structure 205 is located on the p-well 202, and the gate structure 205 can be conventional polysilicon gate
It extremely can also be metal gate structure, include the gate dielectric in the semiconductor substrate 201 in the gate structure 205
Layer, can also be comprising other conventional settings such as offset side wall and clearance wall, and details are not described herein, and those skilled in the art can
To be designed according to actual needs, it is not limited to a certain structure.
Setting of the gate structure 205 with conventional gate structure difference in the gate structure shape, the implementation
The top view of gate structure 205 described in example is as shown in figure 3, the gate structure 205 is whole in " dumbbell shaped ", the grid knot
The thick intermediate thin shape in the both ends that structure 205 is in, the critical size of the edges at two ends of the gate structure 205 is Lw, the grid
The critical size of 205 middle section of structure is Ln, the edges at two ends part of the gate structure 205 and the weight of the source region 204
The critical size of folded part is We, and wherein Lw is greater than Ln.
By the setting of the gate shapes, accordingly in the NMOS transistor available edge channel length
Spend larger, and the length of middle section channel is smaller, NMOS transistor edge critical size described in the anti-fuse structures compared with
Big channel can guarantee that the channel at the edge channels and intermediate position can be breakdown simultaneously, realize and meanwhile programming, have
Help the anti-fuse structures and obtain consistent (uniform) blown state, realizing in the prior art cannot in PPM rank
The fusing rate enough realized is able to maintain prolonged stability, with good performance and yield.Further, it is also possible to pass through
The length of further preferred described Lw, Ln and We, to obtain optimal programing effect and stability.
It is also formed with source region 204 and drain region 203 in the two sides of the gate structure, preferably, the source region 204 and leakage
Area 203 is formed by way of ion implanting after forming grid offset side wall and clearance wall, the N type dopant include P,
As, Sb, the ion energy of the injection are 1kev-10kev, and the ion dose of injection is 5 × 1014-5×1016Atom/cm2.?
It is preferably 400 DEG C in the present invention hereinafter, and can relatively be independent control Impurity Distribution (ion energy) by the method
And impurity concentration (ion current density and injection length), this method are easier to obtain the doping of high concentration, and are each to different
Property doping, can independent controlling depth and concentration.
The transistor of anti-fuse structures described in the embodiment is NMOS transistor, it should be understood that in order to more preferable
Ground illustrates that transistor is limited to NMOS by the structure of the transistor, but the transistor can also for PMOS transistor or other
Transistor, it is not limited to it is a certain, as long as there can be above structure, realize the effect of transistor.
As a further preference, the anti-fuse structures can also further include LDD doped region 206, and the LDD mixes
Miscellaneous area 206 can only be formed in the inside of source region 204, and the NMOS transistor is non-symmetric transistor at this time, and the LDD mixes
Miscellaneous area 206 can also be set to the inside in the source region 204 and drain region 203 simultaneously, at this point, the NMOS transistor is symmetrical
Transistor.
In order to simplify the preparation process of the antifuse, the LDD doped region 206 can not also be formed, relative to formation
LDD doped region 206 has when not forming LDD doped region 206 in the inside of the source region 204 and drain region 203 in drain region
There is higher electric field, while source region-drain region breakdown voltage is also lower.
The LDD doped region 206 is lightly doped for N-type, and the LDD doped region 206 can pass through ion implantation technology or expansion
Day labor skill is formed.The ionic type of LDD injection determines according to by the electrical property of semiconductor devices to be formed, that is, the device formed
Part is NMOS device, then the foreign ion mixed in LDD injection technology is one of phosphorus, arsenic, antimony, bismuth or combination.
The Programming Principle of anti-fuse structures in the embodiment are as follows: the drain region 204 is connect with programming power supply, the source region
204 are connected with the drain electrode of the programming transistor, and the source electrode ground connection of the programming transistor, the grid of the programming transistor connects
Programming power supply is connect, the anti-fuse structures apply program voltage on the grid of the drain region 204 and programming transistor when programming
Afterwards, cause the breakdown of source region and drain region, form access, at this point, the semiconductor substrate 205 is floating, the NMOS transistor quilt
It is constantly in the state of access ON after breakdown, plays the role of antifuse.
Embodiment 3
In this embodiment, the anti-fuse structures further comprise the P-doped zone positioned at 204 outside of source region
207, as shown in Figure 2 c, in the setting of P-doped zone 207 and the p-well 202, the P-doped zone 207 and the programming
Transistor is connected.
Other compositions of the anti-fuse structures are and embodiment 2 is identical, are referred to embodiment 2, details are not described herein.
The Programming Principle of anti-fuse structures in the embodiment are as follows: the drain region 204 is connect with programming power supply, the source region
204 are connected with the drain electrode of the programming transistor, and the source electrode ground connection of the programming transistor, the grid of the programming transistor connects
Programming power supply is connect, the anti-fuse structures apply program voltage on the grid of the drain region 204 and programming transistor when programming
Afterwards, cause source region and drain region breakdown, formed access, at this point, the gate structure 205, semiconductor substrate 201, drain region 205 with
And source region 204 is connected to, and the state of access ON is constantly in after the NMOS transistor is breakdown, plays the role of antifuse.
Anti-fuse structures of the present invention include a MOS transistor, the channel length of marginal portion in the MOS transistor
Greater than the length of the channel of central part, correspondingly, the critical size at both ends is greater than the pass at intermediate position in the gate structure
Key size, the anti-fuse structures program when on the drain region and programming transistor apply program voltage after, cause source region and
The breakdown in drain region forms access, plays the role of antifuse.
The biggish channel in NMOS transistor edge critical size described in the anti-fuse structures can guarantee the edge
Channel and the channel at intermediate position can be breakdown simultaneously, realize and meanwhile programming, facilitate the anti-fuse structures and obtain one
(uniform) blown state caused, realizes the fusing rate that can not be realized in PPM rank in the prior art.Pass through institute
The setting anti-fuse structures are stated to be able to solve in the prior art since amorphous silicon (amorphous silicon) and metal are closed
Anti-fuse structures caused by gold are difficult the problem of maintaining a long-term stability, and improved anti-fuse structures are able to maintain prolonged steady
It is qualitative, with good performance and yield.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
1. a kind of anti-fuse structures, comprising:
NMOS transistor, the channel length of edge is greater than the channel length at center in the NMOS transistor；
Programming transistor, the source region in the NMOS transistor is connected with the programming transistor, in the NMOS transistor
Drain region is connected with programming power supply；
The NMOS transistor includes the whole gate structure in dumbbell shaped, so that the anti-fuse structures obtain consistent fusing
State.
2. anti-fuse structures according to claim 1, which is characterized in that the grid of the NMOS transistor and body area are floating
It sets.
3. anti-fuse structures according to claim 1, which is characterized in that the grid of the NMOS transistor is connected with source region
It is floating to the body area of the programming transistor, the NMOS transistor.
4. anti-fuse structures according to claim 1, which is characterized in that grid, source region and the body of the NMOS transistor
Area is connected to the programming transistor.
5. anti-fuse structures according to claim 1, which is characterized in that the NMOS transistor includes:
Semiconductor substrate；
Gate structure is located in the semiconductor substrate, and the length of the channel below the gate structure both ends is greater than intermediate
The length of channel；
Source region and drain region are located at the two sides of the gate structure, and the source region is connected with programming transistor, the drain region and programming
Power supply is connected, so that the anti-fuse structures obtain consistent blown state.
6. anti-fuse structures according to claim 5, which is characterized in that the critical size at the both ends of the gate structure is big
In intermediate critical size.
7. anti-fuse structures according to claim 5, which is characterized in that the anti-fuse structures further include be only located at it is described
LDD doped region on the inside of drain region.
8. anti-fuse structures according to claim 5, which is characterized in that the anti-fuse structures further include being located at the source
LDD doped region on the inside of area and the LDD doped region on the inside of the drain region.
9. anti-fuse structures according to claim 5, which is characterized in that the semiconductor substrate is P-type semiconductor substrate.
10. anti-fuse structures according to claim 9, which is characterized in that it is formed with p-well in the P-type semiconductor substrate,
The anti-fuse structures are set in the p-well.
11. anti-fuse structures according to claim 9, which is characterized in that the source region and the drain region are that N-type is mixed
It is miscellaneous.
12. anti-fuse structures according to claim 10, which is characterized in that the anti-fuse structures further include p-type doping
Area, the P-doped zone are located in the p-well.
13. anti-fuse structures according to claim 12, which is characterized in that the P-doped zone and the programming crystal
Pipe is connected.
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| CN109786359B (en) * | 2017-11-13 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN109961821A (en) * | 2017-12-22 | 2019-07-02 | 长鑫存储技术有限公司 | Disposable programmable non-volatile fuse storage unit |
| US11189356B2 (en) | 2020-02-27 | 2021-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | One-time-programmable memory |
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| KR20110111954A (en) * | 2010-04-06 | 2011-10-12 | 창원대학교 산학협력단 | Antifuse one time programmable cell of dual port |
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