CN104425380B - The forming method of CMOS inverter grid - Google Patents
The forming method of CMOS inverter grid Download PDFInfo
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- CN104425380B CN104425380B CN201310401303.XA CN201310401303A CN104425380B CN 104425380 B CN104425380 B CN 104425380B CN 201310401303 A CN201310401303 A CN 201310401303A CN 104425380 B CN104425380 B CN 104425380B
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000000463 material Substances 0.000 claims abstract description 86
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 73
- 238000005530 etching Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 230000003667 anti-reflective effect Effects 0.000 claims description 13
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 12
- 239000007772 electrode material Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 210000002381 plasma Anatomy 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
A kind of forming method of grid, including：Substrate is provided, gate material layers is formed, the first list structure and the second list structure is formed in the gate material layers；The first sacrifice layer and patterned first mask layer are formed, patterned first mask layer exposes the first sacrifice layer on the first list structure；The second sacrifice layer is formed afterwards, the first photoresist with first window is formed on the second sacrifice layer, and the length of first window is equal to length of first photoresist on grid width direction；The first list structure is etched along the first window；Etch the position that the second list structure after second list structure, etching defines second grid；Using the second list structure after the first list structure after etching and etching as mask, the gate material layers are etched, grid is formed.It will not be connected with each other between adjacent two first grid in the grid formed by the technical program, grid length direction same row.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a method for forming a grid electrode of a CMOS inverter.
Background
With the development of semiconductor technology, it becomes possible to fabricate highly integrated circuits. In order to improve the integration level of the circuit, on one hand, the critical dimension of the semiconductor device is reduced as much as possible so as to reduce the occupied area of the single semiconductor device; another aspect is to reduce the spacing between two adjacent devices as much as possible.
The following describes an example of the formation of a gate in a CMOS inverter.
Referring to fig. 1, a substrate 1 is provided.
Referring to fig. 2, a gate material layer 2 is formed on the substrate 1.
Referring to fig. 3, a hard mask layer 3 is formed on the gate material layer 2.
Referring to fig. 4A and 4B, a first patterned photoresist 4 is formed on the hard mask layer 3.
Fig. 4B is a top view of a first patterned photoresist 4 formed on the gate material layer 2, and fig. 4A is a schematic diagram of a plane cut along a cut line AA' in fig. 4B.
Referring to fig. 5A and 5B, the hard mask layer 3 is etched using the first patterned photoresist 4 as a mask to form a stripe-shaped hard mask 31, and the first patterned photoresist 4 is removed.
Fig. 5B is a top view of the formation of the stripe-shaped hard mask 31, and fig. 5A is a schematic diagram of a plane cut along a cutting line BB' in fig. 5B.
Referring to fig. 6A and 6B, a sacrificial layer 5 is formed on the gate material layer 2 and the stripe-shaped hard mask 31, an upper surface of the sacrificial layer 5 is flat, and an upper surface of the sacrificial layer 5 is higher than an upper surface of the stripe-shaped hard mask 31.
Fig. 6B is a top view of the sacrificial layer 5 being formed, and fig. 6A is a schematic view of fig. 6B along a plane cut by a cut line CC'.
Referring to fig. 7A and 7B, a photoresist 6 having a window 61 is formed on the sacrificial layer 5.
Fig. 7B is a top view of the photoresist 6 formed, and fig. 7A is a schematic view of fig. 7B taken along a plane cut by a cut line DD'.
Referring to fig. 8A and 8B, the sacrificial layer 5 and the stripe-shaped hard mask 31 are etched through the window 61 to form a patterned sacrificial layer and a patterned hard mask layer 32, and the photoresist 6 and the patterned sacrificial layer are removed.
Fig. 8B is a top view of patterned hard mask layer 32, and fig. 8A is a schematic view of fig. 8B along a plane cut by cut line EE'.
Referring to fig. 9A and 9B, the gate material layer 2 is etched using the patterned hard mask layer 32 as a mask to form a gate 21.
Fig. 9B is a plan view of the gate electrode 21 formed, and fig. 9A is a schematic view of a plane cut along a cutting line FF' in fig. 9B.
The gates 21 prepared by the method are arranged in a staggered manner, and even if the gates 21 are arranged tightly, the mutual interference of electric signals between two adjacent inverters can be prevented after the CMOS inverters are formed, so that the distance between two adjacent devices can be reduced, and the integration level of an integrated circuit is increased.
Referring to fig. 7B, however, since the area of the window 61 is too small, the profile of the window 61 is easily deformed when the photoresist 6 having the window 61 is formed by exposure and development, and residues generated at the time of development are easily attached in the window 61. When the stripe-shaped hard mask 31 is etched through the window 61, incomplete etching is easily caused. And then, the patterned hard mask layer 32 is used as a mask, when the gate material layer 2 is etched, the formed gates 22 may be connected with each other, so that the formed CMOS inverter fails.
Disclosure of Invention
The problem to be solved by the invention is that in the prior art, the gates may be connected to each other.
In order to solve the above problems, the present invention provides a method for forming a gate of a CMOS inverter, wherein the gate is divided into a first gate and a second gate, the first gate and the second gate are arranged periodically in a gate width direction, each period has two adjacent rows of first gates and two adjacent rows of second gates, and the first gate and the second gate are arranged in a staggered manner in the gate width direction; the method comprises the following steps:
providing a substrate, forming a grid electrode material layer on the substrate, and forming a plurality of first strip-shaped structures and second strip-shaped structures which are arranged in parallel on the grid electrode material layer, wherein the first strip-shaped structures define the position of a first grid electrode in the grid width direction, and the second strip-shaped structures define the position of a second grid electrode in the grid width direction;
forming a first sacrificial layer on the first strip-shaped structure, the second strip-shaped structure and the grid material layer, and forming a patterned first mask layer on the first sacrificial layer, wherein the upper surface of the first sacrificial layer is flat, and the patterned first mask layer exposes the first sacrificial layer on the first strip-shaped structure;
forming a second sacrificial layer on the first sacrificial layer and the patterned first mask layer, and forming a first photoresist with a first window on the second sacrificial layer, wherein the upper surface of the second sacrificial layer is flat, the first window defines the distance between two adjacent first grid electrodes in the grid length direction, and the length of the first window is equal to the length of the first photoresist in the grid width direction;
etching the second sacrificial layer, the first sacrificial layer and the first strip-shaped structure along the first window, and then removing the first photoresist, the second sacrificial layer, the first sacrificial layer and the patterned first mask layer;
etching the second strip-shaped structure, wherein the position of the second grid electrode is defined by the etched second strip-shaped structure;
and etching the grid electrode material layer by taking the etched first strip-shaped structure and the etched second strip-shaped structure as masks to form a first grid electrode and a second grid electrode.
Optionally, the method for etching the second stripe structure includes:
forming a third sacrificial layer on the gate material layer, the second strip-shaped structure and the etched first strip-shaped structure, forming a patterned second mask layer on the upper surface of the third sacrificial layer, wherein the patterned second mask layer exposes the third sacrificial layer on the second strip-shaped structure, and the upper surface of the third sacrificial layer is flat;
forming a fourth sacrificial layer on the third sacrificial layer and the patterned second mask layer, and forming a second photoresist with a second window on the fourth sacrificial layer, wherein the upper surface of the fourth sacrificial layer is flat, the second window defines the distance between two adjacent second gates in the gate length direction, and the length of the second window is equal to the length of the second photoresist in the gate width direction;
and etching the fourth sacrificial layer, the third sacrificial layer and the second strip-shaped structure along the second window, and then removing the second photoresist, the third sacrificial layer, the fourth sacrificial layer and the patterned second mask layer.
Optionally, after the first gate and the second gate are formed, the method further includes:
and removing the etched first strip-shaped structure and the etched second strip-shaped structure.
Optionally, the projection of the second window on the substrate overlaps with the projection of the first window on the substrate; or,
the projection of the second window on the substrate and the projection of the first window on the substrate are spaced apart from each other.
Optionally, the first sacrificial layer, the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer are silicon oxide layers, silicon nitride layers or silicon carbide layers.
Optionally, the patterned first mask layer and the patterned second mask layer are titanium nitride layers or silicon nitride layers.
Optionally, the first strip-shaped structure and the second strip-shaped structure are made of titanium nitride or silicon nitride.
Optionally, before forming the first photoresist, a first hard mask layer and a first bottom anti-reflection layer are sequentially formed on the second sacrificial layer from bottom to top, and the first photoresist is formed on the first bottom anti-reflection layer.
Optionally, before forming a second photoresist, a second hard mask layer and a second bottom anti-reflection layer are sequentially formed on the fourth sacrificial layer from bottom to top, and the second photoresist is formed on the second bottom anti-reflection layer.
Optionally, the first hard mask layer and the second hard mask layer are titanium nitride layers or silicon nitride layers.
Optionally, the first bottom anti-reflection layer and the second bottom anti-reflection layer are organic bottom anti-reflection layers or inorganic bottom anti-reflection layers.
Optionally, the gate material layer is a polysilicon layer.
Optionally, before forming the gate material layer on the substrate, a gate dielectric layer is formed on the substrate, and the gate material layer is formed on the gate dielectric layer.
Optionally, the method for forming a plurality of first strip-shaped structures and second strip-shaped structures arranged in parallel on the gate material layer includes:
forming a strip-shaped structure material layer on the grid material layer;
forming a patterned photoresist on the strip-shaped structure material layer;
and etching the strip-shaped structure material layer by taking the patterned photoresist as a mask to form a plurality of first strip-shaped structures and second strip-shaped structures which are arranged in parallel.
Optionally, before forming the patterned photoresist on the strip-shaped structure material layer, a third hard mask layer and a third bottom anti-reflection layer are sequentially formed on the strip-shaped structure material layer from bottom to top, and the patterned photoresist is formed on the third bottom anti-reflection layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the technical scheme includes that a first patterned mask layer is used for exposing a first sacrificial layer on a first strip-shaped structure, and a first photoresist with a first window is used as a mask to etch the first strip-shaped structure; the length of the first window is equal to the length of the first photoresist in the gate width direction, so that the area of the first window is large, and the first window can be prevented from deforming or adhering residues during exposure and development. Furthermore, the first strip-shaped structures after two adjacent etchings on the same column in the gate length direction can be prevented from being connected with each other. And etching the grid electrode material layer by taking the etched first strip-shaped structure as a mask to form a first grid electrode, wherein two adjacent grid electrodes on the same row in the grid length direction are separated from each other, so that the two adjacent grid electrodes on the same row in the grid length direction are prevented from being connected with each other.
Further, the third sacrificial layer on the second strip-shaped structure is exposed by using the patterned second mask layer, and the second strip-shaped structure is etched by taking the second photoresist with the second window as a mask. The length of the second window is equal to the length of the second photoresist in the gate width direction, so that the area of the second window is large, and the second window can be prevented from being deformed or attached with residues during exposure and development. Furthermore, the second strip-shaped structures after two adjacent etchings on the same column in the gate length direction can be prevented from being connected with each other. And etching the grid electrode material layer by taking the etched second strip-shaped structure as a mask to form second grid electrodes, wherein two adjacent grid electrodes on the same row in the grid length direction are mutually separated, so that the two adjacent grid electrodes on the same row in the grid length direction are prevented from being mutually connected.
Drawings
FIGS. 1 to 9B are schematic diagrams of stages in the fabrication of a gate in the prior art;
fig. 10-25B are schematic diagrams of stages in the fabrication of gates in accordance with an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The embodiment provides a method for forming a gate of a CMOS inverter, wherein the gate is divided into a first gate and a second gate, the first gate and the second gate are arranged periodically in the gate width direction, each period has two adjacent columns of first gates and two adjacent columns of second gates, and the first gate and the second gate are arranged in a staggered manner in the gate width direction; the forming method of the gate of the CMOS inverter comprises the following steps:
referring to fig. 10, a substrate 110 is provided.
In a specific embodiment, the material of the substrate 110 is monocrystalline silicon, polycrystalline silicon, amorphous silicon, or silicon-on-insulator. A source electrode and a drain electrode may be formed in the substrate 110.
Referring to fig. 11, a gate material layer 120 is formed on the substrate 110.
The method for forming the gate material layer 120 may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, or epitaxial growth. The gate material layer 120 may be a polysilicon layer.
In other embodiments, before forming the gate material layer 120 on the substrate 110, a gate dielectric layer may be formed on the substrate 110, and then the gate material layer 120 may be formed on the gate dielectric layer.
Then, a plurality of first strip-shaped structures and second strip-shaped structures are formed on the gate material layer 120, where the first strip-shaped structures define the position of the first gate in the gate width direction, and the second strip-shaped structures define the position of the second gate in the gate width direction, that is, the gate width direction is perpendicular to the length directions of the first strip-shaped structures and the second strip-shaped structures.
The method for forming a plurality of first strip-shaped structures and second strip-shaped structures which are arranged in parallel comprises the following steps:
referring to fig. 12, a strip-shaped material layer 130 is formed on the gate material layer 120.
The method for forming the stripe structure material layer 130 may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other methods known in the art. For example, the physical vapor deposition may be performed by using Ar and N2 plasmas as sputtering ions, where the Ar and N2 plasmas collide with a target made of the same material as the strip-shaped structure material layer 130, so as to separate molecules in the target from the target, and deposit the molecules on the gate material layer 120 to form the strip-shaped structure material layer 130.
In an embodiment, the strip structure material layer 130 is a titanium nitride layer or a silicon nitride layer.
Referring to fig. 13A and 13B, a patterned photoresist 103 is formed on the stripe-shaped structure material layer 130.
Fig. 13B is a top view of the patterned photoresist 103, and fig. 13A is a schematic diagram of the plane cut along the cut line AA' in fig. 13B.
In other embodiments, before the patterned photoresist 103 is formed on the strip-shaped structure material layer 130, a third hard mask layer and a third bottom anti-reflection layer are sequentially formed on the strip-shaped structure material layer 130 from bottom to top, and the patterned photoresist 103 is formed on the third bottom anti-reflection layer.
The third hard mask layer functions as a mask for etching the strip-shaped structure material layer 130, and the third bottom anti-reflection layer functions to reduce a reflection effect when the patterned photoresist 103 is formed, so as to improve accurate transfer of a fine pattern.
When the strip-shaped material layer 130 is a titanium nitride layer, the third hard mask layer may be a silicon nitride layer or a low-temperature silicon oxide layer; when the strip-shaped material layer 130 is silicon nitride, the third hard mask layer may be a titanium nitride layer or a low temperature silicon oxide layer. So as to ensure that the third hard mask layer can be used as a mask for etching the strip-shaped structure material layer 130. The third bottom anti-reflective layer may be an organic bottom anti-reflective layer or an inorganic bottom anti-reflective layer.
Referring to fig. 14A and 14B, the patterned photoresist 103 is used as a mask to etch the strip-shaped structure material layer 130, so as to form a plurality of first strip-shaped structures 131A and second strip-shaped structures 131B arranged in parallel. Then, the patterned photoresist 103 is removed.
The first stripe structures 131A and the second stripe structures 131B are arranged periodically in the gate width direction, and each period includes two adjacent first stripe structures 131A and two adjacent second stripe structures 131B.
In this embodiment, adjacent means that there is no other structure in the middle. That is, two adjacent first stripe structures 131A mean that no second stripe structure 131B or other first stripe structures 131A are formed between the two first stripe structures 131A. Similarly, two adjacent second bar structures 131B mean that the first bar structure 131A or other second bar structures 131B are not formed between the two second bar structures 131B.
Fig. 14B is a top view of the first and second stripe structures 131A and 131B, and fig. 14A is a schematic diagram of a plane cut along a cutting line BB' in fig. 14B. For differentiation, in fig. 14A and 14B, the first and second stripe structures 131A and 131B use different filling.
The method for etching the strip-shaped structure material layer 130 may be a plasma etching method.
Referring to fig. 15A and 15B, a first sacrificial layer 141 is formed on the first and second stripe structures 131A and 131B and the gate material layer 120, and an upper surface of the first sacrificial layer 141 is flat. The upper surface of the first sacrificial layer 141 is higher than the upper surfaces of the first and second stripe structures 131A and 131B.
Fig. 15B is a top view of the first sacrificial layer 141, and fig. 15A is a schematic diagram of fig. 15B along a tangent line CC' in a tangent plane.
A method of forming the first sacrificial layer 141 is a spin coating method or a deposition method.
In an embodiment, the first sacrificial layer 141 is a silicon oxide layer, a silicon nitride layer, or a silicon carbide layer, and the material of the first sacrificial layer 141 must be different from the material of the strip-shaped structure material layer 130, and when the first sacrificial layer 141 is etched, the first sacrificial layer 141 has a higher etching selectivity with respect to the first strip-shaped structure 131A and the second strip-shaped structure 131B. If the material of the bar-shaped structure material layer 130 is silicon nitride, the material of the first sacrificial layer 141 may be titanium nitride.
The first sacrificial layer 141 serves to provide a flat upper surface for a first mask layer to be patterned later.
Referring to fig. 16A and 16B, a patterned first mask layer 151 is formed on the first sacrificial layer 141, and the patterned first mask layer 151 exposes the first sacrificial layer 141 on the first stripe structure 131A.
Fig. 16B is a top view of the patterned first mask layer 151, and fig. 16A is a schematic view of the plane cut by the cut line DD' in fig. 16B.
The material of the patterned first mask layer 151 should be different from the material of both the first sacrificial layer 141 and the strip-shaped structure material layer 130. When the first sacrificial layer 141, the first stripe structure 131A, and the second stripe structure 131B are etched, the first sacrificial layer 141 and the patterned first mask layer 151 have a higher etching selectivity, and the first stripe structure 131A, the second stripe structure 131B and the patterned first mask layer 151 also have a higher etching selectivity. If the material of the strip-shaped structure material layer 130 is silicon nitride, the material of the first sacrificial layer 141 is titanium nitride, and the material of the patterned first mask layer 151 may be low-temperature silicon oxide.
In an embodiment, the method of forming the patterned first mask layer 151 includes:
forming a first mask material layer on the first sacrificial layer 141;
forming a patterned photoresist on the first mask material layer;
etching the first mask material layer by taking the patterned photoresist as a mask to form a patterned first mask layer 151;
and removing the patterned photoresist.
The patterned first mask layer 151 is formed to protect the second stripe structure 131B when the first stripe structure 131A is etched, so that the second stripe structure 131B is not etched.
Referring to fig. 17A and 17B, a second sacrificial layer 142 is formed on the first sacrificial layer 141 and the patterned first mask layer 151, and the upper surface of the second sacrificial layer 142 is flat. The upper surface of the second sacrificial layer 142 is higher than the upper surface of the patterned first mask layer 151.
Fig. 17B is a top view of the second sacrificial layer 142, and fig. 17A is a schematic view of fig. 17B along a plane cut by a cut line EE'.
The material and the formation method of the second sacrificial layer 142 may refer to those of the first sacrificial layer 141.
Referring to fig. 18A and 18B, a first photoresist 101 having a first window 161 is formed on the second sacrificial layer 142, and a length direction of the first window 161 is perpendicular to a length direction of the first stripe structure 131A. The first window 161 defines a distance between two adjacent first gates in the gate length direction.
Wherein the gate length direction is parallel to the length direction of the first stripe structure 131A and the second stripe structure 131B.
Fig. 18B is a top view of the first photoresist 101 formed, and fig. 18A is a schematic view of a plane cut along a cut line FF' in fig. 18B.
The length of the first window 161 is equal to the size of the first photoresist 101 in the gate width direction, i.e., the first window 161 penetrates the entire first photoresist 101 in the gate width direction. The area of the first window 161 is large, so that the first window 161 is prevented from being deformed during exposure and development, and residues are prevented from adhering to the side wall and the bottom of the first window 161.
Wherein the gate width direction is perpendicular to the gate length direction.
In other embodiments, before forming the first photoresist 101, a first hard mask layer and a first bottom anti-reflection layer may be sequentially formed on the second sacrificial layer 142 from bottom to top, and the first photoresist 101 is formed on the first bottom anti-reflection layer.
The first hard mask layer serves as a mask for etching the second sacrificial layer 142, the first sacrificial layer 141 and the first strip-shaped structure 131A, and the first bottom anti-reflection layer serves to reduce a reflection effect when the first photoresist 101 is formed, so that accurate transfer of a fine pattern is improved.
When the second sacrificial layer 142, the first sacrificial layer 141 and the first strip-shaped structure 131A are etched, the second sacrificial layer 142, the first sacrificial layer 141 and the first strip-shaped structure 131A are etched to have a higher etching selection ratio with respect to the second hard mask layer. In a specific embodiment, the first hard mask layer is a titanium nitride layer or a silicon nitride layer; the first bottom anti-reflective layer may be an organic bottom anti-reflective layer or an inorganic bottom anti-reflective layer.
Referring to fig. 19A and 19B, the second sacrificial layer 142, the first sacrificial layer 141 and the first stripe structures 131A are etched along the first windows 161; the first photoresist 101, the second sacrificial layer 142, the first sacrificial layer 141, and the patterned first mask layer 151 are then removed.
Fig. 19B is a top view of the first photoresist 101, the second sacrificial layer 142, the first sacrificial layer 141 and the patterned first mask layer 151 after being removed, and fig. 19A is a schematic view of a plane cut along a cut line GG' in fig. 19B.
Since the second stripe structures 131B are covered by the patterned first mask layer 151, the second stripe structures 131B are not etched.
Since the first strip-shaped structures 131A are not covered by the patterned first mask layer 151, each of the first strip-shaped structures 131A is etched into a plurality of small segments. Each first stripe structure 131A is etched into a small segment 132 and a small segment 133 in fig. 19B.
Since the first window 161 is not deformed and no residue is adhered to the sidewall and the bottom of the first window 161, when the first stripe structure 131A is etched through the first window 161, the exposed first stripe structure 131A can be completely etched, and the two adjacent etched first stripe structures on the same column in the gate length direction can be prevented from being connected with each other. The adjacent small sections are completely separated and are not connected with each other. I.e., the minor segment 132 and the minor segment 133 are completely spaced apart.
Moreover, the first window 161 has a large area and a good profile, so that the line edge roughness of the small segments 132 and 133 formed after the etching of the first stripe-shaped structure 131A can be reduced.
Then, the second stripe structure 131B is etched, and the position of the second gate is defined by the etched second stripe structure. The method for etching the second strip-shaped structure 131B includes:
referring to fig. 20A and 20B, a third sacrificial layer 143 is formed on the gate material layer 120, the etched first stripe structure 131A and the etched second stripe structure 131B, and an upper surface of the third sacrificial layer 143 is flat.
Fig. 20B is a top view of the third sacrificial layer 143, and fig. 20A is a schematic diagram of a plane cut along a cut line HH' in fig. 20B.
The formation method and material of the third sacrificial layer 143 may refer to the formation method and material of the first sacrificial layer 141.
The third sacrificial layer 143 serves to provide a flat surface for the subsequent formation of a patterned second mask layer.
Referring to fig. 21A and 21B, a patterned second mask layer 152 is formed on the upper surface of the third sacrificial layer, the patterned second mask layer 152 exposes the third sacrificial layer 143 on the second stripe structure 131B, and the patterned second mask layer 152 covers the etched first stripe structure 131A.
Fig. 21B is a top view of the patterned second mask layer 152, and fig. 21A is a schematic view of the plane cut along the cut line II' in fig. 21B.
In an embodiment, the method of forming the patterned second mask layer 152 includes:
forming a second mask material layer on the third sacrificial layer 143;
forming a patterned photoresist on the second mask material layer;
etching the second mask material layer by taking the patterned photoresist as a mask to form a patterned second mask layer 152;
and removing the patterned photoresist.
The material of the patterned second mask layer 152 may be referred to the material of the patterned first mask layer 151.
Referring to fig. 22A and 22B, a fourth sacrificial layer 144 is formed on the third sacrificial layer 143 and the patterned second mask layer 152, and the upper surface of the fourth sacrificial layer 144 is flat.
Fig. 22B is a top view of the fourth sacrificial layer 144, and fig. 22A is a schematic diagram of fig. 22B along a tangent line JJ'.
The formation method and material of the fourth sacrificial layer 144 may refer to the formation method and material of the first sacrificial layer 141.
The function of the fourth sacrificial layer 144 is to provide a flat surface for the subsequent formation of the second photoresist.
Referring to fig. 23A and 23B, a second photoresist 102 having a second window 162 is formed on the fourth sacrificial layer 144, and a length direction of the second window 162 is parallel to a length direction of the first window 161. The second windows 162 define a distance between two adjacent second gates in the gate length direction.
Fig. 23B is a top view of the second photoresist 102 and fig. 23A is a schematic view of fig. 23B along a tangent line KK'.
The length of the second window 162 is equal to the length of the first window 161, i.e., the second window 162 extends through the entire second photoresist 102 in the direction of the length of the second window 162. Therefore, the area of the second window 162 is large, so that the second window 162 is prevented from being deformed during exposure and development, and residues are prevented from adhering to the side wall and the bottom of the second window 162.
In other embodiments, before forming the second photoresist 102, a second hard mask layer and a second bottom anti-reflection layer may be sequentially formed on the fourth sacrificial layer 144 from bottom to top, and the second photoresist 102 is formed on the second bottom anti-reflection layer.
The second hard mask layer serves as a mask for etching the second stripe structure 131B, and the second bottom anti-reflection layer serves to reduce a reflection effect when the second photoresist 102 is formed, so as to improve accurate transfer of a fine pattern.
The material of the second hard mask layer may be referred to the material of the first hard mask layer. The second bottom anti-reflective layer may be an organic bottom anti-reflective layer or an inorganic bottom anti-reflective layer.
In the present embodiment, the projection of the second window 162 on the substrate 110 and the projection of the first window 161 on the substrate 110 are spaced apart from each other without overlap. So that the first grid and the second grid are arranged in a staggered mode in the grid width direction.
In other embodiments, the projection of the second window 162 on the substrate 110 and the projection of the first window 161 on the substrate 110 may also partially overlap.
Referring to fig. 24A and 24B, the fourth sacrificial layer 144, the third sacrificial layer 143 and the second stripe structures 131B are etched along the second windows 162. Then, the second photoresist 102, the third sacrificial layer 143, the fourth sacrificial layer 144 and the patterned second mask layer 152 are removed.
Fig. 24B is a top view of the second photoresist 102, the third sacrificial layer 143, the fourth sacrificial layer 144 and the patterned second mask layer 152 removed, and fig. 24A is a schematic view of fig. 24B along a plane cut by a cut line LL'.
Since the etched first stripe structures 131A are covered by the patterned second mask layer 152, the etched first stripe structures 131A are not etched.
Since the second stripe structures 131B are not covered by the patterned second mask layer 152, each of the second stripe structures 131B is etched into a plurality of small segments. Referring to fig. 24B, each second stripe structure 131B is etched into a small segment 134, a small segment 135, and a small segment 136.
Since the second window 162 is not deformed and no residue is adhered to the sidewall and the bottom of the second window 162, when the second stripe structure 131B is etched through the second window 162, the exposed second stripe structure 131B can be completely etched, so that the two etched second stripe structures adjacent to each other on the same column in the gate length direction can be prevented from being connected to each other. I.e., the minor segments 134, 135, and 136 are completely separated.
Moreover, the second windows 162 have a large area and a good profile, which can reduce the line edge roughness of the segments 134, 135 and 136 formed after etching the second stripe structures 131B.
Referring to fig. 25A and 25B, the gate material layer 120 is etched using the etched first strip-shaped structure 131A and the etched second strip-shaped structure 131B as masks to form a first gate 121A and a second gate 121B. And the etched first strip structures 131A and the etched second strip structures 131B are removed.
Fig. 25B is a top view of the first gate 121A and the second gate 121B, and fig. 25A is a schematic view of the plane cut by the cut line MM' in fig. 25B.
Because the small sections of the etched first strip-shaped structure 131A and the etched second strip-shaped structure 131B are mutually separated, the line edge roughness is small; the etched first strip-shaped structures 131A and the etched second strip-shaped structures 131B are used as masks, so that two adjacent first gates 121A on the same column in the gate length direction are prevented from being connected with each other, and two adjacent second gates 121B on the same column in the gate length direction are also prevented from being connected with each other. And the line edge roughness of the first gate electrode 121A and the second gate electrode 121B is small.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (14)
1. A method for forming a grid of a CMOS inverter comprises the steps that the grid is divided into a first grid and a second grid, the first grid and the second grid are arranged periodically in the width direction of the grid, each period is provided with two adjacent columns of first grids and two adjacent columns of second grids, and the first grid and the second grid are arranged in a staggered mode in the width direction of the grid; characterized in that the method comprises:
providing a substrate, forming a grid electrode material layer on the substrate, and forming a plurality of first strip-shaped structures and second strip-shaped structures which are arranged in parallel on the grid electrode material layer, wherein the first strip-shaped structures define the position of a first grid electrode in the grid width direction, and the second strip-shaped structures define the position of a second grid electrode in the grid width direction;
forming a first sacrificial layer on the first strip-shaped structure, the second strip-shaped structure and the grid material layer, and forming a patterned first mask layer on the first sacrificial layer, wherein the upper surface of the first sacrificial layer is flat, and the patterned first mask layer covers the first sacrificial layer on the second strip-shaped structure and exposes the first sacrificial layer on the first strip-shaped structure;
forming a second sacrificial layer on the first sacrificial layer and the patterned first mask layer, and forming a first photoresist with a first window on the second sacrificial layer, wherein the upper surface of the second sacrificial layer is flat, the first window defines the distance between two adjacent first grid electrodes in the grid length direction, and the length of the first window is equal to the length of the first photoresist in the grid width direction;
etching the second sacrificial layer, the first sacrificial layer and the first strip-shaped structure along the first window, and then removing the first photoresist, the second sacrificial layer, the first sacrificial layer and the patterned first mask layer;
etching the second strip-shaped structure, wherein the position of the second grid electrode is defined by the etched second strip-shaped structure, and the method for etching the second strip-shaped structure comprises the following steps: forming a third sacrificial layer on the gate material layer, the second strip-shaped structure and the etched first strip-shaped structure, forming a patterned second mask layer on the upper surface of the third sacrificial layer, wherein the patterned second mask layer covers the third sacrificial layer on the first strip-shaped structure and exposes the third sacrificial layer on the second strip-shaped structure, and the upper surface of the third sacrificial layer is flat; forming a fourth sacrificial layer on the third sacrificial layer and the patterned second mask layer, and forming a second photoresist with a second window on the fourth sacrificial layer, wherein the upper surface of the fourth sacrificial layer is flat, the second window defines the distance between two adjacent second gates in the gate length direction, and the length of the second window is equal to the length of the second photoresist in the gate width direction; etching the fourth sacrificial layer, the third sacrificial layer and the second strip-shaped structure along the second window, and then removing the second photoresist, the third sacrificial layer, the fourth sacrificial layer and the patterned second mask layer;
and etching the grid electrode material layer by taking the etched first strip-shaped structure and the etched second strip-shaped structure as masks to form a first grid electrode and a second grid electrode.
2. The method of forming a gate of a CMOS inverter of claim 1, further comprising, after forming the first gate and the second gate:
and removing the etched first strip-shaped structure and the etched second strip-shaped structure.
3. The method of claim 1, wherein a projection of the second window on the substrate overlaps a projection of the first window on the substrate; or,
the projection of the second window on the substrate and the projection of the first window on the substrate are spaced apart from each other.
4. The method of forming a gate of a CMOS inverter of claim 1, wherein the first sacrificial layer, the second sacrificial layer, the third sacrificial layer, and the fourth sacrificial layer are silicon oxide layers, silicon nitride layers, or silicon carbide layers.
5. The method of claim 1, wherein the patterned first mask layer and the patterned second mask layer are a titanium nitride layer or a silicon nitride layer.
6. The method of claim 1, wherein the first and second strip structures are made of titanium nitride or silicon nitride.
7. The method for forming a gate of a CMOS inverter as claimed in claim 1, wherein a first hard mask layer and a first bottom anti-reflection layer are sequentially formed on the second sacrificial layer from bottom to top before forming a first photoresist, and the first photoresist is formed on the first bottom anti-reflection layer.
8. The method for forming a gate of a CMOS inverter as claimed in claim 1 or 7, wherein a second hard mask layer and a second bottom anti-reflection layer are sequentially formed on the fourth sacrificial layer from bottom to top before forming a second photoresist, and the second photoresist is formed on the second bottom anti-reflection layer.
9. The method of claim 8, wherein the first hard mask layer and the second hard mask layer are a titanium nitride layer or a silicon nitride layer.
10. The method of claim 8, wherein the first bottom anti-reflective layer and the second bottom anti-reflective layer are organic bottom anti-reflective layers or inorganic bottom anti-reflective layers.
11. The method of forming a gate of a CMOS inverter of claim 1, wherein the layer of gate material is a layer of polysilicon.
12. The method of forming a gate of a CMOS inverter of claim 1 or 11,
and before forming a grid electrode material layer on the substrate, forming a grid electrode dielectric layer on the substrate, wherein the grid electrode material layer is formed on the grid electrode dielectric layer.
13. The method of forming a gate of a CMOS inverter of claim 1, wherein the method of forming a plurality of first and second strip structures arranged in parallel on the layer of gate material comprises:
forming a strip-shaped structure material layer on the grid material layer;
forming a patterned photoresist on the strip-shaped structure material layer;
and etching the strip-shaped structure material layer by taking the patterned photoresist as a mask to form a plurality of first strip-shaped structures and second strip-shaped structures which are arranged in parallel.
14. The method for forming a gate of a CMOS inverter as claimed in claim 13, wherein a third hard mask layer and a third bottom anti-reflection layer are sequentially formed on the strip-shaped structure material layer from bottom to top before forming the patterned photoresist on the strip-shaped structure material layer, and the patterned photoresist is formed on the third bottom anti-reflection layer.
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| CN102683191A (en) * | 2011-03-17 | 2012-09-19 | 中芯国际集成电路制造(上海)有限公司 | Method forming gate pattern and semiconductor device |
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| CN102683191A (en) * | 2011-03-17 | 2012-09-19 | 中芯国际集成电路制造(上海)有限公司 | Method forming gate pattern and semiconductor device |
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