CN104425380B - The forming method of CMOS inverter grid - Google Patents

Abstract

A method for forming a gate, comprising: providing a substrate, forming a gate material layer, forming a first strip structure and a second strip structure on the gate material layer; forming a first sacrificial layer and a patterned first A mask layer, the patterned first mask layer exposes the first sacrificial layer on the first strip structure; then a second sacrificial layer is formed, and a first photoresist with a first window is formed on the second sacrificial layer , the length of the first window is equal to the length of the first photoresist in the gate width direction; the first strip structure is etched along the first window; the second strip structure is etched, and the etched second The strip structure defines the position of the second gate; using the etched first strip structure and the etched second strip structure as masks, etching the gate material layer to form a gate. For the gates formed by the technical solution, two adjacent first gates in the same column in the gate length direction will not be connected to each other.

Description

Formation method of CMOS inverter gate

technical field

The invention relates to the field of semiconductors, in particular to a method for forming a gate of a CMOS inverter.

Background technique

With the development of semiconductor technology, it becomes possible to prepare high integrated circuits. In order to improve the integration of circuits, on the one hand, it is necessary to reduce the critical size of semiconductor devices as much as possible to reduce the area occupied by a single semiconductor device; on the other hand, it is to reduce the distance between two adjacent devices as much as possible.

The formation of the gate in the CMOS inverter is taken as an example for illustration.

Referring to Fig. 1, a substrate 1 is provided.

Referring to FIG. 2 , a gate material layer 2 is formed on the substrate 1 .

Referring to FIG. 3 , a hard mask layer 3 is formed on the gate material layer 2 .

Referring to FIGS. 4A and 4B , a first patterned photoresist 4 is formed on the hard mask layer 3 .

Fig. 4B is a top view of the first patterned photoresist 4 formed on the gate material layer 2, and Fig. 4A is a schematic diagram of a plane cut along the tangent line AA' of Fig. 4B.

5A and 5B, using the first patterned photoresist 4 as a mask, etch the hard mask layer 3 to form a stripe hard mask 31, and remove the first patterned photoresist 4. Photoresist4.

FIG. 5B is a top view of forming a strip-shaped hard mask 31, and FIG. 5A is a schematic diagram of a plane cut along the tangent line BB' in FIG. 5B.

6A and 6B, a sacrificial layer 5 is formed on the gate material layer 2 and the strip-shaped hard mask 31, the upper surface of the sacrificial layer 5 is flat, and the upper surface of the sacrificial layer 5 is higher than the upper surface of the strip-shaped hard mask 31 .

Fig. 6B is a top view of the sacrificial layer 5 formed, and Fig. 6A is a schematic diagram of a plane cut along the tangent line CC' of Fig. 6B.

Referring to FIGS. 7A and 7B , a photoresist 6 with a window 61 is formed on the sacrificial layer 5 .

Fig. 7B is a top view of the photoresist 6 formed, and Fig. 7A is a schematic diagram of a plane cut along the tangent line DD' in Fig. 7B.

Referring to FIG. 8A and FIG. 8B, the sacrificial layer 5 and the strip-shaped hard mask 31 are etched through the window 61 to form a patterned sacrificial layer and a patterned hard mask layer 32, and the light is removed. Resist 6 and a patterned sacrificial layer.

FIG. 8B is a top view of the patterned hard mask layer 32, and FIG. 8A is a schematic diagram of a plane cut along the tangent line EE' in FIG. 8B.

Referring to FIG. 9A and FIG. 9B , using the patterned hard mask layer 32 as a mask, the gate material layer 2 is etched to form a gate 21 .

FIG. 9B is a top view with the gate 21 formed, and FIG. 9A is a schematic diagram of a plane cut along the tangent line FF' in FIG. 9B.

The gates 21 prepared by the above method are arranged in a staggered manner. Even if the gates 21 are closely arranged, after forming a CMOS inverter, it can prevent the electrical signals between two adjacent inverters from interfering with each other. Therefore, it can reduce the The spacing between two adjacent devices increases the integration of integrated circuits.

Referring to FIG. 7B , however, since the area of the window 61 is too small, when the photoresist 6 with the window 61 is formed by exposure and development, the shape of the window 61 is easily deformed, and the residue generated during the development is easy to adhere to the window 61 . When the strip-shaped hard mask 31 is etched through the window 61 , it is easy to cause incomplete etching. Then, when the gate material layer 2 is etched using the patterned hard mask layer 32 as a mask, the formed gates 22 may be connected to each other, resulting in failure of the formed CMOS inverter.

Contents of the invention

The problem solved by the present invention is that in the prior art, the gates may be connected to each other.

In order to solve the above problems, the present invention provides a method for forming the gate of a CMOS inverter. The gate is divided into a first gate and a second gate, and the first gate and the second gate are arranged periodically in the gate width direction. , there are two adjacent columns of first gates and two adjacent columns of second gates in each period, and the first gates and the second gates are arranged in a staggered manner in the gate width direction; the method includes:

A substrate is provided, a gate material layer is formed on the substrate, a plurality of first strip structures and second strip structures arranged in parallel are formed on the gate material layer, the first strip structures define a first gate At the position in the gate width direction, the second strip structure defines the position of the second gate in the gate width direction;

A first sacrificial layer is formed on the first strip structure, the second strip structure and the gate material layer, a patterned first mask layer is formed on the first sacrificial layer, and the first sacrificial layer The upper surface is flat, and the patterned first mask layer exposes the first sacrificial layer on the first strip structure;

A second sacrificial layer is formed on the first sacrificial layer and the patterned first mask layer, a first photoresist with a first window is formed on the second sacrificial layer, and the upper surface of the second sacrificial layer is flat , the first window defines the distance between two adjacent first gates in the gate length direction, and the length of the first window is equal to the length of the first photoresist in the gate width direction;

etching the second sacrificial layer, the first sacrificial layer and the first strip structure along the first window, and then removing the first photoresist, the second sacrificial layer, the first sacrificial layer and the patterned first sacrificial layer; a mask layer;

Etching the second strip structure, the etched second strip structure defines the position of the second gate;

Using the etched first strip structure and the etched second strip structure as a mask, the gate material layer is etched to form a first gate and a second gate.

Optionally, the method for etching the second strip structure includes:

A third sacrificial layer is formed on the gate material layer, the second strip structure, and the etched first strip structure, and a patterned second mask layer is formed on the upper surface of the third sacrificial layer. The second mask layer is exposed to the third sacrificial layer on the second strip structure, and the upper surface of the third sacrificial layer is flat;

A fourth sacrificial layer is formed on the third sacrificial layer and the patterned second mask layer, a second photoresist with a second window is formed on the fourth sacrificial layer, and a second photoresist with a second window is formed on the fourth sacrificial layer. The surface is flat, the second window defines the distance between two adjacent second gates in the gate length direction, and the length of the second window is equal to the length of the second photoresist in the gate width direction;

etching the fourth sacrificial layer, the third sacrificial layer and the second strip structure along the second window, and then removing the second photoresist, the third sacrificial layer, the fourth sacrificial layer and the patterned first Two mask layers.

Optionally, after forming the first gate and the second gate, further include:

The etched first strip structure and the etched second strip structure are removed.

Optionally, the projection of the second window on the base partially overlaps the projection of the first window on the base; or,

The projection of the second window on the substrate and the projection of the first window on the substrate are spaced apart from each other.

Optionally, the first sacrificial layer, the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer are silicon oxide layers, silicon nitride layers or silicon carbide layers.

Optionally, the patterned first mask layer and the patterned second mask layer are titanium nitride layers or silicon nitride layers.

Optionally, the material of the first strip structure and the second strip structure is titanium nitride or silicon nitride.

Optionally, before forming the first photoresist, a first hard mask layer and a first bottom anti-reflection layer are sequentially formed on the second sacrificial layer from bottom to top, and the first photoresist is formed on the on the first bottom antireflection layer.

Optionally, before forming the second photoresist, a second hard mask layer and a second bottom anti-reflection layer are sequentially formed on the fourth sacrificial layer from bottom to top, and the second photoresist is formed on the on the second bottom anti-reflection layer.

Optionally, the first hard mask layer and the second hard mask layer are titanium nitride layers or silicon nitride layers.

Optionally, the first bottom anti-reflection layer and the second bottom anti-reflection layer are organic bottom anti-reflection layers or inorganic bottom anti-reflection layers.

Optionally, the gate material layer is a polysilicon layer.

Optionally, before forming the gate material layer on the substrate, a gate dielectric layer is formed on the substrate, and the gate material layer is formed on the gate dielectric layer.

Optionally, the method for forming a plurality of first striped structures and second striped structures arranged in parallel on the gate material layer includes:

forming a strip structure material layer on the gate material layer;

forming a patterned photoresist on the strip structure material layer;

The patterned photoresist is used as a mask to etch the strip structure material layer to form a plurality of first strip structures and second strip structures arranged in parallel.

Optionally, before forming a patterned photoresist on the strip-shaped structural material layer, a third hard mask layer and a third bottom anti-reflective layer are sequentially formed on the strip-shaped structural material layer from bottom to top, The patterned photoresist is formed on the third BARC.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In this technical solution, a patterned first mask layer is used to expose the first sacrificial layer on the first strip structure, and the first photoresist with the first window is used as a mask to etch the first strip structure; The length of the first window is equal to the length of the first photoresist in the gate width direction, so the area of the first window is large, which can prevent the first window from being deformed or attaching residues during exposure and development. Furthermore, it is possible to prevent two adjacent etched first strip structures in the same column in the gate length direction from being connected to each other. Using the etched first strip structure as a mask, etch the gate material layer to form the first gate, two adjacent first gates in the same column in the gate length direction are separated from each other, preventing gate Two adjacent first gates in the same row in the longitudinal direction are connected to each other.

Further, the third sacrificial layer on the second strip structure is exposed by using the patterned second mask layer, and the second strip structure is etched by using the second photoresist with the second window as a mask. The length of the second window is equal to the length of the second photoresist in the gate width direction, so the second window has a large area, which can prevent the second window from deforming or attaching residues during exposure and development. Furthermore, it is possible to prevent two adjacent etched second strip structures in the same column in the gate length direction from being connected to each other. Using the etched second strip structure as a mask, etch the gate material layer to form the second gate, the two adjacent second gates in the same column in the gate length direction are separated from each other, preventing the gate Two adjacent second gates in the same row in the longitudinal direction are connected to each other.

Description of drawings

1 to 9B are schematic diagrams of various stages of gate formation in the prior art;

FIG. 10 to FIG. 25B are schematic diagrams of each fabrication stage for forming a gate in a specific embodiment of the present invention.

detailed description

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

This embodiment provides a method for forming the gate of a CMOS inverter. The gate is divided into a first gate and a second gate, and the first gate and the second gate are arranged periodically in the gate width direction. Each period There are two adjacent columns of first gates and two adjacent columns of second gates inside, and the first gates and the second gates are arranged staggered in the gate width direction; the forming method of the gate of the CMOS inverter include:

Referring to Figure 10, a substrate 110 is provided.

In a specific embodiment, the material of the substrate 110 is single crystal silicon, polycrystalline silicon, amorphous silicon or silicon-on-insulator. A source and a drain may be formed in the substrate 110 .

Referring to FIG. 11 , a gate material layer 120 is formed on the substrate 110 .

The method for forming the gate material layer 120 may be chemical vapor deposition, physical vapor deposition, atomic layer deposition or epitaxial growth. The gate material layer 120 may be a polysilicon layer.

In other embodiments, before forming the gate material layer 120 on the substrate 110 , a gate dielectric layer may be formed on the substrate 110 first, and then the gate material layer 120 may be formed on the gate dielectric layer.

Then on the gate material layer 120, a plurality of first strip structures and second strip structures arranged in parallel are formed, the first strip structures define the position of the first gate in the gate width direction, and the second strip structures The position of the second gate in the gate width direction is defined, that is, the gate width direction is perpendicular to the length direction of the first strip structure and the second strip structure.

A method of forming a plurality of first and second strip structures arranged in parallel includes:

Referring to FIG. 12 , a strip structure material layer 130 is formed on the gate material layer 120 .

The method for forming the strip-shaped structure material layer 130 may be other methods known in the art such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. For example, physical vapor deposition can use Ar and N2 plasma as sputtering ions, and the Ar and N2 plasma hits the same target material as the strip structure material layer 130, and the molecules in the target material are hit and separated from the target material, and the deposition On the gate material layer 120, a strip structure material layer 130 is formed.

In a specific embodiment, the strip structure material layer 130 is a titanium nitride layer or a silicon nitride layer.

Referring to FIG. 13A and FIG. 13B , a patterned photoresist 103 is formed on the strip structure material layer 130 .

FIG. 13B is a top view of the patterned photoresist 103, and FIG. 13A is a schematic diagram of a plane cut along the tangent line AA' in FIG. 13B.

In other embodiments, before forming the patterned photoresist 103 on the strip-shaped structure material layer 130, a third hard mask layer and a third hard mask layer are sequentially formed on the strip-shaped structure material layer 130 from bottom to top. Bottom anti-reflection layer, the patterned photoresist 103 is formed on the third bottom anti-reflection layer.

The function of the third hard mask layer is as a mask for etching the strip structure material layer 130, and the function of the third bottom anti-reflection layer is to reduce the reflection effect when forming the patterned photoresist 103, so as to Improve precise transfer of fine graphics.

When the strip-shaped structure material layer 130 is a titanium nitride layer, the third hard mask layer can be a silicon nitride layer or a low-temperature silicon oxide layer; when the strip-shaped structure material layer 130 is silicon nitride, the third hard mask layer The mask layer can be a titanium nitride layer or a low temperature silicon oxide layer. To ensure that the third hard mask layer can be used as a mask for etching the strip structure material layer 130 . The third bottom anti-reflection layer may be an organic bottom anti-reflection layer or an inorganic bottom anti-reflection layer.

14A and 14B, using the patterned photoresist 103 as a mask, etch the strip structure material layer 130 to form a plurality of first strip structures 131A and second strip structures arranged in parallel 131B. Then, the patterned photoresist 103 is removed.

The first strip structures 131A and the second strip structures 131B are arranged periodically in the gate width direction, and each period has two adjacent first strip structures 131A and two adjacent second strip structures 131B.

In this specific embodiment, adjacent means that there is no other structure in between. That is, two adjacent first strip structures 131A mean that no second strip structure 131B or other first strip structures 131A are formed between the two first strip structures 131A. Similarly, two adjacent second strip structures 131B mean that the first strip structure 131A or other second strip structures 131B are not formed between the two second strip structures 131B.

Fig. 14B is a top view of the first strip structure 131A and the second strip structure 131B, and Fig. 14A is a schematic diagram of a plane cut along the tangent line BB' in Fig. 14B. In order to distinguish, in FIG. 14A and FIG. 14B , the first strip structure 131A and the second strip structure 131B use different fillings.

The method of etching the strip structure material layer 130 may be a plasma etching method.

Referring to FIG. 15A and FIG. 15B , a first sacrificial layer 141 is formed on the first strip structure 131A, the second strip structure 131B and the gate material layer 120 , and the upper surface of the first sacrificial layer 141 is flat. The upper surface of the first sacrificial layer 141 is higher than the upper surfaces of the first strip structure 131A and the second strip structure 131B.

FIG. 15B is a top view of the first sacrificial layer 141 formed, and FIG. 15A is a schematic diagram of a plane cut along the tangent line CC' in FIG. 15B.

The method of forming the first sacrificial layer 141 is a spin coating method or a deposition method.

In a specific embodiment, the first sacrificial layer 141 is a silicon oxide layer, a silicon nitride layer or a silicon carbide layer, and the material of the first sacrificial layer 141 must be different from that of the strip structure material layer 130. When there is one sacrificial layer 141 , the first sacrificial layer 141 has a higher etching selectivity to the first strip structure 131A and the second strip structure 131B. For example, the material of the strip structure material layer 130 is silicon nitride, and the material of the first sacrificial layer 141 may be titanium nitride.

The function of the first sacrificial layer 141 is to provide a flat upper surface for subsequent formation of a patterned first mask layer.

Referring to FIG. 16A and FIG. 16B, a patterned first mask layer 151 is formed on the first sacrificial layer 141, and the patterned first mask layer 151 exposes the first sacrificial layer on the first strip structure 131A. Layer 141.

FIG. 16B is a top view of the patterned first mask layer 151, and FIG. 16A is a schematic diagram of a plane cut along the tangent line DD' in FIG. 16B.

The material of the patterned first mask layer 151 should be different from that of the first sacrificial layer 141 and the material layer 130 of the strip structure. And when etching the first sacrificial layer 141, the first strip structure 131A, and the second strip structure 131B, the first sacrificial layer 141 and the patterned first mask layer 151 have a higher etching selectivity ratio, and the first The strip structure 131A, the second strip structure 131B and the patterned first mask layer 151 also have a higher etching selectivity. For example, the material of the strip structure material layer 130 is silicon nitride, the material of the first sacrificial layer 141 is titanium nitride, and the material of the patterned first mask layer 151 can be low temperature silicon oxide.

In a specific embodiment, the method for forming the patterned first mask layer 151 includes:

forming a first mask material layer on the first sacrificial layer 141;

forming a patterned photoresist on the first mask material layer;

Using the patterned photoresist as a mask, etching the first mask material layer to form a patterned first mask layer 151;

The patterned photoresist is removed.

The function of forming the patterned first mask layer 151 is to protect the second striped structure 131B when etching the first striped structure 131A so that the second striped structure 131B is not etched.

Referring to FIG. 17A and FIG. 17B , a second sacrificial layer 142 is formed on the first sacrificial layer 141 and the patterned first mask layer 151 , and the upper surface of the second sacrificial layer 142 is flat. The upper surface of the second sacrificial layer 142 is higher than the upper surface of the patterned first mask layer 151 .

FIG. 17B is a top view of the second sacrificial layer 142 formed, and FIG. 17A is a schematic diagram of a plane cut along the tangent line EE' in FIG. 17B.

The material and forming method of the second sacrificial layer 142 can refer to the material and forming method of the first sacrificial layer 141 .

Referring to FIG. 18A and FIG. 18B, a first photoresist 101 having a first window 161 is formed on the second sacrificial layer 142, and the length direction of the first window 161 is perpendicular to the length of the first strip structure 131A. direction. The first window 161 defines the distance between two adjacent first gates in the gate length direction.

The gate length direction is parallel to the length directions of the first strip structure 131A and the second strip structure 131B.

FIG. 18B is a top view of the first photoresist 101 formed, and FIG. 18A is a schematic diagram of a plane cut along the tangent line FF' in FIG. 18B.

The length of the first window 161 is equal to the size of the first photoresist 101 in the gate width direction, that is, the first window 161 penetrates the entire first photoresist 101 in the gate width direction. Therefore, the area of the first window 161 is large, which can prevent the deformation of the first window 161 during exposure and development, and prevent residues from adhering to the side walls and bottom of the first window 161 .

Wherein the gate width direction is perpendicular to the gate length direction.

In other embodiments, before forming the first photoresist 101, a first hard mask layer and a first bottom anti-reflection layer may be sequentially formed on the second sacrificial layer 142 from bottom to top. A resist 101 is formed on the first bottom anti-reflection layer.

Wherein, the function of the first hard mask layer is as a mask for etching the second sacrificial layer 142, the first sacrificial layer 141 and the first strip structure 131A, and the function of the first bottom anti-reflection layer is to reduce the formation of the second sacrificial layer 142 A reflective effect of the photoresist 101 to improve the precise transfer of fine patterns.

When etching the second sacrificial layer 142, the first sacrificial layer 141 and the first strip-like structure 131A, the etching of the second sacrificial layer 142, the first sacrificial layer 141 and the first strip-like structure 131A and the second hard mask layer have High etch selectivity ratio. In a specific embodiment, the first hard mask layer is a titanium nitride layer or a silicon nitride layer; the first bottom anti-reflection layer may be an organic bottom anti-reflection layer or an inorganic bottom anti-reflection layer.

19A and 19B, etch the second sacrificial layer 142, the first sacrificial layer 141 and the first strip structure 131A along the first window 161; then remove the first photoresist 101, the second The sacrificial layer 142 , the first sacrificial layer 141 and the patterned first mask layer 151 .

Figure 19B is a top view after removing the first photoresist 101, the second sacrificial layer 142, the first sacrificial layer 141 and the patterned first mask layer 151, and Figure 19A is a plane cut along the tangent line GG' in Figure 19B schematic diagram.

Since the second strip structures 131B are covered by the patterned first mask layer 151 , the second strip structures 131B will not be etched.

Since the first strip structures 131A are not covered by the patterned first mask layer 151 , each first strip structure 131A is etched into several small segments. Each first strip structure 131A in FIG. 19B is etched into a small segment 132 and a small segment 133 .

Since the first window 161 will not be deformed, and there is no residue attached to the sidewall and bottom of the first window 161, when the first strip structure 131A is etched through the first window 161, the exposed first strip structure 131A can be completely removed. Etching can prevent two adjacent etched first strip structures in the same column in the gate length direction from being connected to each other. Adjacent segments are completely separated and do not connect to each other. That is, the small segment 132 and the small segment 133 are completely separated.

Moreover, the first window 161 has a large area and a good shape, which can reduce the line edge roughness of the small segments 132 and 133 formed after etching the first strip structure 131A.

Then, the second strip structure 131B is etched, and the etched second strip structure defines the position of the second gate. The method for etching the second strip structure 131B includes:

Referring to FIG. 20A and FIG. 20B, a third sacrificial layer 143 is formed on the gate material layer 120, the etched first strip structure 131A and the second strip structure 131B, and the upper surface of the third sacrificial layer 143 flat.

FIG. 20B is a top view of the third sacrificial layer 143 formed, and FIG. 20A is a schematic diagram of a plane cut along the tangent line HH' in FIG. 20B .

The formation method and material of the third sacrificial layer 143 can refer to the formation method and material of the first sacrificial layer 141 .

The function of the third sacrificial layer 143 is to provide a flat surface for subsequent formation of a patterned second mask layer.

21A and 21B, a patterned second mask layer 152 is formed on the upper surface of the third sacrificial layer, and the patterned second mask layer 152 exposes the third sacrificial layer 143 on the second strip structure 131B. , the patterned second mask layer 152 covers the etched first strip structures 131A.

FIG. 21B is a top view of the patterned second mask layer 152, and FIG. 21A is a schematic diagram of a plane cut along the tangent line II' in FIG. 21B.

In a specific embodiment, the method for forming the patterned second mask layer 152 includes:

forming a second mask material layer on the third sacrificial layer 143;

forming a patterned photoresist on the second mask material layer;

Using the patterned photoresist as a mask, etching the second mask material layer to form a patterned second mask layer 152;

The patterned photoresist is removed.

The material of the patterned second mask layer 152 can refer to the material of the patterned first mask layer 151 .

Referring to FIG. 22A and FIG. 22B , a fourth sacrificial layer 144 is formed on the third sacrificial layer 143 and the patterned second mask layer 152 , and the upper surface of the fourth sacrificial layer 144 is flat.

FIG. 22B is a top view of the fourth sacrificial layer 144 formed, and FIG. 22A is a schematic diagram of a plane cut along the tangent line JJ' in FIG. 22B.

The formation method and material of the fourth sacrificial layer 144 can refer to the formation method and material of the first sacrificial layer 141 .

The function of the fourth sacrificial layer 144 is to provide a flat surface for subsequent formation of the second photoresist.

Referring to FIGS. 23A and 23B , a second photoresist 102 having a second window 162 is formed on the fourth sacrificial layer 144 , and the length direction of the second window 162 is parallel to the length direction of the first window 161 . The second window 162 defines the distance between two adjacent second gates in the gate length direction.

FIG. 23B is a top view of the second photoresist 102 formed, and FIG. 23A is a schematic diagram of a plane cut along the tangent line KK' in FIG. 23B.

The length of the second window 162 is equal to the length of the first window 161 , that is, the second window 162 runs through the entire second photoresist 102 in the length direction of the second window 162 . Therefore, the area of the second window 162 is large, which can prevent the deformation of the second window 162 during exposure and development, and prevent residues from adhering to the side walls and bottom of the second window 162 .

In other embodiments, before forming the second photoresist 102, a second hard mask layer and a second bottom anti-reflection layer may be sequentially formed on the fourth sacrificial layer 144 from bottom to top. A resist 102 is formed on the second BARC.

Wherein, the function of the second hard mask layer is as a mask for etching the second strip structure 131B, and the function of the second bottom anti-reflection layer is to reduce the reflection effect when forming the second photoresist 102, so as to improve Precise transfer of fine graphics.

The material of the second hard mask layer can refer to the material of the first hard mask layer. The second bottom anti-reflection layer may be an organic bottom anti-reflection layer or an inorganic bottom anti-reflection layer.

In this embodiment, the projection of the second window 162 on the base 110 and the projection of the first window 161 on the base 110 are separated from each other without overlapping. so that the first grid and the second grid are arranged in dislocation in the gate width direction.

In other embodiments, the projection of the second window 162 on the base 110 and the projection of the first window 161 on the base 110 may also partially overlap.

Referring to FIG. 24A and FIG. 24B , the fourth sacrificial layer 144 , the third sacrificial layer 143 and the second strip structure 131B are etched along the second window 162 . Then, the second photoresist 102 , the third sacrificial layer 143 , the fourth sacrificial layer 144 and the patterned second mask layer 152 are removed.

Figure 24B is a top view of the second photoresist 102, the third sacrificial layer 143, the fourth sacrificial layer 144 and the patterned second mask layer 152 removed, and Figure 24A is a plane cut along the tangent line LL' in Figure 24B schematic diagram.

Since the etched first strip structures 131A are covered by the patterned second mask layer 152 , the etched first strip structures 131A will not be etched.

Since the second strip structures 131B are not covered by the patterned second mask layer 152 , each second strip structure 131B is etched into several small segments. Referring to FIG. 24B , each second strip structure 131B is etched into a small segment 134 , a small segment 135 and a small segment 136 .

Since the second window 162 will not be deformed, and there is no residue attached to the sidewall and bottom of the second window 162, when the second strip structure 131B is etched through the second window 162, the exposed second strip structure 131B can be completely removed. Etching can prevent two adjacent etched second strip structures in the same column in the gate length direction from being connected to each other. That is, the small segment 134, the small segment 135 and the small segment 136 are completely separated from each other.

Moreover, the second window 162 has a large area and a better shape, which can reduce the line edge roughness of the small segments 134 , 135 and 136 formed after etching the second strip structure 131B.

25A and 25B, using the etched first strip structure 131A and the etched second strip structure 131B as a mask, etch the gate material layer 120 to form the first gate 121A and the second gate 121B. And remove the etched first strip structure 131A and the etched second strip structure 131B.

Fig. 25B is a top view of the first gate 121A and the second gate 121B formed, and Fig. 25A is a schematic diagram of a plane cut along the tangent line MM' in Fig. 25B.

Since the small segments in the etched first strip structure 131A and the etched second strip structure 131B are all separated from each other, and the line edge roughness is small; the etched first strip structure 131A and the etched The etched second strip structure 131B serves as a mask, which prevents two adjacent first gates 121A in the same column in the gate length direction from being connected to each other, and also prevents two adjacent second gates 121B in the same column in the gate length direction. And the line edge roughness of the first gate 121A and the second gate 121B is small.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (14)

1. A method for forming the grid of a CMOS inverter, the grid is divided into a first grid and a second grid, and the first grid and the second grid are periodically arranged in the gate width direction, and each period has There are two adjacent columns of first grids and two adjacent columns of second grids, and the first grids and the second grids are staggered in the grid width direction; it is characterized in that the method includes: A substrate is provided, a gate material layer is formed on the substrate, a plurality of first strip structures and second strip structures arranged in parallel are formed on the gate material layer, the first strip structures define a first gate At the position in the gate width direction, the second strip structure defines the position of the second gate in the gate width direction; A first sacrificial layer is formed on the first strip structure, the second strip structure and the gate material layer, a patterned first mask layer is formed on the first sacrificial layer, and the first sacrificial layer The upper surface is flat, and the patterned first mask layer covers the first sacrificial layer on the second strip structure and exposes the first sacrificial layer on the first strip structure; A second sacrificial layer is formed on the first sacrificial layer and the patterned first mask layer, a first photoresist with a first window is formed on the second sacrificial layer, and the upper surface of the second sacrificial layer is flat , the first window defines the distance between two adjacent first gates in the gate length direction, and the length of the first window is equal to the length of the first photoresist in the gate width direction; etching the second sacrificial layer, the first sacrificial layer and the first strip structure along the first window, and then removing the first photoresist, the second sacrificial layer, the first sacrificial layer and the patterned first sacrificial layer; a mask layer; Etching the second strip structure, the etched second strip structure defines the position of the second gate, the method for etching the second strip structure includes: in the gate material layer, the second A third sacrificial layer is formed on the striped structure and the etched first striped structure, and a patterned second mask layer is formed on the upper surface of the third sacrificial layer, and the patterned second mask layer covers the first The third sacrificial layer on the strip structure and expose the third sacrificial layer on the second strip structure, the upper surface of the third sacrificial layer is flat; on the third sacrificial layer and the patterned second mask layer Forming a fourth sacrificial layer, forming a second photoresist with a second window on the fourth sacrificial layer, the upper surface of the fourth sacrificial layer is flat, and the second window defines two adjacent second windows in the direction of gate length. The distance between the two gates, the length of the second window is equal to the length of the second photoresist in the gate width direction; the fourth sacrificial layer, the third sacrificial layer and the second strip are etched along the second window shape structure, and then remove the second photoresist, the third sacrificial layer, the fourth sacrificial layer and the patterned second mask layer; Using the etched first strip structure and the etched second strip structure as a mask, the gate material layer is etched to form a first gate and a second gate. 2. The method for forming the CMOS inverter gate as claimed in claim 1, further comprising: after forming the first gate and the second gate: The etched first strip structure and the etched second strip structure are removed. 3. The method for forming the gate of a CMOS inverter according to claim 1, wherein the projection of the second window on the substrate partially overlaps the projection of the first window on the substrate; or, The projection of the second window on the substrate and the projection of the first window on the substrate are spaced apart from each other. 4. The forming method of CMOS inverter gate as claimed in claim 1, characterized in that, the first sacrificial layer, the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer are silicon oxide layer, silicon nitride layer or SiC layer. 5. The forming method of CMOS inverter gate as claimed in claim 1, characterized in that, the patterned first mask layer and the patterned second mask layer are titanium nitride layer or silicon nitride layer . 6 . The method for forming the gate of a CMOS inverter according to claim 1 , wherein the material of the first strip structure and the second strip structure is titanium nitride or silicon nitride. 7. The method for forming a CMOS inverter gate as claimed in claim 1, wherein, before forming the first photoresist, a first hard mask layer is sequentially formed on the second sacrificial layer from bottom to top and a first bottom anti-reflection layer, the first photoresist is formed on the first bottom anti-reflection layer. 8. The method for forming a gate of a CMOS inverter according to claim 1 or 7, wherein, before forming the second photoresist, a second hard mask is sequentially formed on the fourth sacrificial layer from bottom to top. A film layer and a second bottom anti-reflection layer, the second photoresist is formed on the second bottom anti-reflection layer. 9 . The method for forming the gate of a CMOS inverter according to claim 8 , wherein the first hard mask layer and the second hard mask layer are titanium nitride layers or silicon nitride layers. 10 . The method for forming a CMOS inverter gate as claimed in claim 8 , wherein the first bottom anti-reflection layer and the second bottom anti-reflection layer are organic bottom anti-reflection layers or inorganic bottom anti-reflection layers. 11 . 11. The method for forming the gate of a CMOS inverter according to claim 1, wherein the gate material layer is a polysilicon layer. 12. The method for forming the CMOS inverter gate as claimed in claim 1 or 11, characterized in that, Before forming the gate material layer on the substrate, a gate dielectric layer is formed on the substrate, and the gate material layer is formed on the gate dielectric layer. 13. The forming method of CMOS inverter gate as claimed in claim 1, characterized in that, the method of forming a plurality of first strip structures and second strip structures arranged in parallel on the gate material layer include: forming a strip structure material layer on the gate material layer; forming a patterned photoresist on the strip structure material layer; The patterned photoresist is used as a mask to etch the strip structure material layer to form a plurality of first strip structures and second strip structures arranged in parallel. 14. The forming method of CMOS inverter gate as claimed in claim 13, characterized in that, before forming a patterned photoresist on the strip structure material layer, on the strip structure material layer A third hard mask layer and a third bottom anti-reflection layer are sequentially formed from bottom to top, and the patterned photoresist is formed on the third bottom anti-reflection layer.