CN104409409A - Method for improving SiC stress property of shallow trench isolation edge - Google Patents
Method for improving SiC stress property of shallow trench isolation edge Download PDFInfo
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- 238000002955 isolation Methods 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 title claims abstract description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 70
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 70
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 67
- 239000010703 silicon Substances 0.000 claims abstract description 67
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 32
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 32
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000001259 photo etching Methods 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 16
- 230000008569 process Effects 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 208000032750 Device leakage Diseases 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract description 3
- 238000000227 grinding Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000011160 research Methods 0.000 description 4
- 239000002800 charge carrier Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a method for improving SiC stress property of a shallow trench isolation edge. The step of forming a shallow trench isolation in a silicon substrate comprises the steps: depositing a silicon dioxide cushion layer with a first thickness and a silicon nitride cushion layer with a second thickness on the surface of the silicon substrate in sequence; secondly, with respect to the utilized photoetching process, choosing the first thickness of the silicon dioxide cushion layer to adjust the height of the shallow trench isolation to be formed, wherein the first thickness of the silicon dioxide cushion layer is chosen to satisfy the photoetching requirement; thirdly, actively photoetching and etching the silicon dioxide cushion layer, the silicon nitride cushion layer and the silicon substrate so as to form a groove in the silicon substrate; fourthly, filling silicon dioxide in the groove and flattening the filled silicon dioxide through chemical and mechanical grinding to form shallow trench isolation; and finally, peeling off the silicon nitride cushion layer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of method that optimization by bed course silicon nitride layer technique improves shallow groove isolation edge SiC stress performance.
Background technology
Along with developing rapidly of very large scale integration technology, the size of MOSFET element, in continuous reduction, generally includes the reduction of MOSFET element channel length, and the thinning grade of gate oxide thickness is to obtain device speed faster.But along with very large scale integration technology be developed to sub-micro level time, particularly when 90 nanometers and following technology node, reduce channel length and can bring series of problems, in order to control short-channel effect, the impurity with higher concentration can be mixed in channels, this can reduce the mobility of charge carrier, thus causes device performance to decline, and simple device size reduces to be difficult to the development meeting large scale integrated circuit technology.Therefore, the extensive research of stress engineering is used for improving the mobility of charge carrier, thus reaches device speed faster, and meets the rule of Moore's Law.
The eighties in last century, academia just started to realize heterostructure research based on silicon-based substrate, until just realize business application the beginning of this century to the nineties.Wherein have two kinds of representational stress application, one is biaxial stress technology (Biaxial Technique), another kind is simple stress technology (Uniaxial Technique), i.e. stress memory technique (Stress Memorization Technology), nCESL and selectivity (or embedding) epitaxial growth silicon-carbon SiC drain-source are (see document " K.W.Ang et al., IEDM Tech.Dig., pp.1069, 2004 " and document " Y.C.Liu et al., VLSI, pp.44-45, 2007 ") mobility that tensile stress improves electronics is applied to the raceway groove of NMOSFET, selectivity (or embedding) epitaxial growth Ge-Si SiGe, pCESL applies to PMOSFET raceway groove the mobility that compression improves hole, thus improve the performance of device, see Fig. 2.
At present, the research for SiC epitaxial growth technology mainly concentrates on the concentration how improving carbon in SiC, and the concentration of carbon is higher, and lattice mismatch is larger, and the stress of generation is larger, more remarkable to the raising of carrier mobility; In addition, the shape of SiC, SiC drain-source is close to the edge of polysilicon, and namely near device channel, stress more directly acts on the charge carrier of device channel, obvious to the lifting of device performance.
Research and development all are above all based on silicon substrate, that is, the seed that silicon substrate provides SiC to grow, SiC carries out epitaxial growth along the lattice of silicon, but, in semiconductor technology, electric isolation is realized by shallow ditch groove separation process (STI) between device, silicon dioxide is used to fill in STI, therefore at STI and active-surface, SiC epitaxy technique can be subject to the impact of STI, and STI can not provide enough silicon " seed ", just there will be STI edge, left and right sides SiC in SiC selective epitaxial process and grows and lowly even to lack.
Summary of the invention
Technical problem to be solved by this invention is for there is above-mentioned defect in prior art, provides a kind of method can being improved shallow groove isolation edge SiC stress performance by the optimization of bed course silicon nitride layer technique.
In order to realize above-mentioned technical purpose, according to the present invention, providing a kind of method improving shallow groove isolation edge SiC stress performance, comprising: in a silicon substrate formed carry out shallow trench isolation from; Carry out trap and inject formation N-type trap and/or P type trap; Make grid oxic horizon, perform the deposit of gate polycrystalline silicon materials, and the photoetching carrying out grid polycrystalline silicon forms grid; By the silicon dioxide layer of protection that atomic deposition generates; Make first grid side wall; Carry out PMOS light dope and inject formation PMOS device leakage light-dope structure; Carry out germanium and silicon epitaxial growth technique; Carry out NMOS light dope and inject formation nmos device leakage light-dope structure; Make second grid side wall, second grid side wall comprises SiO2 layer and SiN layer; Form NMOS source and drain SiC epitaxial region.
Preferably, in a silicon substrate formed carry out shallow trench isolation from step comprise: at the bed course silicon dioxide layer of surface of silicon successively deposit first thickness and the bed course silicon nitride layer of the second thickness; Wherein, for the photoetching process used, the shallow trench isolation selecting the first thickness of bed course silicon dioxide layer to regulate will to be formed from height, and select the first thickness of bed course silicon dioxide layer to meet etching condition; Then active area photoetching and etching are carried out to form groove in a silicon substrate to bed course silicon dioxide layer, bed course silicon nitride layer and silicon substrate; Subsequently in a groove fill silicon dioxide and by cmp to fill silicon dioxide carry out planarization with obtain shallow trench isolation from; Then bed course silicon nitride layer is peeled off.
Preferably, the second thickness of bed course silicon nitride layer is selected as the maximum ga(u)ge meeting etching condition, make thus shallow trench isolation from height maximize.
Preferably, formed in a silicon substrate carry out shallow trench isolation from step make shallow trench isolation from upper surface higher than the upper surface of silicon chip substrate.
Preferably, formed in a silicon substrate carry out shallow trench isolation from step make shallow trench isolation from upper surface be not less than the upper surface of silicon chip substrate.
Preferably, the step forming NMOS source and drain SiC epitaxial region comprises: first deposit grows the silicon nitride layer on barrier layer as SiC, utilize silicon nitride layer to carry out photoetching to define SiC region, then carry out wall embeded silicon dry etching to form U-type silicon groove for SiC region.
The thickness of reasonably optimizing bed course bed course silicon nitride layer of the present invention, thus control shallow trench isolation from silicon oxide layer surface to the thickness of active area silicon face, make it possible to neither affect photoetching, obtain again simultaneously rational shallow trench isolation from height, to control in follow-up SiC technique wall embeded silicon etching process to the loss situation of shallow trench isolated side wall silicon, enhance SiC epitaxial growth ability, improve SiC semiconductor manufacturing process ability.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows the difference in height of STI silicon oxide layer and active area silicon face.
Fig. 2 schematically shows the flow chart of the method improving shallow groove isolation edge SiC stress performance according to the preferred embodiment of the invention.
Fig. 3 to Fig. 6 schematically shows each step improving the method for shallow groove isolation edge SiC stress performance according to the present invention according to the preferred embodiment of the invention.
The different components structure that the bed course silicon nitride layer that Fig. 7 to Figure 10 schematically shows different-thickness obtains.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
By research, inventor advantageously finds, it is because shallow trench isolation causes from (STI) silicon oxide layer to the difference in height of active area silicon face that STI edge, left and right sides SiGe grows the low reason even lacked, when STI height is lower than device active region silicon AA surface, when carrying out wall embeded silicon etching process, silicon more than STI surface is all etched away, and provide silicon " seed " can not to follow-up SiC growth, causes and lowly even to lack as STI edge, left and right sides SiC grows.Therefore, as shown in Figure 1, the difference in height 12 of STI silicon oxide layer 20 and active area 10 silicon face, and STI edge silicon (as indicated by the dashed line in figure 1) number, most important to SiC technique.
In the present invention, by optimizing bed course silicon dioxide layer, control STI silicon oxide layer is to the thickness of active area silicon face, thus wall embeded silicon etching process (Si Recess Etch in control SiC technique, also referred to as silicon recess etch) loss to shallow trench isolated side wall silicon, strengthen SiC selective epitaxial growth ability, improve SiC semiconductor manufacturing process ability.
Fig. 2 schematically shows the flow chart of the method improving shallow groove isolation edge SiC stress performance according to the preferred embodiment of the invention.
Particularly, as shown in Figure 2, the method improving shallow groove isolation edge SiC stress performance according to the preferred embodiment of the invention comprises:
First carry out step S10, formed in silicon substrate 10 and carry out shallow trench isolation from 20.
Step S10 specifically can comprise the steps:
First the bed course silicon dioxide layer 1 of deposit first thickness and the bed course silicon nitride layer 2 (as shown in Figure 3) of the second thickness successively on silicon substrate 10 surface; Wherein, for the photoetching process used, the shallow trench isolation selecting the first thickness of bed course silicon dioxide layer 1 to regulate will to be formed from height, and select the first thickness of bed course silicon dioxide layer 1 to meet etching condition; Such as, preferably, the second thickness of bed course silicon nitride layer 2 is selected as meeting the maximum ga(u)ge (can obtain thus maximum shallow trench isolation under present case from height) of etching condition;
Then active area photoetching and etching are carried out to form groove 3 (as shown in Figure 4) in silicon substrate 10 to bed course silicon dioxide layer 1, bed course silicon nitride layer 2 and silicon substrate 10;
In groove 3, fill silicon dioxide subsequently and by cmp, planarization carried out to obtain shallow trench isolation from 20 (as shown in Figure 5) to the silicon dioxide of filling;
Then bed course silicon nitride layer 2 (as shown in Figure 6) is peeled off.
As shown in Figure 7 to 10, thicker bed course silicon nitride layer 2 can obtain the height of higher STI oxide layer.Fig. 7 and Fig. 8 show bed course silicon nitride layer 2 thickness relatively little time STI oxide layer height (as shown in the double-head arrow in Fig. 8), Fig. 9 and Figure 10 show bed course silicon nitride layer 2 thickness relatively large time STI oxide layer height (as shown in the double-head arrow in Fig. 8).
Preferably, formed in silicon substrate 10 and carry out upper surface that the step of shallow trench isolation from 20 make shallow trench isolation from 20 upper surface higher than silicon chip substrate.
Then carry out step S11, carry out trap and inject formation N-type trap and/or P type trap.
Then carry out step S12, make grid oxic horizon, perform the deposit of gate polycrystalline silicon materials, and the photoetching carrying out grid polycrystalline silicon forms grid.
Then continue step S13, the silicon dioxide layer of protection generated by atomic deposition, the silicon face of protection device, reduce the loss of surface silicon.
Then continue step S14, alternatively, perform light dope for input and output device region and inject the leakage light-dope structure forming peripheral input and output device.
Then continue step S15, make first grid side wall; Such as, the material of first grid side wall is SiN; Particularly, the step such as making first grid side wall comprises deposit and the etching of SiN.
Then continue step S16, carry out PMOS light dope and inject formation PMOS device leakage light-dope structure.
Then continue step S17, carry out germanium and silicon epitaxial growth technique.
Then continue step S18, carry out NMOS light dope and inject formation nmos device leakage light-dope structure.
Then continue step S19, make second grid side wall, second grid side wall comprises SiO
2layer and SiN layer; Such as, the formation of second grid side wall comprises deposit and the etching of many SiO2 and SiN.
Then continue step S20, form NMOS source and drain SiC epitaxial region.Wherein, first deposit is as the silicon nitride layer on SiC growth barrier layer, utilizes silicon nitride layer to carry out photoetching to define SiC region, then carries out wall embeded silicon dry etching to form U-type silicon groove for SiC region.
When STI upper surface is lower than active area silicon face, all silicon higher than STI upper surface all will be etched, and SiC can grow at STI edge SiC and lowly even to lack.When STI upper surface is higher than active area silicon face, STI oxide layer can be protected the silicon of its edge sidewall, as the scope that Fig. 1 dotted line is irised out, decreases the loss of STI sidewall silicon, strengthens SiC epitaxial growth ability, improves SiC semiconductor manufacturing process ability.
Then continue step S21, carry out source and drain and inject formation source-drain electrode.
Then pre-metal dielectric, through hole, metal plug and metal level is made.
The thickness of reasonably optimizing bed course bed course silicon nitride layer of the present invention, thus control shallow trench isolation from silicon oxide layer surface to the thickness of active area silicon face, make it possible to neither affect photoetching, obtain again simultaneously rational shallow trench isolation from height, to control in follow-up SiC technique wall embeded silicon etching process to the loss situation of shallow trench isolated side wall silicon, enhance SiC epitaxial growth ability, improve SiC semiconductor manufacturing process ability.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (8)
1. improve a method for shallow groove isolation edge SiC stress performance, it is characterized in that comprising:
In a silicon substrate formed carry out shallow trench isolation from;
Carry out trap and inject formation N-type trap and/or P type trap;
Make grid oxic horizon, perform the deposit of gate polycrystalline silicon materials, and the photoetching carrying out grid polycrystalline silicon forms grid;
By the silicon dioxide layer of protection that atomic deposition generates.
2. the method improving shallow groove isolation edge SiC stress performance according to claim 1, characterized by further comprising:
Make first grid side wall;
Carry out PMOS light dope and inject formation PMOS device leakage light-dope structure;
Carry out germanium and silicon epitaxial growth technique;
Carry out NMOS light dope and inject formation nmos device leakage light-dope structure;
Make second grid side wall, second grid side wall comprises SiO2 layer and SiN layer;
Form NMOS source and drain SiC epitaxial region.
3. the method improving shallow groove isolation edge SiC stress performance according to claim 1 and 2, is characterized in that, in a silicon substrate formed carry out shallow trench isolation from step comprise:
At the bed course silicon dioxide layer of surface of silicon successively deposit first thickness and the bed course silicon nitride layer of the second thickness; Wherein, for the photoetching process used, the shallow trench isolation selecting the first thickness of bed course silicon dioxide layer to regulate will to be formed from height, and select the first thickness of bed course silicon dioxide layer to meet etching condition;
Then active area photoetching and etching are carried out to form groove in a silicon substrate to bed course silicon dioxide layer, bed course silicon nitride layer and silicon substrate;
Subsequently in a groove fill silicon dioxide and by cmp to fill silicon dioxide carry out planarization with obtain shallow trench isolation from;
Then bed course silicon nitride layer is peeled off.
4. the method improving shallow groove isolation edge SiC stress performance according to claim 3, is characterized in that, the second thickness of bed course silicon nitride layer is selected as the maximum ga(u)ge meeting etching condition, make thus shallow trench isolation from height maximize.
5. the method improving shallow groove isolation edge SiC stress performance according to claim 1 and 2, is characterized in that, formed in a silicon substrate carry out shallow trench isolation from step make shallow trench isolation from upper surface higher than the upper surface of silicon chip substrate.
6. the method improving shallow groove isolation edge SiC stress performance according to claim 1 and 2, is characterized in that, formed in a silicon substrate carry out shallow trench isolation from step make shallow trench isolation from upper surface be not less than the upper surface of silicon chip substrate.
7. the method improving shallow groove isolation edge SiC stress performance according to claim 1 and 2, it is characterized in that, the step forming NMOS source and drain SiC epitaxial region comprises: first deposit grows the silicon nitride layer on barrier layer as SiC, utilize silicon nitride layer to carry out photoetching to define SiC region, then carry out wall embeded silicon dry etching to form U-type silicon groove for SiC region.
8. the method improving shallow groove isolation edge SiC stress performance according to claim 1 and 2, is characterized in that, described method is for the manufacture of MOS transistor.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090090941A1 (en) * | 2007-10-09 | 2009-04-09 | Fujitsu Microelectronics Limited | Semiconductor device and method of manufacturing the same |
| CN101996949A (en) * | 2009-08-11 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102074461A (en) * | 2009-10-30 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of fabricating same |
| CN103050443A (en) * | 2011-10-13 | 2013-04-17 | 国际商业机器公司 | Improving performance and reducing variation of narrow channel devices |
| CN103779224A (en) * | 2012-10-23 | 2014-05-07 | 中国科学院微电子研究所 | MOSFET manufacturing method |
| US20140264444A1 (en) * | 2013-03-13 | 2014-09-18 | International Business Machines Corporation | Stress-enhancing selective epitaxial deposition of embedded source and drain regions |
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- 2014-11-19 CN CN201410664583.8A patent/CN104409409A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090090941A1 (en) * | 2007-10-09 | 2009-04-09 | Fujitsu Microelectronics Limited | Semiconductor device and method of manufacturing the same |
| CN101996949A (en) * | 2009-08-11 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102074461A (en) * | 2009-10-30 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of fabricating same |
| CN103050443A (en) * | 2011-10-13 | 2013-04-17 | 国际商业机器公司 | Improving performance and reducing variation of narrow channel devices |
| CN103779224A (en) * | 2012-10-23 | 2014-05-07 | 中国科学院微电子研究所 | MOSFET manufacturing method |
| US20140264444A1 (en) * | 2013-03-13 | 2014-09-18 | International Business Machines Corporation | Stress-enhancing selective epitaxial deposition of embedded source and drain regions |
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Application publication date: 20150311 |
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