CN104409093B - The transistor memory unit of difference 10 of anti-single particle reversion - Google Patents
The transistor memory unit of difference 10 of anti-single particle reversion Download PDFInfo
- Publication number
- CN104409093B CN104409093B CN201410742432.XA CN201410742432A CN104409093B CN 104409093 B CN104409093 B CN 104409093B CN 201410742432 A CN201410742432 A CN 201410742432A CN 104409093 B CN104409093 B CN 104409093B
- Authority
- CN
- China
- Prior art keywords
- pmos
- storage node
- cross
- nmos
- linked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention belongs to integrated circuit memory technical field, specially a kind of transistor memory unit of difference 10 of anti-single particle reversion.Its cellular construction include two couples of cross-linked PMOS to, two pairs cross-linked NMOS pairs and a pair of NMOS transfer tubes, and contain the storage nodes of 4 interlockings.Wherein, first and second storage nodes by first couple of cross-linked PMOS to interlocking；First and the 3rd storage node by first couple of cross-linked NMOS to interlocking；Second and the 4th storage node by second couple of cross-linked NMOS to interlocking；Third and fourth storage node is by second couple of cross-linked PMOS to interlocking；When memory cell is disturbed by single event, the storage node of interlocking can effectively resist single-particle interference, and the data of protection storage are not inverted.With the present invention has same difference reading and writing mode of operation 6 transistor memory units as, but eliminates the bad and semi-selection of reading a character with two or more ways of pronunciation that 6 transistor memory units often occur and destroys.
Description
Technical field
Technical field is set the invention belongs to integrated circuit memory, and in particular to a kind of register file (Register
) and SRAM (Static Random Access Memory, SRAM) unit File.
Background technology
With the diminution of process, the electric capacity of signal node is less and less, and node capacitance stored charge is also therewith
Less and less, this causes signal node to become increasingly susceptible to the interference of single event.Caused by single event interference
Chip error is generally termed soft error (soft error), and this is random caused by being a kind of impact because of high energy particle, do not weigh
Existing non-permanent mistake.
In the encapsulating material of chip, there is a small amount of radioactive element uranium, thorium, they produce α in decay process
Son, when α particles impact signal node, can produce high energy electron pulse, so that reverse signal moment.With the development of technique,
The material of encapsulation is more and more purer so that soft error rate is more and more lower caused by encapsulation.But, at present, the height from space
Moderate energy neutron is the main source of chip soft error.For the chip applied to Aero-Space, it occurs the probability of soft error
Three orders of magnitude are at least higher by than ground chip.
In chip, logic circuit and memory are all vulnerable to the interference of single event, but for memory, it is special
It is not SRAM, due to its high density and does not have mask mechanism so that it is more easy to occur soft error.Therefore, resist
Soft error SRAM is particularly important.
Design all tendency using support position interleaving function SRAM, add the error correcting code (error of unit
Correction code, ECC) realize anti-soft error SRAM.For example, 2009, author I. J. Chang,
Magazine " delivers " 32 kb 10T sub-threshold SRAM in Journal of Solid-State Circuits "
The nm CMOS " of array with bit-interleaving and differential read scheme in 90, are proposed
There is the subthreshold value 10TSRAM of position interleaving function；2011, author Do Anh-Tuan were in magazine " Transaction on
Circuits and Systems-I:" An 8T Differential SRAM With are delivered in Regular Papers "
The nm CMOS " of Improved Noise Margin for Bit-Interleaving in 65, equally propose each use
Hand over 8 transistor memory units in the position of AND structures., author Ming-Hsien Tu, in magazine " Journal of in 2012
" A Single-Ended Disturb-Free 9T Subthreshold SRAM are delivered in Solid-State Circuits "
With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and
Adaptive Read Operation Timing Tracing " a, it is proposed that subthreshold value with position interleaving function
9TSRAM。
But, these SRAM can only solve the problems, such as the soft error of unit data, and need the association of ECC
Help, for the soft error of multidigit, then need to be specifically designed the SRAM of anti-single particle reversion.
The content of the invention
Store single it is an object of the invention to provide a kind of 10 pipes of the anti-single particle reversion with higher reading and writing stability
Member.
10 transistor memory units of the anti-single particle reversion that the present invention is provided, including：Two pairs cross-linked PMOS pairs, two pairs
Cross-linked NMOS pairs, and a pair of NMOS transfer tubes, the storage node of 4 mutually lockings.Wherein：
The grid of first PMOS is connected with the drain electrode of second PMOS, the grid of second PMOS and first
The drain electrode of PMOS is connected, and their source electrodes are connected with power vd D, constitutes first pair cross-linked PMOS pairs；First NMOS
The grid of pipe is connected with the drain electrode of second NMOS tube, and the grid of second NMOS tube is connected with the drain electrode of first NMOS tube,
Their source electrodes are connected with ground GND, constitute first pair cross-linked NMOS pairs；The grid and the 4th NMOS of 3rd NMOS tube
The drain electrode of pipe is connected, and the grid of the 4th NMOS tube is connected with the drain electrode of the 3rd NMOS tube, and their source electrodes are connected with ground GND,
Constitute second pair cross-linked NMOS pairs；The grid of 3rd PMOS is connected with the drain electrode of the 4th PMOS, the 4th
The grid of PMOS is connected with the drain electrode of the 3rd PMOS, and their source electrodes are connected with power vd D, constitutes second pair of cross-couplings
PMOS pairs；
Also, first storage node and second storage node are mutual to carrying out by first couple of cross-linked PMOS
Lock；First storage node and the 3rd storage node are by first couple of cross-linked NMOS to interlocking；Second is deposited
Node and the 4th storage node are stored up by second couple of cross-linked NMOS to interlocking；3rd storage node and the 4th
Individual storage node is by second couple of cross-linked PMOS to interlocking；The value of first storage node storage is equal to the 4th
The value of storage node storage, the value of second storage node storage is equal to the value of the 3rd storage node storage；
Meanwhile, two NMOS transfer tubes by wordline WL control, and their source electrode respectively with first storage node and
Second storage node is connected, and drain electrode is connected with bit line BL and paratope line BLB respectively, constitutes the reading and writing circuit of memory cell.
When memory cell is disturbed by single event, storage node interlocked with one another can effectively resist single-particle
Interference, the data of protection storage are not inverted.Also, it and 6 traditional transistor memory units have same difference reading and writing operation
Mode, but eliminate that 6 transistor memory units often occur reads a character with two or more ways of pronunciation the destruction of bad and semi-selection.
The anti-single particle reversion memory cell that the present invention is provided can effectively resist soft error, and with higher
Reading and writing stability.
Brief description of the drawings
Fig. 1 is the electrical block diagram of the present invention.
Fig. 2 is that the present invention deposits the circuit operation schematic diagram that " 1 " node is disturbed by single-particle.
Fig. 3 is that the present invention deposits the circuit operation schematic diagram that " 0 " node is disturbed by single-particle.
Fig. 4 is reading circuit operation chart of the present invention.
Embodiment
The present invention describes a kind of 10 transistor memory units of anti-single particle reversion, design philosophy of the invention set forth below and
Example.
Fig. 1 show the anti-single particle 10 transistor memory unit circuit structures of reversion that the present invention is realized.PMOS 301 and 302
First couple of cross-linked PMOS is constituted to 311, PMOS 307 and 308 constitutes second couple of cross-linked PMOS to 341,
NMOS tube 303 and 304 constitutes first couple of cross-linked NMOS to 321, and NMOS tube 305 and 306 constitutes second pair of cross-couplings
NMOS to 331, NMOS tube 309 and 310 is two transfer tubes, and 320,330,340 and 350 be the storage of four mutually lockings
Node.Wherein, the grid of PMOS 301 is connected with the drain electrode of PMOS 302, grid and the PMOS 301 of the pipe of PMOS 302
Drain electrode be connected, their source electrodes are connected with power vd D, cross coupled with one another；The grid of NMOS tube 303 and the leakage of NMOS tube 304
Extremely it is connected, the grid of NMOS tube 304 is connected with the drain electrode of NMOS tube 303, their source electrodes are connected with ground GND, cross coupled with one another
's；The grid of NMOS tube 305 is connected with the drain electrode of NMOS tube 306, and the grid of NMOS tube 306 is connected with the drain electrode of NMOS tube 305,
Their source electrodes are connected with ground GND, cross coupled with one another；The grid of PMOS 307 is connected with the drain electrode of PMOS 308, PMOS
308 grid is connected with the drain electrode of PMOS 307, and their source electrodes are connected with power vd D, cross coupled with one another.Also, first
Storage node 320 and second storage node 330 are interlocked by first couple of cross-linked PMOS to 311；First is deposited
Storage node 320 and the 3rd storage node 340 are interlocked by first couple of cross-linked NMOS to 321；Second storage
Node 330 and the 4th storage node 350 are interlocked by second couple of cross-linked NMOS to 331；3rd storage knot
Point 340 and the 4th storage node 350 are interlocked by second couple of cross-linked PMOS to 341.First storage node
The value of 320 storages is equal to the value that the 4th storage node 350 is stored, and the value that second storage node 330 is stored is equal to the 3rd
The value that storage node 340 is stored.Meanwhile, two NMOS transfer tubes are controlled by wordline WL, and their source electrode is respectively with first
Individual storage node 320 is connected with second storage node 330, and drain electrode is connected with bit line BL and paratope line BLB respectively, and composition is deposited
The reading and writing circuit of storage unit.
Fig. 2 represents that the present invention deposits the circuit operation that " 1 " node is disturbed by single-particle.Now, the value that node 320 and 350 is deposited
For " 1 ", the value that node 330 and 340 is deposited is " 0 ".If node 320 is disturbed by single-particle, a negative pulse is produced, then it is from " 1 "
Instantaneous abrupt change is " 0 ".Due to this saltus step, PMOS 302 is opened, and starts to charge to storage node 330, due to storage node 340
Isolate with 350 with occurring the node of saltus step, so the value that they are stored is unaffected.Therefore, NMOS tube 305 is in all the time
Opening, is pulled down to node 330, then now node 330 has the charging of PMOS and the electric discharge of NMOS tube simultaneously, is produced
Raw larger short circuit current flow, it is possible to produce the positive current pulses of moment.After the single event of moment terminates, PMOS pair
330 charging weakens, then node 330 is pulled original " 0 " state again, then, occurs the node 320 that single-particle hits
One state is retracted by PMOS 301.This whole process continues more of short duration, and the storage node of interlocking causes whole memory cell
It can recover after single-particle shock.
Fig. 3 represents that the memory cell of the present invention deposits the circuit operation that " 0 " node is disturbed by single-particle.Now, the He of node 320
350 values deposited are " 0 ", and the value that node 330 and 340 is deposited is " 1 ".If node 320 is disturbed by single-particle, a positive pulse is produced,
Then its from " 0 " instantaneous abrupt change be " 1 ".Due to this saltus step, NMOS tube 304 is opened, and starts to discharge to storage node 340, due to depositing
Storage node 330 and 350 is isolated with occurring the node of saltus step, so the value that they are stored is unaffected.Therefore, NMOS tube
307 are in opening all the time, node 340 are carried out to fill the people, then now node 340 has charging and the NMOS of PMOS simultaneously
The electric discharge of pipe, produces larger short circuit current flow, it is possible to produce the negative current pulse of moment.Treat that the single event of moment terminates
Afterwards, NMOS tube weakens to 340 charging, then node 340 is filled back original one state again, then, occurs single-particle and hits
Node 320 " 0 " state is also retracted by NMOS tube 303.This whole process continues more of short duration, and the storage node of interlocking causes whole
Individual memory cell can be recovered after single-particle shock.So, no matter what value that the present invention is stored, done by single-particle
It can recover when disturbing from interference, effectively resist the generation of soft error.
Fig. 4 represents the circuit operation under the memory cell reading mode of the present invention.When memory cell carries out read operation, wordline WL
For height, BL preliminary fillings are high and floating.The data of difference are read on bit line by 309,303 and 310,305.In read operation process
In, due to the presence of process deviation, the magnitude of voltage of node 320 or 330 is likely to be breached a high level, but due to other storage knots
Point is isolated with participating in the node of read operation, so the value of other storage nodes is interference-free.After read operation terminates,
Be disturbed the value of node storage equally can retract original state by other undisturbed nodes.And in traditional memory cell
In, because this read a character with two or more ways of pronunciation that process deviation is produced can not badly avoid.Therefore, in other words, the present invention completely eliminate read a character with two or more ways of pronunciation it is bad, when
The semi-selection caused by reading a character with two or more ways of pronunciation badly is so also eliminated to destroy.
Claims (1)
1. a kind of 10 transistor memory units of anti-single particle reversion, it is characterised in that including：Two pairs cross-linked PMOS pairs, two
To cross-linked NMOS pairs, a pair of NMOS transfer tubes, the storage node of 4 mutually lockings；Wherein：
The grid of first PMOS is connected with the drain electrode of second PMOS, the grid and first PMOS of second PMOS
The drain electrode of pipe is connected, and their source electrodes are connected with power vd D, constitutes first pair cross-linked PMOS pairs；First NMOS tube
Grid is connected with the drain electrode of second NMOS tube, and the grid of second NMOS tube is connected with the drain electrode of first NMOS tube, they
Source electrode is connected with ground GND, constitutes first pair cross-linked NMOS pairs；The grid of 3rd NMOS tube and the 4th NMOS tube
Drain electrode is connected, and the grid of the 4th NMOS tube is connected with the drain electrode of the 3rd NMOS tube, and their source electrodes are connected with ground GND, constitute
Second pair cross-linked NMOS pairs；The grid of 3rd PMOS is connected with the drain electrode of the 4th PMOS, the 4th PMOS
The grid of pipe is connected with the drain electrode of the 3rd PMOS, and their source electrodes are connected with power vd D, and second pair of composition is cross-linked
PMOS pairs；
Also, first storage node and second storage node are by first couple of cross-linked PMOS to interlocking；The
One storage node and the 3rd storage node are by first couple of cross-linked NMOS to interlocking；Second storage node
With the 4th storage node by second couple of cross-linked NMOS to interlocking；3rd storage node and the 4th storage
Node is by second couple of cross-linked PMOS to interlocking；The value of first storage node storage is equal to the 4th storage knot
The value of point storage, the value of second storage node storage is equal to the value of the 3rd storage node storage；
Meanwhile, two NMOS transfer tubes are controlled by wordline WL；The source electrode of one of them of two NMOS transfer tubes is deposited with first
Store up node to be connected, another source electrode is connected with second storage node；The drain electrode of one of them of two NMOS transfer tubes with
Bit line BL is connected, and another drain electrode is connected with paratope line BLB；Constitute the reading and writing circuit of memory cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410742432.XA CN104409093B (en) | 2014-12-09 | 2014-12-09 | The transistor memory unit of difference 10 of anti-single particle reversion |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410742432.XA CN104409093B (en) | 2014-12-09 | 2014-12-09 | The transistor memory unit of difference 10 of anti-single particle reversion |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104409093A CN104409093A (en) | 2015-03-11 |
| CN104409093B true CN104409093B (en) | 2017-07-28 |
Family
ID=52646714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410742432.XA Active CN104409093B (en) | 2014-12-09 | 2014-12-09 | The transistor memory unit of difference 10 of anti-single particle reversion |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104409093B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328210B (en) * | 2015-06-17 | 2019-10-08 | 复旦大学 | A kind of preparation method of Anti-radioactive Fault-tolerant storage unit |
| CN108831515A (en) * | 2018-05-17 | 2018-11-16 | 上海华虹宏力半导体制造有限公司 | SRAM memory cell |
| CN109872747A (en) * | 2019-01-10 | 2019-06-11 | 中国人民武装警察部队海警学院 | A kind of 10 transistor memory unit of subthreshold value for supporting column selection structure |
| CN110047535B (en) * | 2019-03-20 | 2021-01-22 | 上海华虹宏力半导体制造有限公司 | SRAM memory cell |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101635169A (en) * | 2008-07-23 | 2010-01-27 | 台湾积体电路制造股份有限公司 | Sram with improved read/write stability |
| CN102169718A (en) * | 2011-01-28 | 2011-08-31 | 中国航天科技集团公司第九研究院第七七一研究所 | Anti-single event upset performance reinforced static memory unit |
| CN103021456A (en) * | 2012-12-19 | 2013-04-03 | 电子科技大学 | Nonvolatile high-resistance single-particle configuration memory unit |
| CN103366802A (en) * | 2013-06-26 | 2013-10-23 | 清华大学 | Static random storage unit |
| CN103956183A (en) * | 2014-04-24 | 2014-07-30 | 中国科学院微电子研究所 | Radiation-resistant SRAM cell |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7872903B2 (en) * | 2009-03-19 | 2011-01-18 | Altera Corporation | Volatile memory elements with soft error upset immunity |
-
2014
- 2014-12-09 CN CN201410742432.XA patent/CN104409093B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101635169A (en) * | 2008-07-23 | 2010-01-27 | 台湾积体电路制造股份有限公司 | Sram with improved read/write stability |
| CN102169718A (en) * | 2011-01-28 | 2011-08-31 | 中国航天科技集团公司第九研究院第七七一研究所 | Anti-single event upset performance reinforced static memory unit |
| CN103021456A (en) * | 2012-12-19 | 2013-04-03 | 电子科技大学 | Nonvolatile high-resistance single-particle configuration memory unit |
| CN103366802A (en) * | 2013-06-26 | 2013-10-23 | 清华大学 | Static random storage unit |
| CN103956183A (en) * | 2014-04-24 | 2014-07-30 | 中国科学院微电子研究所 | Radiation-resistant SRAM cell |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104409093A (en) | 2015-03-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104299644B (en) | 12-tube SRAM (Static Random Access memory) unit circuit capable of simultaneously increasing read noise tolerance and writing margin | |
| CN104409093B (en) | The transistor memory unit of difference 10 of anti-single particle reversion | |
| CN103778954B (en) | The memorizer of anti-multiple node upset | |
| CN103077741B (en) | The storage unit circuit of a kind of SRAM of low voltage operating | |
| CN105336362B (en) | The static random access memory of radiation hardening | |
| CN108492843B (en) | 14T radiation-resistant static storage unit | |
| CN112259143B (en) | Read-write separation 14T anti-radiation SRAM memory cell circuit structure | |
| Naso et al. | A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology | |
| CN107886986A (en) | A kind of subthreshold value SRAM memory cell circuit for solving half selected problem | |
| CN102314538B (en) | Method for laying out transistors of fault-tolerant storage unit | |
| CN102157195B (en) | Low-voltage static random access memory unit, memory and writing operation method | |
| CN106847333B (en) | A kind of novel anti-single particle SRAM bit cell | |
| CN102385916A (en) | Dual-port static random access memory (SRAM) unit 6T structure with reading-writing separation function | |
| CN105869668B (en) | Flouride-resistani acid phesphatase double interlocking applied to Dynamic voltage scaling system deposits type storage unit | |
| CN104637530A (en) | Random access memory with redundant structure | |
| CN111128271A (en) | RHPD-12T radiation-resistant SRAM memory cell circuit | |
| CN104700889A (en) | Storage unit based on DICE structure for static random access storage device | |
| Hao et al. | Design of radiation-hardened memory cell by polar design for space applications | |
| CN204102573U (en) | A kind of novel 12 pipe sram cell circuit improving read noise tolerance limit simultaneously and write nargin | |
| CN109935260A (en) | A kind of average 7T1R element circuit using multiple multiplex strategy | |
| WO2016154825A1 (en) | Dice structure-based storage unit of static random access memory | |
| CN104409094B (en) | The transistor memory unit of subthreshold value 6 | |
| CN103578530A (en) | Sub-threshold storage unit supporting column selection function | |
| CN108766494B (en) | SRAM memory cell circuit with high read noise tolerance | |
| US9013941B2 (en) | DRAM with pulse sense amp |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |