CN104392950A - Positioning method of chip welding points - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000003466 welding Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 238000012545 processing Methods 0.000 claims abstract description 14
- 229910000679 solder Inorganic materials 0.000 claims abstract description 13
- 239000000284 extract Substances 0.000 claims description 5
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims 1
- 238000013461 design Methods 0.000 abstract description 6
- 238000007781 pre-processing Methods 0.000 description 10
- 238000004806 packaging method and process Methods 0.000 description 6
- 238000012937 correction Methods 0.000 description 4
- 238000000605 extraction Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 230000009466 transformation Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000013519 translation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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Abstract
本发明公开了一种芯片焊点的定位方法，包括对位于设定位置的芯片和贴片基板进行图像采集，对采集的图像进行分析处理得出芯片和贴片基板的坐标偏移量以及角度偏移量，依据坐标偏移量和角度偏移量对引线键合头位置进行调整，然后进行引线键合。上述方法能够快速、准确的检测出芯片和贴片基板相对于设计位置的偏移位置和偏移角度，分析得出键合焊点的实际中心坐标位置，提高引线键合工艺中的焊接质量。
The invention discloses a method for locating solder joints of a chip, which includes collecting images of a chip and a patch substrate at a set position, and analyzing and processing the collected image to obtain the coordinate offset and angle of the chip and the patch substrate Offset, adjust the position of the wire bonding head according to the coordinate offset and angle offset, and then perform wire bonding. The above method can quickly and accurately detect the offset position and offset angle of the chip and the chip substrate relative to the design position, analyze and obtain the actual center coordinate position of the bonding solder joint, and improve the welding quality in the wire bonding process.
Description
技术领域technical field
本发明涉及芯片焊接封装领域，具体涉及一种芯片焊点的定位方法。The invention relates to the field of chip soldering and packaging, in particular to a method for positioning chip solder joints.
背景技术Background technique
芯片封装是指将芯片安装、固定、密封于封装基板中，并将其上的I/O点用导线连接到封装外壳引脚上的过程。芯片封装的主要流程包括硅片测试和拣选、分片、贴片、引线键合、塑料封装和最终封装与测试。其中，贴片过程又叫芯片粘贴，是将芯片固定于封装基板或引线框架的芯片基板上的处理过程。贴片的方式主要有共晶粘贴法、焊接粘贴法、导电胶粘贴法和玻璃胶粘贴法。Chip packaging refers to the process of installing, fixing, and sealing the chip in the package substrate, and connecting the I/O points on it to the pins of the package shell with wires. The main process of chip packaging includes silicon wafer testing and sorting, slicing, placement, wire bonding, plastic packaging and final packaging and testing. Among them, the placement process is also called chip bonding, which is a process of fixing the chip on the package substrate or the chip substrate of the lead frame. The methods of patch mainly include eutectic paste method, welding paste method, conductive adhesive paste method and glass glue paste method.
在贴片过程中产生的贴片误差主要包括：芯片和基板相对预先定义的标准坐标位置的偏差值、芯片和引线框架在制造过程中产生的尺寸误差以及引线键合时固定引线框架产生的定位误差，这些误差都是随机误差，无法通过预先判断误差大小的方式来消除。因此，单纯通过加强对运动平台的控制来提高精度减小误差已经不能满足芯片封装的发展需求。The placement error generated during the placement process mainly includes: the deviation value of the chip and the substrate relative to the predefined standard coordinate position, the size error of the chip and the lead frame during the manufacturing process, and the positioning of the fixed lead frame during wire bonding These errors are random errors and cannot be eliminated by pre-judging the size of the error. Therefore, improving the accuracy and reducing the error simply by strengthening the control of the motion platform can no longer meet the development needs of chip packaging.
发明内容Contents of the invention
本发明的目的在于提供一种芯片焊点的定位方法，其可有效解决上述问题，为引线键合头提供定位修正参数，提高引线键合的精度。The object of the present invention is to provide a method for positioning solder joints of chips, which can effectively solve the above problems, provide positioning correction parameters for wire bonding heads, and improve the accuracy of wire bonding.
为实现上述目的，本发明采用如下技术方进行实施：To achieve the above object, the present invention adopts the following technical side to implement:
一种芯片焊点的定位方法，包括对位于设定位置的芯片和贴片基板进行图像采集，对采集的图像进行分析处理得出芯片和贴片基板的实际坐标位置，将芯片和贴片基板的实际坐标位置与芯片和贴片基板的设定坐标位置进行比较得出芯片和贴片基板的坐标偏移量以及角度偏移量，依据坐标偏移量和角度偏移量对引线键合头位置进行调整，然后进行引线键合。A method for positioning chip solder joints, comprising collecting images of a chip and a chip substrate at a set position, analyzing and processing the collected images to obtain the actual coordinate positions of the chip and the chip substrate, and placing the chip and the chip substrate Compare the actual coordinate position of the chip and the set coordinate position of the chip and the chip substrate to obtain the coordinate offset and angle offset of the chip and the chip substrate, and adjust the wire bonding head according to the coordinate offset and angle offset The position is adjusted and then wire bonded.
具体的方案为：The specific plan is:
对芯片和贴片基板进行图像采集的具体方法为：通过计算机机器视觉系统采集位于设定位置的带有芯片的引线框架贴片基板的图像，然后提取图像中的ROI区域并保存ROI区域的坐标参数，所述的RIO区域图像为只包括芯片和贴片基板图像的局部区域。The specific method for image acquisition of the chip and the chip substrate is: collect the image of the lead frame chip substrate with the chip at the set position through the computer machine vision system, and then extract the ROI area in the image and save the coordinates of the ROI area Parameters, the RIO area image is a local area that only includes images of chips and patch substrates.
采集的图像进行分析处理的具体方法为：在ROI区域中提取芯片和贴片基板的虚拟角点，依据虚拟角点拟合芯片和贴片基板的最小外接矩形，然后依据最小外接矩形确定设定的芯片和贴片基板的实际坐标位置。The specific method for analyzing and processing the collected images is: extracting the virtual corner points of the chip and the chip substrate in the ROI area, fitting the minimum circumscribed rectangle of the chip and the chip substrate according to the virtual corner points, and then determining the setting according to the minimum circumscribed rectangle The actual coordinate position of the chip and the patch substrate.
ROI区域中提取的芯片和贴片基板的虚拟角点分别有四个，在四个虚拟角点中任意选取其中三个点构成一个虚拟角点组，使用矩形判定准则对虚拟角点组判定，误差最小的组认为是芯片/基板的实际最小外接矩形，再通过对误差最小组的第四个角点求解，得到芯片和基板的最小外接矩形。There are four virtual corners of the chip and the patch substrate extracted in the ROI area, three of which are arbitrarily selected from the four virtual corners to form a virtual corner group, and the virtual corner group is judged using the rectangle judgment criterion, The group with the smallest error is considered to be the actual smallest circumscribed rectangle of the chip/substrate, and then the minimum circumscribed rectangle of the chip and substrate is obtained by solving the fourth corner point of the group with the smallest error.
详细的操作为：The detailed operation is:
一、首先由机器视觉系统获取芯片和引线框架贴片基板部位的数字图像，通过图像预处理模块提取图像中芯片和引线框架贴片基板的图像。确定芯片和贴片基板的ROI区域时，应将该区域作为图像处理的核心区域，处于ROI区域之外的图像都不予考虑。对芯片和贴片基板的图像进行批量化处理时，不再重新设定ROI区域和函数参数并且保证光学环境、芯片与引线框架型号不变的条件。1. First, the machine vision system acquires the digital image of the chip and the lead frame chip substrate, and extracts the image of the chip and the lead frame chip substrate in the image through the image preprocessing module. When determining the ROI area of the chip and the patch substrate, this area should be regarded as the core area of image processing, and images outside the ROI area will not be considered. When performing batch processing on images of chips and SMT substrates, it is no longer necessary to reset the ROI area and function parameters and ensure that the optical environment, chip and lead frame models remain unchanged.
二、针对ROI区域内的芯片和贴片基板图像，分别提取芯片和贴片基板的虚拟角点。对图像进行预处理之后，得到的是单边缘像素的图像，由于芯片和引线框架基板在制造中存在一定误差，并且在环境中受到氧化，得到的边缘图像不是规则的直线段，因此发明中通过提取边缘图像上的特征点，对特征点进行拟合得到边缘直线方程。对该区域处理时记录预处理函数和虚拟角点提取算法的参数，对预定义的ROI区域调用预先确定参数的预处理函数和虚拟角点提取算法，逐个提取芯片和引线框架贴片基板的虚拟角点。2. Aiming at the images of the chip and the chip substrate in the ROI region, extract virtual corner points of the chip and the chip substrate respectively. After the image is preprocessed, the image obtained is a single-edge pixel image. Due to certain errors in the manufacturing of the chip and the lead frame substrate, and the oxidation in the environment, the obtained edge image is not a regular straight line segment. Therefore, in the invention, the The feature points on the edge image are extracted, and the feature points are fitted to obtain the edge straight line equation. When processing this area, record the parameters of the preprocessing function and virtual corner point extraction algorithm, call the preprocessing function and virtual corner point extraction algorithm with predetermined parameters for the predefined ROI area, and extract the virtual corner.
三、计算出的虚拟角点结合外接矩形判定准则拟合芯片和贴片基板的最小外接矩形，并计算出外接矩形的中心位置和轴向偏角，将外界矩形的中心位置和轴向偏角作为芯片和贴片基板的实际定位参数。芯片和贴片基板中心点的实际坐标位置是相对于芯片和贴片基板的设计位置经过坐标平移和旋转变换得到。通过对基板和芯片几何中心坐标的求解，可以得到芯片和贴片基板的实际坐标位置和偏移角度。3. The calculated virtual corners are combined with the circumscribed rectangle criterion to fit the minimum circumscribed rectangle of the chip and the chip substrate, and the center position and axial deflection angle of the circumscribed rectangle are calculated, and the center position and axial deflection angle of the external rectangle are calculated. As the actual positioning parameters of chips and SMT substrates. The actual coordinate position of the center point of the chip and the patch substrate is obtained through coordinate translation and rotation transformation relative to the design position of the chip and the patch substrate. By solving the geometric center coordinates of the substrate and the chip, the actual coordinate position and offset angle of the chip and the patch substrate can be obtained.
四、由芯片和贴片基板的实际坐标位置参数计算出相对于设定坐标位置的坐标偏移量和转角偏移量，以偏移量作为引线键合头的定位修正参数，针对每片芯片对引线键合头定位进行在线修正，提高引线键合质量。4. Calculate the coordinate offset and rotation angle offset relative to the set coordinate position from the actual coordinate position parameters of the chip and the chip substrate, and use the offset as the positioning correction parameter of the wire bonding head for each chip On-line correction of wire bonding head positioning to improve wire bonding quality.
由于芯片和基板上存在很多直线段，而这些直线段并不是需要检测的芯片和基板边缘，这给边缘特征点提取带来很大的干扰和困难。因此首先在机器视觉系统采集到的数字图像中设置ROI区域，直接剔除可能产生干扰的其他线段，针对ROI区域内的芯片和贴片基板图像确定提取虚拟角点的相关函数参数。Since there are many straight line segments on the chip and the substrate, and these straight line segments are not the edge of the chip and the substrate to be detected, this brings great interference and difficulty to the edge feature point extraction. Therefore, first set the ROI area in the digital image collected by the machine vision system, directly eliminate other line segments that may cause interference, and determine the relevant function parameters for extracting virtual corner points for the chip and chip substrate images in the ROI area.
在检测环境不变的情况下，对于同种型号的芯片和引线框架，按照预定义的ROI区域和图像处理函数与参数进行批量化处理。对每幅粘贴在引线框架贴片基板上的芯片和贴片基板的图像进行处理，提取出芯片和贴片基板的虚拟角点。由于芯片和贴片基板的制造误差以及成像误差，虚拟角点求解特征区域的外接矩形时可能无解，因此采用在四个虚拟角点中选择任意三个虚拟角点构造外接矩形的方法对理想外接矩形进行拟合。由任意选取的三个虚拟角点构成一个虚拟角点组，使用矩形判定准则对虚拟角点组判定，误差最小的组认为是芯片和基板的实际最小外接矩形，再通过对最小误差组的第四个角点求解，得到芯片和基板的最小外接矩形。Under the condition that the detection environment remains unchanged, for the same type of chips and lead frames, batch processing is performed according to the predefined ROI area and image processing functions and parameters. Each image of the chip and the chip substrate pasted on the lead frame chip substrate is processed, and the virtual corner points of the chip and the chip substrate are extracted. Due to the manufacturing error and imaging error of the chip and the patch substrate, virtual corner points may have no solution when solving the circumscribed rectangle of the feature area. The bounding rectangle is fitted. A virtual corner group is composed of three virtual corner points selected arbitrarily, and the virtual corner group is judged using the rectangle judging criterion. The four corner points are solved to obtain the minimum circumscribed rectangle of the chip and the substrate.
芯片和贴片基板的中心点的实际坐标位置是相对于设定坐标位置作几何变换得到。通过计算最小拟合矩形的中心坐标和偏角可以得到芯片和贴片基板的实际坐标参数和偏移角度。用实际坐标参数和设计坐标参数对比可以计算出为芯片和贴片基板的坐标偏移量(Δx,Δy)和角度偏移量Δθ。The actual coordinate position of the center point of the chip and the patch substrate is obtained by geometric transformation relative to the set coordinate position. By calculating the center coordinates and deflection angles of the minimum fitting rectangle, the actual coordinate parameters and deflection angles of the chip and the patch substrate can be obtained. By comparing the actual coordinate parameters with the design coordinate parameters, the coordinate offset (Δx, Δy) and angle offset Δθ of the chip and the patch substrate can be calculated.
上述方法能够快速、准确的检测出芯片和贴片基板相对于设计位置的偏移位置和偏移角度，分析得出键合焊点的实际中心坐标位置，提高引线键合工艺中的焊接质量，通过人工辅助的方法排除了非相关区域中同种特征因素的影响，简化特征提取的步骤、缩短分析处理的复杂度和提高检测的效率，也通过人工干预的方式对干扰点的筛选，提高了分析检测的精确度。The above method can quickly and accurately detect the offset position and offset angle of the chip and the chip substrate relative to the design position, analyze and obtain the actual center coordinate position of the bonding solder joint, and improve the welding quality in the wire bonding process. The influence of the same characteristic factors in non-related areas is eliminated by artificial assistance, the steps of feature extraction are simplified, the complexity of analysis and processing is shortened, and the efficiency of detection is improved. The screening of interference points by manual intervention is also improved. Analyze the precision of detection.
附图说明Description of drawings
图1为计算机机器视觉系统采集的芯片和引线框架的局部图像；Fig. 1 is the partial image of chip and lead frame that computer machine vision system gathers;
图2为图1处理后的示意图；Fig. 2 is the schematic diagram after Fig. 1 processing;
图3为芯片/贴片基板拟合的最小外接矩形在偏移量坐标系上的示意图。Fig. 3 is a schematic diagram of the minimum circumscribed rectangle fitted by the chip/chip substrate on the offset coordinate system.
具体实施方式Detailed ways
为了使本发明的目的及优点更加清楚明白，以下结合实施例对本发明进行具体说明。应当理解，以下文字仅仅用以描述本发明的一种或几种具体的实施方式，并不对本发明具体请求的保护范围进行严格限定。In order to make the objects and advantages of the present invention clearer, the present invention will be specifically described below in conjunction with examples. It should be understood that the following words are only used to describe one or several specific implementation modes of the present invention, and do not strictly limit the protection scope of the specific claims of the present invention.
本发明的原理如下：建立一套最小拟合矩形标定方法对芯片图像和引线框架贴片基板图像标定，求出芯片和基板的实际坐标位置相对于预先定义的标准坐标位置的偏差值，得到芯片和贴片基板相对于标准图像的位置坐标和转角误差，有效的实现了芯片封装中的芯片和引线框架焊点精确定位。The principle of the present invention is as follows: a set of minimum fitting rectangle calibration method is established to calibrate the chip image and the lead frame patch substrate image, and the deviation value of the actual coordinate position of the chip and the substrate relative to the predefined standard coordinate position is obtained to obtain the chip The position coordinates and rotation angle errors of the chip substrate relative to the standard image effectively realize the precise positioning of the solder joints of the chip and the lead frame in the chip package.
实施例1Example 1
一种芯片焊点的定位方法，包括下述步骤：A method for positioning chip solder joints, comprising the steps of:
一、在确定预处理函数和虚拟角点函数参数的测定流程阶段，通过计算机机器视觉系统采集到的引线键合芯片和引线框架贴片基板的图像，如图1所示。在采集到的图像中设置ROI区域并保存ROI区域的坐标参数，设置的RIO区域只包括芯片和贴片基板的局部图像，完成ROI区域图像预处理函数参数的设置，消除图像干扰。1. In the determination process stage of determining the parameters of the preprocessing function and the virtual corner function, the images of the wire bonded chip and the lead frame chip substrate collected by the computer machine vision system are shown in Figure 1. Set the ROI area in the collected image and save the coordinate parameters of the ROI area. The set RIO area only includes the partial image of the chip and the patch substrate, and complete the setting of the image preprocessing function parameters of the ROI area to eliminate image interference.
二、在确定预处理函数和虚拟角点函数参数的测定流程阶段，针对预处理后的ROI区域图像分别提取芯片和贴片基板的虚拟角点，并设置虚拟角点算法的参数。2. In the determination process stage of determining the parameters of the preprocessing function and the virtual corner function, the virtual corner points of the chip and the chip substrate are respectively extracted from the preprocessed ROI area image, and the parameters of the virtual corner point algorithm are set.
三、在确定预处理函数和虚拟角点函数参数的测定流程阶段，对于芯片和贴片基板的虚拟角点，根据图像特点采用一个角是直角的平行四边形是矩形的矩形判定准则求取芯片和贴片基板的最小外接矩形，如图2所示。3. In the determination process stage of determining the preprocessing function and virtual corner function parameters, for the virtual corner points of the chip and the chip substrate, according to the characteristics of the image, a rectangular judgment criterion with a right-angled parallelogram and a rectangle is used to obtain the chip and The minimum circumscribed rectangle of the chip substrate is shown in Figure 2.
四、在确定预处理函数和虚拟角点函数参数的测定流程阶段，根据芯片和贴片基板的最小外接矩形，分别计算芯片和贴片基板中心的实际坐标参数和偏转角度。根据芯片的实际坐标和偏转角度可以分析得出芯片实际坐标位置与设计位置的位移偏差和角度偏差；根据芯片和贴片基板的实际定位坐标和偏转角度可以计算出芯片和贴片基板实际坐标位置与设定坐标位置之间的位移偏差和角度偏差，如图3所示。对偏差进行验证，满足引线键合要求后对预处理和虚拟角点算法参数记录并作为批处理阶段的工作参数。将焊点的实际坐标位置视为对理论位置进行平移和旋转复合二维图形变换的结果。依据芯片和贴片基板的实际坐标位置与设计位置的偏差可以计算出芯片和引线框架定位的坐标和角度偏差。该偏差参数可以作为引线键合头定位在线修正的调整参数，通过动态调整引线键合头的定位可以进一步提高引线键合的质量。4. In the determination process stage of determining the parameters of the preprocessing function and the virtual corner function, the actual coordinate parameters and deflection angles of the center of the chip and the chip substrate are respectively calculated according to the minimum circumscribed rectangle of the chip and the chip substrate. According to the actual coordinates and deflection angle of the chip, the displacement deviation and angle deviation between the actual coordinate position of the chip and the design position can be analyzed; according to the actual positioning coordinates and deflection angle of the chip and the chip substrate, the actual coordinate position of the chip and the chip substrate can be calculated The displacement deviation and angle deviation from the set coordinate position are shown in Figure 3. Verify the deviation, and record the preprocessing and virtual corner algorithm parameters after meeting the wire bonding requirements and use them as working parameters in the batch processing stage. The actual coordinate position of the solder joint is regarded as the result of translation and rotation compound two-dimensional graphics transformation of the theoretical position. According to the deviation between the actual coordinate position of the chip and the chip substrate and the design position, the coordinate and angle deviation of the positioning of the chip and the lead frame can be calculated. The deviation parameter can be used as an adjustment parameter for online correction of the wire bonding head positioning, and the quality of wire bonding can be further improved by dynamically adjusting the positioning of the wire bonding head.
五、在芯片和贴片基板的批量检测阶段，保证光学环境和待检芯片和引线框架型号不变的条件下，采用在试验阶段确定的ROI区域以及测试合格的预处理算法和虚拟角点算法参数对芯片和贴片基板图像进行批量化处理，计算偏移参数。5. In the batch inspection stage of chips and chip substrates, under the condition that the optical environment and the type of chips and lead frames to be inspected remain unchanged, the ROI area determined in the test stage and the preprocessing algorithm and virtual corner algorithm that pass the test are adopted Parameters Batch processing of chips and SMT substrate images to calculate offset parameters.
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在获知本发明中记载内容后，在不脱离本发明原理的前提下，还可以对其作出若干同等变换和替代，这些同等变换和替代也应视为属于本发明的保护范围。The above is only a preferred embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, after knowing the content recorded in the present invention, they can also make changes to it without departing from the principle of the present invention. Several equivalent transformations and substitutions should also be deemed to belong to the protection scope of the present invention.
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