CN104347730A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method, comprising an N-type substrate, an epitaxial layer located on the surface of the N-type substrate, the epitaxial layer including a groove; a metal layer covering the surface of the groove; An insulating layer on the surface of the epitaxial layer outside the groove; a first P-type well region located in the surface of the epitaxial layer and surrounding the groove, the first P-type well region isolating the metal layer and the epitaxial layer; wherein, the contact region of the first P-type well region and the metal layer forms an ohmic contact. The semiconductor device and the manufacturing method provided by the invention can effectively reduce the reverse leakage current of the device.

Description

Semiconductor device and manufacturing method

technical field

The invention relates to the field of semiconductors, in particular to a semiconductor device and a manufacturing method.

Background technique

At present, commonly used diodes usually include PN junction diodes and Schottky Barrier Diodes (Schottky Barrier Diode, abbreviated as SBD). Among them, the structural principle of SBD and PN junction diode is different by using the contact between P-type semiconductor and N-type semiconductor to form a PN junction. The SBD uses the structural principle of a Schottky junction formed by contacting a metal and a semiconductor.

Compared with PN junction diodes, SBD has the advantages of low power consumption, short reverse recovery time, and reduced forward voltage. But at the same time, the reverse performance of the diodes with the above two structures is not ideal, especially the reverse leakage current of the device is relatively large, which leads to a decrease in the performance of the device. Therefore, how to effectively reduce the reverse leakage current of the diode has become an urgent problem to be solved.

Contents of the invention

The invention provides a semiconductor device and a manufacturing method, which are used to solve the problem of large reverse leakage current of existing diodes.

A first aspect of the present invention is to provide a semiconductor device, comprising: an N-type substrate, an epitaxial layer on the surface of the N-type substrate, and the epitaxial layer includes a groove;

a metal layer covering the surface of the groove;

an insulating layer covering the surface of the epitaxial layer except the groove;

A first P-type well region located in the surface of the epitaxial layer and surrounding the groove, the first P-type well region isolating the metal layer and the epitaxial layer;

Wherein, an ohmic contact is formed between the first P-type well region and the contact region of the metal layer.

Another aspect of the present invention provides a method of manufacturing a semiconductor device, comprising:

forming an insulating layer on the surface of the epitaxial layer of the N-type substrate;

removing the insulating layer in the preset region by etching to expose the surface of the epitaxial layer to form a window;

Implanting P-type impurities into the window for the first time, and driving in to form a first P-type well region located in the surface of the epitaxial layer, the region corresponding to the first P-type well region includes and is larger than the The area corresponding to the window;

Etching a region corresponding to the window according to a preset etching depth to form a groove on the surface of the epitaxial layer;

on the surface of the groove, depositing a metal layer to cover the surface of the groove;

Wherein, the first P-type well region isolates the metal layer and the epitaxial layer.

In the semiconductor device and manufacturing method provided by the present invention, a groove is provided in the epitaxial layer, and a P-type well region surrounding the groove is formed in the surface of the epitaxial layer, and the P-type well region isolates and covers the The technical scheme of the metal layer on the surface of the groove and the epitaxial layer can effectively reduce the reverse leakage current of the device.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a semiconductor device provided by Embodiment 1 of the present invention;

2 is a schematic cross-sectional view of another semiconductor device provided by Embodiment 2 of the present invention;

FIG. 3 is a schematic flowchart of a method for manufacturing a semiconductor device provided by Embodiment 3 of the present invention;

4-7 are schematic cross-sectional views of semiconductor devices during the execution of Embodiment 3 of the present invention;

FIG. 8 is a schematic flowchart of another semiconductor device manufacturing method provided by Embodiment 4 of the present invention;

FIG. 9 is a schematic flowchart of another method for manufacturing a semiconductor device provided by Embodiment 5 of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. For convenience of description, the sizes of different layers and regions are enlarged or reduced, so the sizes and ratios shown in the drawings do not necessarily represent actual sizes, nor do they reflect the proportional relationship of sizes.

FIG. 1 is a schematic cross-sectional view of a semiconductor device provided by Embodiment 1 of the present invention. As shown in FIG. 1, the device includes: an N-type substrate 11, and an epitaxial layer 12 located on the surface of the N-type substrate. The epitaxial layer includes grooves;

a metal layer 13 covering the surface of the groove;

an insulating layer 14 covering the surface of the epitaxial layer 12 except for the groove;

The first P-type well region 15 located in the surface of the epitaxial layer 12 and surrounding the groove, the first P-type well region 15 isolates the metal layer 13 and the epitaxial layer 12, and the contact between the first P-type well region 15 and the metal layer 13 areas form ohmic contacts;

Wherein, the N-type substrate 11 and the epitaxial layer 12 can be semiconductor elements, such as monocrystalline silicon, polycrystalline silicon or silicon or silicon germanium (SiGe) with an amorphous structure, or a mixed semiconductor structure, such as silicon carbide, indium antimonide , lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors, or combinations thereof. This embodiment does not limit it here.

Specifically, the material of the metal layer 13 may be gold, silver, aluminum, platinum or molybdenum, and the selection of specific materials may be determined according to actual conditions. The material of the insulating layer 14 includes silicon dioxide.

It can be understood that in the semiconductor device provided in this embodiment, the first P-type well region 15 is located in the surface of the epitaxial layer 12, surrounds the groove, and isolates the contact between the metal layer 13 and the epitaxial layer 12, avoiding the contact between the metal layer 13 and the epitaxial layer 12. Semiconductor direct contact. Specifically, the contact region between the first P-type well region 15 and the metal layer 13 forms an ohmic contact, and the contact region between the first P-type well region 15 and the epitaxial layer 12 forms a PN junction, so that when the semiconductor device is applied with a reverse voltage When the pressure drops, the PN junction formed by the contact between the first P-type well region 15 and the epitaxial layer 12 is reversely blocked, thereby forming a depletion region, and, as the reverse voltage drop increases, the width of the depletion region gradually increases Large, effectively prevent the reverse leakage current, thereby effectively reducing the reverse leakage current of the device, and enabling the device to withstand a relatively large reverse voltage.

In an implementation manner of this embodiment, the device may further include:

The second P-type well region 16 located in the surface of the epitaxial layer 12 and in the first P-type well region 15 and below the groove, the width of the second P-type well region 16 is greater than the width of the groove, the second P-type well region 16 The width of a P-type well region 15 is greater than the width of the second P-type well region 16, and the impurity concentration of the first P-type well region 15 is smaller than the impurity concentration of the second P-type well region 16;

Specifically, the contact area between the second P-type well region 16 and the metal layer 13 forms an ohmic contact. Generally, a semiconductor with a high impurity concentration is conducive to forming a better ohmic contact. It can be understood that since the impurity concentration of the second P-type well region 16 is greater than the impurity concentration of the first P-type well region 15, through the second P-type well region 16 The setting of the well region can form a better ohmic contact with the metal layer 13, thereby effectively reducing the forward conduction resistance between the metal and the semiconductor, and improving the forward characteristics of the device.

In the semiconductor device provided in this embodiment, a groove is provided in the epitaxial layer, and a P-type well region surrounding the groove is formed in the surface of the epitaxial layer, and the P-type well region isolates and covers the groove. The technical solution of the metal layer on the surface and the epitaxial layer can effectively reduce the reverse leakage current of the device.

FIG. 2 is a schematic cross-sectional view of another semiconductor device provided by Embodiment 2 of the present invention. As shown in FIG. The sides of the groove; the device may also include:

An N-type region 17 located in the first P-type well region 15, the N-type region 17 surrounds the side of the groove, and is in contact with both the metal layer 13 and the insulating layer 14;

Wherein, the N-type region 17 is not in contact with the epitaxial layer 12 , and the depth of the N-type region 17 is smaller than the depth of the groove.

It can be understood that, according to the semiconductor device provided in this embodiment, when the semiconductor device is applied with a forward voltage drop, that is, when a forward voltage is applied to the metal layer 13, the first P-type region 15 is located under the insulating layer 14 And the region close to the insulating layer 14 undergoes inversion, thereby forming a conductive channel between the N-type region 17 and the epitaxial layer 12, and realizing forward conduction; and, the first P-type region 15 or the second P-type region 16, and The PN junction formed by the epitaxial layer 12 is also forward-conducting, so that the device can realize a larger forward current.

Specifically, in this implementation manner, the device may further include: a polysilicon layer 18 located between the metal layer 13 and the insulating layer 14 .

Through the semiconductor device provided by this embodiment, the forward characteristic of the device can be effectively improved while the reverse leakage current of the device can be effectively reduced, and the performance of the device can be improved.

Fig. 3 is a schematic flow chart of a method for manufacturing a semiconductor device provided by Embodiment 3 of the present invention. In order to describe the method in this embodiment clearly and systematically, Figs. 4-7 are schematic cross-sectional views of the semiconductor device during the execution of Embodiment 3 , as shown in Figure 3, the method includes the following steps:

301. Form an insulating layer on a surface of an epitaxial layer of an N-type substrate.

Specifically, a schematic cross-sectional view of the semiconductor device after performing 301 is shown in FIG. 4 , wherein the N-type substrate is denoted by a numeral 11, the epitaxial layer is denoted by a numeral 12, and the insulating layer is denoted by a numeral 14. .

302. Remove the insulating layer in the preset region by etching to expose the surface of the epitaxial layer and form a window.

Specifically, a schematic cross-sectional view of the semiconductor device after performing 302 is shown in FIG. 5 .

303. Implant P-type impurities into the window for the first time, and drive them in to form a first P-type well region located in the surface of the epitaxial layer, and the region corresponding to the first P-type well region includes and is greater than The region corresponding to the window.

Specifically, a schematic cross-sectional view of the semiconductor device after performing 303 is shown in FIG. 6 , wherein the first P-type well region is denoted by reference numeral 15 .

304. Etch a region corresponding to the window according to a preset etching depth, so as to form a groove on the surface of the epitaxial layer.

Specifically, a schematic cross-sectional view of the semiconductor device after performing 304 is shown in FIG. 7 .

305. On the surface of the groove, deposit a metal layer to cover the surface of the groove.

Wherein, the first P-type well region isolates the metal layer and the epitaxial layer.

Specifically, a schematic cross-sectional view of the semiconductor device after performing 305 is shown in FIG. 1 , wherein the metal layer is denoted by reference numeral 13 .

In practical applications, the coverage of the metal layer may include but not limited to the surface of the groove, and may also be the surface of the groove and the insulating layer, and what is shown in the figure is only a specific implementation without restricting it.

In the semiconductor device provided in this embodiment, a groove is provided in the epitaxial layer, and a P-type well region surrounding the groove is formed in the surface of the epitaxial layer, and the P-type well region isolates and covers the groove. The technical solution of the metal layer on the surface and the epitaxial layer can effectively reduce the reverse leakage current of the device.

FIG. 8 is a schematic flowchart of another semiconductor device manufacturing method provided in Embodiment 4 of the present invention. As shown in FIG. 8 , according to the semiconductor device manufacturing method described in Embodiment 2, in order to improve the forward characteristics of the semiconductor device, In an implementable manner of this embodiment, after step 304, the method may further include:

801. Implant P-type impurities into the groove for a second time, and perform driving to form a second P-type well region located in the first P-type well region and below the groove.

Specifically, the energy of the first implantation of P-type impurities is greater than the energy of the second implantation of P-type impurities, and the impurity dose of the first implantation of P-type impurities is smaller than the second implantation of P-type impurities, and, the A region corresponding to the second P-type well region includes and is larger than a region corresponding to the groove, and a region corresponding to the first P-type well region includes and is larger than a region corresponding to the second P-type well region.

The method provided in this embodiment can form a better ohmic contact with the metal layer by forming the second P-type well region, thereby effectively reducing the forward conduction resistance between the metal and the semiconductor, and improving the forward characteristics of the device.

Fig. 9 is a schematic flow chart of another method for manufacturing a semiconductor device provided in Embodiment 5 of the present invention. As shown in Fig. 9, according to the method for manufacturing a semiconductor device described in any of the above embodiments, in order to further improve the forward characteristics of , before 304, can also include:

901. Implant and drive N-type impurities into the window to form an N-type well region located in the first P-type well region, and a region corresponding to the first P-type well region includes and is larger than the A region corresponding to the N-type well region, where the region corresponding to the N-type well region includes and is larger than the region corresponding to the window;

Correspondingly, 304 specifically includes:

902. Etch the region corresponding to the window with the etching depth greater than the depth of the N-type well region, so as to remove the region below the window in the N-type well region and retain the N-type well region. a region under the insulating layer in the well region;

Correspondingly, 305 specifically includes:

903. Deposit a metal layer on the surface of the groove, the upper surface of the insulating layer, and the side surface close to the groove, so as to cover the surface of the groove and the upper surface of the insulating layer and near the sides of the groove.

Optionally, in this embodiment, before 302, it may also include:

904. Form a polysilicon layer on the surface of the insulating layer, and photoetch the polysilicon layer, so as to expose the surface of the insulating layer in the region.

Through the above embodiments, while effectively reducing the reverse leakage current of the device, the forward characteristic of the device can be effectively improved, and the performance of the device can be improved.

It should be noted that after performing steps 301 , 904 , 302 , 303 , 901 , 902 , 801 , and 903 in sequence, a semiconductor device as shown in FIG. 2 can be obtained. Specifically, the labels of the structures in this embodiment correspond to the labels of the structures in the foregoing embodiments.

The semiconductor device provided in this embodiment can effectively reduce the reverse leakage current of the device, effectively improve the forward characteristics of the device, and improve the performance of the device.

Those skilled in the art can clearly understand that for the convenience and brevity of description, for the specific manufacturing methods of the devices in the foregoing embodiments, reference can be made to the corresponding processes in the foregoing method embodiments.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (10)

1. A semiconductor device, comprising: an N-type substrate, an epitaxial layer positioned on a surface of the N-type substrate, and the epitaxial layer includes a groove; a metal layer covering the surface of the groove; an insulating layer covering the surface of the epitaxial layer except the groove; A first P-type well region located in the surface of the epitaxial layer and surrounding the groove, the first P-type well region isolating the metal layer and the epitaxial layer; Wherein, an ohmic contact is formed between the first P-type well region and the contact region of the metal layer. 2. The device according to claim 1, wherein the device further comprises: A second P-type well region located in the surface of the epitaxial layer and in the first P-type well region and below the groove, the width of the second P-type well region is greater than the width of the groove , the width of the first P-type well region is greater than the width of the second P-type well region, and the impurity concentration of the first P-type well region is smaller than the impurity concentration of the second P-type well region; Wherein, the contact region of the second P-type well region and the metal layer forms an ohmic contact. 3. The device according to claim 1 or 2, wherein the metal layer also covers the upper surface of the insulating layer and the side near the groove; the device further comprises: an N-type region located in the first P-type well region, the N-type region surrounds the side of the groove and is in contact with both the metal layer and the insulating layer; Wherein, the N-type region is not in contact with the epitaxial layer, and the depth of the N-type region is smaller than the depth of the groove. 4. The device according to claim 3, further comprising: a polysilicon layer located between the metal layer and the insulating layer. 5. The device according to claim 1, wherein the N-type substrate is saturated doped N-type single crystal silicon; The epitaxial layer is N-type single crystal silicon with a doping concentration lower than that of the N-type substrate. 6. A method for manufacturing a semiconductor device, comprising: forming an insulating layer on the surface of the epitaxial layer of the N-type substrate; removing the insulating layer in the preset region by etching to expose the surface of the epitaxial layer to form a window; Implanting P-type impurities into the window for the first time, and driving in to form a first P-type well region located in the surface of the epitaxial layer, the region corresponding to the first P-type well region includes and is larger than the The area corresponding to the window; Etching a region corresponding to the window according to a preset etching depth to form a groove on the surface of the epitaxial layer; on the surface of the groove, depositing a metal layer to cover the surface of the groove; Wherein, the first P-type well region isolates the metal layer and the epitaxial layer. 7. The method according to claim 6, wherein said etching the region corresponding to the window according to the preset etching depth to form grooves on the surface of the epitaxial layer, further comprising: Implanting P-type impurities into the groove for the second time, and driving in to form a second P-type well region located in the first P-type well region and below the groove; Wherein, the energy of the first implantation of P-type impurities is greater than the energy of the second implantation of P-type impurities, the dose of impurities injected into P-type impurities for the first time is smaller than the dose of impurities injected into P-type impurities for the second time, and the second P-type impurity A region corresponding to the well region includes and is larger than a region corresponding to the groove, and a region corresponding to the first P-type well region includes and is larger than a region corresponding to the second P-type well region. 8. The method according to claim 6 or 7, wherein, before etching the region corresponding to the window according to the preset etching depth, further comprising: Implanting N-type impurities into the window and driving them in to form an N-type well region located in the first P-type well region, the region corresponding to the first P-type well region includes and is larger than the N-type well region. A region corresponding to the well region, the region corresponding to the N-type well region includes and is larger than the region corresponding to the window; The etching the area corresponding to the window according to the preset etching depth specifically includes: Etching the region corresponding to the window with the etching depth greater than the depth of the N-type well region, so as to remove the region below the window in the N-type well region and retain the N-type well region a region located below the insulating layer; The depositing a metal layer on the surface of the groove to cover the surface of the groove specifically includes: On the surface of the groove, the upper surface of the insulating layer and the side surfaces close to the groove, a metal layer is deposited to cover the surface of the groove, the upper surface of the insulating layer and the sides close to the groove. the sides of the groove. 9. The method according to claim 8, characterized in that, before removing the insulating layer in the preset region by etching, further comprising: forming a polysilicon layer on the surface of the insulating layer; photoetching the polysilicon layer to expose the surface of the insulating layer in the region; The depositing a metal layer on the surface of the groove to cover the surface of the groove specifically includes: On the surface of the groove, the upper surface of the polysilicon layer and the side surfaces close to the groove, a metal layer is deposited to cover the surface of the groove, the upper surface of the polysilicon layer and the sides close to the groove. the sides of the groove. 10. The method according to claim 8, wherein the N-type impurity is arsenic; the P-type impurity is boron.