CN104347102B - Signal receiver - Google Patents
Signal receiver Download PDFInfo
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- CN104347102B CN104347102B CN201310348238.9A CN201310348238A CN104347102B CN 104347102 B CN104347102 B CN 104347102B CN 201310348238 A CN201310348238 A CN 201310348238A CN 104347102 B CN104347102 B CN 104347102B
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- active component
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Abstract
The present invention provides a kind of signal receiver, include a current source, an input active component to and a resistance pair.The current source provides an electric current, and it has a current value.Each input active component has a control end, one first conduction terminals and one second conduction terminals.One of two control ends of the input active component pair receive an input signal, and two the first conduction terminals link together and receive the electric current.One of two second conduction terminals are as an output end, and the input active component is to being to output signal to a core circuit according to the electric current and input signal output one.Each resistance has a resistance value, is connected to one of two second conduction terminals between a power line.The resistance value determines a target voltage values with the current value, so that the voltage swing of the output signal is not more than the target voltage values, and then an operating voltage of the core circuit is approximately equal to the target voltage values.
Description
Technical field
It, on signal receiver, is the signal receiver on can tolerate high voltage signal especially that the present invention, which is,.
Background technology
With the evolution of integrated circuit manufacture process technology, the lasting reduction of operating voltage in integrated circuit.However, of new generation
Integrated circuit, generally require from printed circuit board (PCB), go to receive the extraneous signal that old generation integrated circuit is sent, and
The signal voltage of extraneous signal may exceed the operating voltage of integrated circuit of new generation.
Third generation double data rate Synchronous Dynamic Random Access Memory（Double-Data-Rate Three
Synchronous Dynamic Random Access Memory, commonly referred to as DDR3SDRAM）, for example, it operates electricity
Press and be defined as 1.5V, and 1st generation and 2nd generation double data rate Synchronous Dynamic Random Access Memory (abbreviation DDR1 and DDR2)
Operating voltage is respectively 2.5V and 1.8V.And the newest DDR4 (DDR of forth generation) not decided on a verdict also, or even predetermined operation electricity
Force down 1.2V.So for example, one can meet DDR2/3/4 receiver simultaneously, just allow for being resistant to and handling
The scope of voltage can be from 1.2V to 1.8V input signal.
In addition to considering tolerating high voltage signal, the design of DDR receivers is also required to consider output voltage switching rate
(output voltage slew rate), power attenuation (power consumption), signal propagation delay time
(signal propagation delay), circuit hardware cost (wafer area) etc. factor.Have only and taken in many factors
It must optimize, be only a good circuit design.
The content of the invention
The present invention proposes a kind of signal receiver, include a current source, an input active component to and a resistance
It is right.The current source provides an electric current, and it has a current value.Each input active component has a control end, one first conduction
End and one second conduction terminals.One of these control ends of the input active component pair receive an input signal, and these the
One conduction terminals link together and receive the electric current.One of these second conduction terminals are as an output end, and the input is active
Element according to the electric current and input signal output one to outputing signal to a core circuit.Each resistance has a resistance value, point
It is not connected between one of these second conduction terminals and a power line.The resistance value determines a target voltage with the current value
Value, so that the voltage swing of the output signal is not more than the target voltage values, and then makes an operating voltage of the core circuit big
It is approximately equal to the target voltage values.
A kind of signal receiver of also proposition of the present invention, includes a first order amplifier and a second level amplifier.Should
First order amplifier receives an input signal, and is exported according to the first voltage gain process input signal with providing one first
Signal, the wherein first order amplifier are made the voltage swing of first output signal be not more than a preset value by framework.This
Two-stage amplifier receives first output signal, and according to a second voltage gain process first output signal to produce one
Two output signal to a core circuit, and wherein the second level amplifier is made the voltage swing of second output signal by framework not
More than the preset value.The second voltage gain is more than the first voltage gain, and the first voltage gain is more than 1.Core electricity
Road is to be powered with a high digital circuit power source line with a low digital circuit power source line, and the preset value is approximately equal to high numeral electricity
Voltage difference between road power line and the low digital circuit power source line.
Brief description of the drawings
For the above objects, features and advantages of the present invention can be become apparent, below in conjunction with tool of the accompanying drawing to the present invention
Body embodiment elaborates, wherein：
Two ICs 1 and IC2 that Fig. 1 displays are communicated using DDR3 specifications.
Fig. 2 shows binary signal receiver R_DQS and R_DQ0 in one embodiment of this invention, and some correlations
Circuit.
Fig. 3 shows a signal receiver RV, can as Fig. 2 signal receiver R_DQS or R_DQ0.
Fig. 4 shows the embodiment of the current source S1 and S2 in Fig. 3.
Component label instructions in figure：
100th, 200 differential amplifier
300 buffer stages
DF1, DF2 trigger
DL delay circuits
DQ0~DQ7 pins
DQS+, DQS- pin
IC1, IC2 integrated circuit
Iref determines electric current
It1, It2 tail current
OP operational amplifiers
PAD_DQ0 joint sheets
PAD_DQS+, PAD_DQS- joint sheet
P1N、P2N、P1P、P2P、PSC、PS0、PS1、PS2 PMOS
Res, R1N, R2N, R2P, R1P resistance
R_DQS, R_DQ0 signal receiver
RV signal receivers
S1, S2 current source
The high digital circuit power source lines of VDDdigital
The high analog circuit power lines of VDDanalog
Vin+, Vin- signal input part
Vo1+, Vo1-, Vo2+, Vo2- differential output
Vout+, Vout- signal output part
Vref fixed reference potentials
The low digital circuit power source lines of VSSdigital
The low analog circuit power lines of VSSanalog
Embodiment
Although embodiments of the present invention be with DDR receivers as an example, the present invention is not limited thereto.Citing comes
Say, embodiments of the invention are probably any single-ended signal reception amplifier or differential wave reception amplifier.
Two ICs 1 and IC2 that Fig. 1 displays are communicated using DDR3 specifications.Pin DQS+ and DQS- is used for transmitting
Or reception is used for data strobe signal DQS (data queue strobe), the pin DQ0~DQ7 represented by a differential wave
Transmission receives data-signal.Such as DDR3 institutes specification, data strobe signal DQS rising edge and falling edge can be defined
The reading for the byte data (one byte) that IC 1 and IC2 is transmitted from pin DQ0~DQ7 or write time.
The higher voltage signal come is transmitted with maintaining altitude information processing in order to be able to take into account the old generation integrated circuit of tolerance
At least possessing in speed, the integrated circuit implemented according to the present invention has two kinds of elements：Core parts (core device) with
And high pressure resistant element (high-voltage-tolerable device).High pressure resistant element has a high voltage tolerance, and core
The service speed of element is than very fast.For example, core parts and high pressure resistant element are all MOS elements, and high pressure resistant element
Lock oxide layer be more than core parts lock oxide layer.Integrated circuit has core circuit and output/input circuit, substantially distinguishes
Using core parts and high pressure resistant element.Core circuit is not really wanted to be made up of core parts completely, can also be set depending on circuit
The demand of meter, and use some high pressure resistant elements.Similar, output/input circuit also not necessarily will be by high pressure resistant element institute structure
Into, can regard circuit design on demand, using some core parts.As the window to the outside world of integrated circuit, so import and export
Circuit has joint sheet, for example, bonding wire can be formed on joint sheet, is electrically connected to the pin of integrated circuit.
Core circuit is digital circuit mostly, and it is generally low by a high digital circuit power source line VDDdigital and one
Digital circuit power source line VSSdigital is powered；Output/input circuit is analog circuit mostly, and it is generally by a high simulation electricity
Road power line VDDanalog is powered with a low analog circuit power line VSSanalog.Not it is used for limiting the present invention's below
In embodiment, digital circuit power source line VDDdigital and VSSdigital, with analog circuit power line VDDanalog with
VSSanalog, its magnitude of voltage is respectively 1.1V, 0V, 1.8V and 0V.Digital circuit power source line VSSdigital and analog circuit electricity
Source line VSSanalog is 0V (ground connection), therefore in integrated circuits, can be connected or in parallel, or mutually substitution.Depending on setting
Demand on meter, output/input circuit may also have partial circuit by digital circuit power source line VDDdigital and VSSdigital
Powered.Certainly if necessary, the partial circuit in core circuit can also be by analog circuit power line VDDanalog
Powered with VSSanalog.
Fig. 2 shows binary signal receiver R_DQS and R_DQ0 in one embodiment of this invention, and some correlations
Circuit, it is possible to implement in Fig. 1 IC 1 or IC2.In fig. 2, signal receiver R_DQS and R_DQ0 has a mould
The same circuit framework, each there is two signal input parts a Vin+ and Vin-, and two signal output part Vout+ with
Vout-.Signal receiver R_DQS and R_DQ0 may belong to output/input circuit, and delay circuit (delay circuit) DL
Core circuit is may belong to two trigger DF1 and DF2.
Signal receiver R_DQ0 signal input part Vin+ is connected to joint sheet PAD_DQ0, and it is electrically connected to pin DQ0
(being shown in Fig. 1).And signal receiver R_DQ0 signal input part Vin- is connected to a fixed reference potential Vref.Citing comes
Say, this reference voltage Vref can be 0.75 or 0.9 volt, depending on signal receiver R_DQ0 will be applied to DDR3 or
Depending on DDR2.Signal receiver R_DQ0 signal output part Vout- floats, and signal output part Vout+ is connected to two D and touched
Send out device DF1 and DF2 D inputs.The comparators of signal receiver R_DQ0 herein as a single input, differentiate instantly from pin
The logical value for the signal that DQ0 is inputted, result is produced in signal output part Vout+.
Signal receiver R_DQS signal input part Vin+ and Vin- is connected respectively to joint sheet PAD_DQS+ and PAD_
DQS-.Joint sheet PAD_DQS+ and PAD_DQS- is electrically connected respectively to pin DQS+ and DQS- (being shown in Fig. 1).Signal is received
Device R_DQS signal output part Vout+ is connected to a delay circuit (delay circuit) DL, and it drives two d type flip flops
The clock pulse end of (flip flop).In other words, signal receiver R_DQS is as differential amplifier comparator, receive from pin DQS+ with
The data strobe signal DQS that DQS- comes.In data strobe signal DQS rising edge or after one section of time delay of falling edge,
The result produced by signal receiver R_DQ0 is recorded in d type flip flop DF1 or DF2.
Although Fig. 2 shows a signal receiver R_DQ0 for data-signal DQ0, correspond to other data-signals DQ1~
The structure and embodiment of 7 signal receiver can also deduce according to the teaching of this specification, therefore do not tire out and state.
Fig. 3 shows a signal receiver RV, can as Fig. 2 signal receiver R_DQS or R_DQ0.Signal receiver RV
The DDR signal of simulation on joint sheet can be converted into the data signal being adapted in core circuit.
Signal receiver RV has input Vin+ and Vin-, and output end vo ut+ and Vout-.Signal receiver RV is big
Cause is divided into concatenation (cascade) three-level：Differential amplifier 100 and 200, and buffer stage 300.Differential amplifier 100 and 200
Purpose substantially is that signal amplification and current potential are translated (level shifting), so differential amplifier 100 and 200
Voltage signal gain is both greater than 1.Buffer stage 300 is increase fan output (fanout), that is, makes signal receiver RV thrust
Increase.
Differential amplifier 100 and 200 is all with high analog circuit power line VDDanalog and low analog circuit power line
VSSanalog (voltage is respectively 1.8V and 0V, it is noted that, according to the present invention, high analog circuit power line VDDanalog can be with
Use the voltage higher than 1.8V, such as 3.3V) powered.Buffer stage 300 be then with digital circuit power source line VDDdigital with
And VSSdigital (voltage is respectively 1.1V and 0V) power supplies.
Differential amplifier 100 has two PMOS P1P and P1N, current source S1, two passive type resistance R1P and R1N.Electric current
Source S1 produces tail current (tail current) It1 from high analog circuit power line VDDanalog, with current value II1.PMOS
P1P and P1N is connected to current source S1 together with common-source stage (common source) framework.Two of PMOS P1P and P1N
Grid end (gate), that is, two control ends, respectively as input Vin+ and Vin-.PMOS P1P and P1N drain terminal
(drain) resistance R1P and R1N, are then connected respectively to.Two resistance R1P and R1N is all connected to low analog circuit power line
VSSanalog.Resistance R1P and R1N resistance value are approximately equivalent, are RR1.PMOS P1P and P1N drain terminal also serve as differential put
The differential output Vo1+ and Vo1- of big device 100.Current value II1 and resistance value RR1 product is equal to a definite value Vcon.It is real herein
Apply in example, definite value Vcon is equal to the voltage difference between digital circuit power source line VDDdigital and VSSdigital, that is,
The operating voltage of core circuit.
In addition to the function that signal amplifies, another function of differential amplifier 100 is current potential translation (level
shift).No matter the input signal of differential amplifier 100 is why, differential output Vo1+ and Vo1- output common-mode voltages
(common mode voltage) is exactly being averaged for digital circuit power source line VDDdigital and VSSdigital voltage
Value.Definite value Vcon differential output Vo1+ and Vo1- in fact maximum possible voltage, be also differential output Vo1+ and Vo1- most
Greatly may voltage swing (voltage swing).Differential output Vo1+ and Vo1- mobility scale, are already confined to digital electricity
In road power line VDDdigital and VSSdigital voltage difference, can as core circuit input.
The PMOS P2P and P2N of differential amplifier 200 two grid ends (gate) are connected respectively to differential amplifier 100
Differential output Vo1+ and Vo1-.It is similar with differential amplifier 100, in differential amplifier 200, current source S2 current value II2
Product with resistance R2P or R2N resistance value RR2 is also approximately equal to definite value Vcon, but resistance value RR2 is unnecessary with resistance value
RR1 is equal.As shown in figure 3, the circuit structure of differential amplifier 200 is roughly the same with the circuit structure of differential amplifier 100, can
To learn operation therein according to previous teaching, therefore it is not repeated.
In being high pressure resistant element, differential amplifier 200 different from the PMOS P1P in differential amplifier 100 and P1N
PMOS P2P and P2N is core parts.Therefore, component symbol of the PMOS P1P and P1N component symbol with PMOS P2P and P2N
It is different.
Buffer stage 300 has two simple buffers, and its input is connected respectively to differential output Vo2+ and Vo2-, according to
To produce signal on signal output part Vout+ and Vout-.For example, each buffer is the reverser of two concatenations
Constituted, each reverser is constituted with core parts.
Fig. 4 shows the embodiment of the current source S1 and S2 in Fig. 3.Operational amplifier OP, PMOS PSC, resistance Res can be with
Electric current Iref is determined in generation, and its value is approximately equal to digital circuit power source line VDDdigital magnitude of voltage divided by resistance Res resistance value.
PMOS PS0, PS1, PS2 then constitute a current mirror, and will determine electric current Iref difference mirror images (mirror) is tail current It1 and It2.
In broad terms, PMOS PS1 and PS2 can be considered as current source S1 and S2.In this embodiment, PMOS PSC, PS0, PS1 and PS2
All it is high pressure resistant element.
Fig. 3 signal receiver RV has well-to-do input voltage range, can receive to meet DDR2 1.8V signal,
DDR4 1.2V signal can also be received to meet.Because employ can high voltage bearing high pressure resistant member for differential amplifier 100
Part and passive type resistance.Moreover, differential amplifier 100 can limit its voltage swing on differential output Vo1+ and Vo1-
Size, therefore, the core parts employed in differential amplifier 200 will not suffer damage.Differential amplifier 200 can be designed
When differential output Vo1+ and Vo1- output common-mode voltages, high-gain is enjoyed, the voltage conversion of differential amplifier 200 is improved
Speed (slew rate).
In general, the high speed DDR input signal amplitude of oscillation (signal swing) can be with the signal model of its band
(signal pattern) is different and has sizable difference.The signal propagation delay produced to reduce the unlike signal amplitude of oscillation
Time difference, high voltage switching rate is generally a preferably solution.Differential amplifier 200 employs high-gain
Core parts, and the appropriate voltage swing size for limiting its differential output Vo2+ and Vo2-, to reach high voltage switching rate
And produce the purpose of the output signal of full width (full-swing).Core parts are used in differential amplifier 200 and passive
Resistance, can effectively obtain an equalization point between gain, output voltage swing scope and power consumption.
For example, because using the high pressure resistant element of low gain, the voltage gain of differential amplifier 100 may only have 2；
Relative, the voltage gain of differential amplifier 200 is probably 10.Now, as long as the signal swing of DDR input signal has
55mV, the output signal amplitude of oscillation of that differential amplifier 200 can just have 1.1V, as the full width signal in core circuit.
With the drift of manufacture of semiconductor, the signal propagation delay time also can be with difference；And such difference, also can be with
The number increase of amplifier series and increase.Amplifier stage in signal receiver RV keeps count of only two, it is possible to
Effective limitation is because of the signal propagation delay time-variance caused by process drift.
In the example in figure 3, the differential amplifier 100 and 200 in signal receiver RV, and buffer stage 300 are belonged to
Output/input circuit, but the invention is not restricted to this.In another embodiment, only differential amplifier 100 and 200 is to belong to output
Enter circuit, and buffer stage 300 belongs to core circuit.In another embodiment, only differential amplifier 100 belongs to import and export electricity
Road, and differential amplifier 200 belongs to core circuit with buffer stage 300.
Although the present invention is disclosed as above with preferred embodiment, so it is not limited to the present invention, any this area skill
Art personnel, without departing from the spirit and scope of the present invention, when a little modification can be made and perfect, therefore the protection model of the present invention
Enclose when by being defined that claims are defined.
Claims (8)
1. a kind of signal receiver, includes a first order amplifier and a second level amplifier, the second level amplifier is one
Core circuit；
The first order amplifier, includes：
One current source is there is provided an electric current, with a current value；
One input active component pair, each input active component has a control end, one first conduction terminals and one second conduction
Hold, one of two control ends of the input active component pair receive an input signal, two the first conduction terminals are connected to one
Rise and receive the electric current, two second conduction terminals are two first order output ends, and the input active component is to being according to the electricity
Stream outputs signal to the second level amplifier with input signal output one；And
One resistance pair, each resistance has a resistance value, is connected to one of two second conduction terminals and a power line
Between；
Wherein, the resistance value determines a target voltage values with the current value, so that the voltage swing of the output signal is not more than this
Target voltage values, and then an operating voltage of the core circuit is equal to the target voltage values；
The second level amplifier, includes：
There is provided another electric current for another current source；
It is another input active component pair, this it is another input active component centering each input active component have a control end,
One first conduction terminals and one second conduction terminals, two the first conduction terminals of another input active component pair link together,
Two control ends of another input active component pair are respectively connecting to two first order output ends；And
Another resistance pair, each resistance of another resistance centering has another resistance value, and being connected to another input has
One of two second conduction terminals of source element pair are between the power line；
Wherein, one of two second conduction terminals of another input active component pair another output signal of output, this is another
One resistance value and the product of another electric current are equal to the operating voltage.
2. signal receiver as claimed in claim 1, it is characterised in that the signal receiver is formed in an integrated circuit, should
Integrated circuit has multiple core parts and multiple high pressure resistant elements, and the plurality of high pressure resistant element has than the plurality of core parts
High voltage tolerance, the input active component is to being high pressure resistant element.
3. signal receiver as claimed in claim 1, it is characterised in that the signal receiver is formed in an integrated circuit, should
Integrated circuit has multiple core parts and multiple high pressure resistant elements, and the plurality of high pressure resistant more the plurality of core parts of element have
High voltage tolerance, the input active component is to for high pressure resistant element, and another input active component is to for core parts.
4. the as claimed in claim 1 signal receiver, it is characterised in that first and second grade of amplifier have respectively first with
Second voltage gain, the second voltage gain is more than the first voltage gain, and the first voltage gain is more than 1.
5. signal receiver as claimed in claim 1, it is characterised in that the power line is a low analog circuit power line, and is somebody's turn to do
Current source is connected between the input active component pair and a high analog circuit power line, wherein, the high analog circuit power line
With the voltage difference between the low analog circuit power line, higher than the operating voltage.
6. signal receiver as claimed in claim 1, it is characterised in that two control ends of the input active component pair are wherein
Another be coupled to a reference voltage.
7. signal receiver as claimed in claim 1, it is characterised in that two control ends of the input active component pair are wherein
Another input signal of another reception, two input signal constitutes a differential wave.
8. signal receiver as claimed in claim 1, it is characterised in that the current source includes a current mirror, and it includes number
Individual high pressure resistant element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310348238.9A CN104347102B (en) | 2013-08-09 | 2013-08-09 | Signal receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310348238.9A CN104347102B (en) | 2013-08-09 | 2013-08-09 | Signal receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104347102A CN104347102A (en) | 2015-02-11 |
| CN104347102B true CN104347102B (en) | 2017-08-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310348238.9A Expired - Fee Related CN104347102B (en) | 2013-08-09 | 2013-08-09 | Signal receiver |
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| Country | Link |
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| CN (1) | CN104347102B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10163465B1 (en) * | 2017-08-18 | 2018-12-25 | Novatek Microelectronics Corp. | Data receiver and controller for DDR memory |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102684619A (en) * | 2011-03-07 | 2012-09-19 | Nxp股份有限公司 | Amplifier circuit and method |
-
2013
- 2013-08-09 CN CN201310348238.9A patent/CN104347102B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102684619A (en) * | 2011-03-07 | 2012-09-19 | Nxp股份有限公司 | Amplifier circuit and method |
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| Publication number | Publication date |
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| CN104347102A (en) | 2015-02-11 |
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Effective date of registration: 20200414 Address after: No.1, Duhang 1st Road, Hsinchu City, Hsinchu Science Park, Taiwan, China Patentee after: MEDIATEK Inc. Address before: Taiwan Hsinchu County Tai Yuan Street China jhubei City, No. 26 4 floor 1 Patentee before: MSTAR SEMICONDUCTOR Inc. |
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Granted publication date: 20170804 |