CN104332489A - Terminal with surface super-structure and of semiconductor device - Google Patents
Terminal with surface super-structure and of semiconductor device Download PDFInfo
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- CN104332489A CN104332489A CN201410578556.9A CN201410578556A CN104332489A CN 104332489 A CN104332489 A CN 104332489A CN 201410578556 A CN201410578556 A CN 201410578556A CN 104332489 A CN104332489 A CN 104332489A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000012535 impurity Substances 0.000 claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 9
- 239000012212 insulator Substances 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 13
- 238000009826 distribution Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention belongs to the technical field of semiconductor devices and provides a terminal with a surface super-structure and of a semiconductor device. Accordingly, the semiconductor devices can be good in pressure resistance and stability. The manufacturing process of the devices need to be simplified and the pressure resistance of the devices need to be improved in the prior art. The surface super-structure is formed by a plurality of P type impurity areas and a plurality of N type impurity areas through alternate arrangement. The terminal is characterized in that the surface super-structure is located on the surface of the device chip terminal and every P type impurity area and every N type impurity area extend from the active area boundary to the edge of the chip. According to the terminal with the surface super-structure and of the semiconductor device, the surface electric field intensity of the semiconductor device chip terminal can be reduced, the pressure-proof capability of the unit width of the chip terminal is significantly improved, the pressure resistance can even be equivalent to that of an insulator, and meanwhile the manufacturing process of the surface super-structure is general and simple.
Description
Technical field
The present invention relates to a kind of terminal with surperficial super-junction structures of semiconductor device, be specifically related to the terminal structure of semiconductor device, this terminal structure makes semiconductor device have good withstand voltage and stability, belongs to technical field of semiconductor device.
Background technology
In the terminal structure of device chip, device is along with the increase of reversed bias voltage, and depletion region is expanded to the both sides of PN junction, high electric field is there is in terminal end surface, reduce device withstand voltage, along with the raising that terminal end surface PN junction quantity increases and PN junction is withstand voltage, surface electric field distribution is just more complicated.Prior art reduces device chip terminal surface field intensity by terminal structure design, improves the puncture voltage close to the parallel PN junction of device inside, thus improves the withstand voltage properties of device.Existing semiconductor device terminal technology relevant therewith comprises field plate termination technology, JTE (knot terminal extends) terminal technology, VLD (variety lateral doping) terminal technology and field limiting ring terminal technology.
Resistive field plate technology in field plate termination technology adopts oxygen-doped polysilicon (SIPOS) as the resistive field plate of device, device is when reverse-biased, rise from active area to the Potential distribution approximately linear device chip edge polysilicon, and device chip terminal silicon interface place Potential distribution rises faster.So just obtain two favourable results: (1) makes the electric-field intensity distribution on device chip surface become smooth; (2) field plate current potential is at any one all lower than Si surface, and this is favourable to increase surface PN junction width of depletion region.Therefore, puncture voltage is improved.But oxygen-doped polysilicon resistance field plate complex manufacturing technology, as needs increase polysilicon layer depositing technics, and procedure parameter in producing is wayward, as oxygen-doped ratio.
In JTE terminal technology, VLD terminal technology, because surface concentration is lower, effects on surface charge ratio is more responsive, and easily by the impact of interface charge, device stability is affected.
In field limiting ring terminal technology, in order to improve the withstand voltage of semiconductor device, the terminal structure of existing semiconductor device is generally the combination of field limiting ring and floating field plate.
Therefore the terminal technology of the more efficiently raising device withstand voltage performance of searching one is needed.
Summary of the invention
In order to simplify device making technics, improving device withstand voltage performance, we have invented a kind of terminal with surperficial super-junction structures of semiconductor device.
The present invention semiconductor device have in the terminal of surperficial super-junction structures, described surperficial super-junction structures is alternately arranged by multiple p type impurity district and N-type impurity district and forms, it is characterized in that, described surperficial super-junction structures is positioned at device chip terminal 1 surface, each p type impurity district 2, N-type impurity district 3 extend to chip edge 5 from border, active area 4, as shown in figures 1-4.
Its technique effect of the present invention is, due to surperficial super-junction structures (Surface Super Junction, be called for short SCSJ) withstand voltage mechanism different from common PN junction, surface super-junction structures is after reverse-biased, peak electric field moves to the two ends of surperficial super-junction structures, super interface surface electric field distribution in the super-junction structures of surface is even, in fact a uniform Withstand voltage layer of Electric Field Distribution is formed in device chip terminal end surface from border, active area to chip edge, two ends due to this Withstand voltage layer are the chip edges on border, chip active district, surface field is farthest launched, reduce the intensity of surface field.Semiconductor current potential under terminal end surface is less than the current potential on terminal end surface top layer, therefore, the also expansion under the pullling of terminal end surface of chip depletion region, make surface field intensity distributions further level and smooth, intensity reduce further, the withstand voltage level of chip terminal unit width is improved significantly, and voltage endurance capability even can be equivalent to insulator.Because the formation p type impurity district of super-junction structures and the impurity concentration in N-type impurity district can reach very high degree, so this surperficial super-junction structures effects on surface electric charge is insensitive, device withstand voltage is stablized.Further, by changing chip terminal width, the namely length of super junction, just can adjusting device withstand voltage, this measure is convenient, simply.Meanwhile, the technique making surperficial super-junction structures is very conventional and simple.
From another viewpoint, the present invention while the withstand voltage level not reducing device, can also reduce chip terminal size, reduces the sensitiveness to interface charge, improves the withstand voltage stability of device.
Accompanying drawing explanation
Fig. 1 is the terminal structure schematic top plan view with surperficial super-junction structures of the present invention, and this figure is simultaneously as Figure of abstract.Fig. 2 is the structure schematic top plan view with the chip four corners of the terminal of surperficial super-junction structures of the present invention, and this figure represents simultaneously and extends to chip edge from border, active area with radial manner in each p type impurity district of rectangular dies four corners position, N-type impurity district.Fig. 3 be the present invention there is surperficial super-junction structures sectional perspective schematic diagram.Fig. 4 be the present invention there is surperficial super-junction structures partial schematic sectional view.Fig. 5 is the structure schematic top plan view with the chip four corners of the terminal of surperficial super-junction structures of the present invention, and this figure represents simultaneously and extends to chip edge along rectangular dies diagonal from border, active area in rectangular dies four corners position p type impurity district.
Embodiment
The present invention semiconductor device have in the terminal of surperficial super-junction structures, described surperficial super-junction structures is alternately arranged by multiple p type impurity district and N-type impurity district and forms.Described surperficial super-junction structures is positioned at device chip terminal 1 surface, and each p type impurity district 2, N-type impurity district 3 extend to chip edge 5 from border, active area 4, as shown in figures 1-4.The production method of described surperficial super-junction structures is the diffusion of photoetching selectivity, one of cutting doping and cutting extension three kinds of modes.Each p type impurity district 2 of described surperficial super-junction structures, the impurity concentration in N-type impurity district 3, width and the degree of depth are optimized and revised according to RESURF method.P type impurity district 2 is equal with the width in N-type impurity district 3 or unequal.Time unequal with the width in N-type impurity district 3 when p type impurity district 2, the width in p type impurity district 2 is greater than or less than the width in N-type impurity district 3.The deep equality in p type impurity district 2 and N-type impurity district 3 or unequal.Time unequal with the degree of depth in N-type impurity district 3 when p type impurity district 2, the degree of depth in p type impurity district 2 is greater than or less than the degree of depth in N-type impurity district 3.
At rectangular dies four corners position, each p type impurity district 2 in described surperficial super-junction structures, N-type impurity district 3 extend to chip edge 5 extension form from border, active area 4 is one of following two kinds:
1, radially extend centered by rectangular dies geometric center, as shown in Figure 2.If will be from border, active area 4 to the distance definition of chip edge 5 width of described surperficial super-junction structures, so, the width that described surperficial super-junction structures is positioned at the part of rectangular dies four corners position is greater than or equal to the width that described surperficial super-junction structures is positioned at the part of rectangular dies four edge position.Because the electric field strength in rectangular dies corner is comparatively large, when described wide association is for being greater than, be conducive to the reduction of electric field strength, and then improve the withstand voltage level of chip.
2, a p type impurity district 2 extends along rectangular dies diagonal, and as shown in Figure 5, in this branch of Ge Youyizu p type impurity district 2, both sides, p type impurity district 2, other p type impurity districts 2 of trend and this side of branch of Mei Zu p type impurity district 2 move towards parallel.Being distributed with to be beneficial to of rule like this realizes charge balance, improves device chip terminal withstand voltage properties.
Claims (8)
1. the terminal with surperficial super-junction structures of a semiconductor device, described surperficial super-junction structures is alternately arranged by multiple p type impurity district and N-type impurity district and forms, it is characterized in that, described surperficial super-junction structures is positioned at device chip terminal (1) surface, and each p type impurity district (2), N-type impurity district (3) extend to chip edge (5) from border, active area (4).
2. the terminal with surperficial super-junction structures of semiconductor device according to claim 1, is characterized in that, the production method of described surperficial super-junction structures is the diffusion of photoetching selectivity, one of cutting doping and cutting extension three kinds of modes.
3. the terminal with surperficial super-junction structures of semiconductor device according to claim 1, it is characterized in that, each p type impurity district (2) of described surperficial super-junction structures, the impurity concentration of N-type impurity district (3), width and the degree of depth are optimized and revised according to RESURF method.
4. the terminal with surperficial super-junction structures of semiconductor device according to claim 1, is characterized in that, p type impurity district (2) are equal or unequal with the width of N-type impurity district (3).
5. the terminal with surperficial super-junction structures of semiconductor device according to claim 4, it is characterized in that, time unequal with the width in N-type impurity district (3) when p type impurity district (2), the width of p type impurity district (2) is greater than or less than the width of N-type impurity district (3).
6. the terminal with surperficial super-junction structures of semiconductor device according to claim 1, is characterized in that, the deep equality in p type impurity district (2) and N-type impurity district (3) or unequal.
7. the terminal with surperficial super-junction structures of semiconductor device according to claim 6, it is characterized in that, time unequal with the degree of depth in N-type impurity district (3) when p type impurity district (2), the degree of depth of p type impurity district (2) is greater than or less than the degree of depth of N-type impurity district (3).
8. the terminal with surperficial super-junction structures of semiconductor device according to claim 1, it is characterized in that, at rectangular dies four corners position, each p type impurity district (2) in described surperficial super-junction structures, N-type impurity district (3) are one of following two kinds from the extension form that border, active area (4) extend to chip edge (5):
A, radially to extend centered by rectangular dies geometric center, distance from border, active area (4) to chip edge (5) is the width of described surperficial super-junction structures, and the width that described surperficial super-junction structures is positioned at the part of rectangular dies four corners position is greater than or equal to the width that described surperficial super-junction structures is positioned at the part of rectangular dies four edge position;
B, a p type impurity district (2) extend along rectangular dies diagonal, in this p type impurity district (2) both sides Ge Youyizu p type impurity district (2) branch, other p type impurity districts (2) of the trend and this side of Mei Zu p type impurity district (2) branch move towards parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410578556.9A CN104332489A (en) | 2014-10-23 | 2014-10-23 | Terminal with surface super-structure and of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410578556.9A CN104332489A (en) | 2014-10-23 | 2014-10-23 | Terminal with surface super-structure and of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| CN104332489A true CN104332489A (en) | 2015-02-04 |
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| CN201410578556.9A Pending CN104332489A (en) | 2014-10-23 | 2014-10-23 | Terminal with surface super-structure and of semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108987459A (en) * | 2018-07-25 | 2018-12-11 | 王永贵 | A kind of power device |
| CN111354780A (en) * | 2020-03-19 | 2020-06-30 | 浙江大学 | Super junction terminal with inversion injection side wall and manufacturing method thereof |
| CN115602709A (en) * | 2022-10-24 | 2023-01-13 | 上海功成半导体科技有限公司（Cn） | Super junction device terminal protection layout structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008016562A (en) * | 2006-07-04 | 2008-01-24 | Rohm Co Ltd | Semiconductor device |
| US20090236697A1 (en) * | 2008-03-24 | 2009-09-24 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| CN102569357A (en) * | 2010-12-28 | 2012-07-11 | 瑞萨电子株式会社 | Semiconductor device |
-
2014
- 2014-10-23 CN CN201410578556.9A patent/CN104332489A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008016562A (en) * | 2006-07-04 | 2008-01-24 | Rohm Co Ltd | Semiconductor device |
| US20090236697A1 (en) * | 2008-03-24 | 2009-09-24 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| CN102569357A (en) * | 2010-12-28 | 2012-07-11 | 瑞萨电子株式会社 | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108987459A (en) * | 2018-07-25 | 2018-12-11 | 王永贵 | A kind of power device |
| CN111354780A (en) * | 2020-03-19 | 2020-06-30 | 浙江大学 | Super junction terminal with inversion injection side wall and manufacturing method thereof |
| CN115602709A (en) * | 2022-10-24 | 2023-01-13 | 上海功成半导体科技有限公司（Cn） | Super junction device terminal protection layout structure |
| CN115602709B (en) * | 2022-10-24 | 2023-12-19 | 上海功成半导体科技有限公司 | Territory structure for protecting super junction device terminal |
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Application publication date: 20150204 |